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lei137lei137
committedMay 24, 2018
[PowerPC] Remove the match pattern in the definition of LXSDX/STXSDX
The match pattern in the definition of LXSDX is xoaddr, so the Pseudo instruction XFLOADf64 never gets selected. XFLOADf64 expands to LXSDX/LFDX post RA based on the register pressure. To avoid ambiguity, we need to remove the select pattern for LXSDX, same as what was done for LXSD. STXSDX also have the same issue. Patch by Qing Shan Zhang (steven.zhang). Differential Revision: https://reviews.llvm.org/D47178 llvm-svn: 333150
·
llvmorg-21-initllvmorg-7.0.0-rc1
1 parent 4d53b74 commit f4ec678

18 files changed

+103
-103
lines changed
 

‎llvm/lib/Target/PowerPC/PPCInstrVSX.td

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -129,7 +129,7 @@ let Uses = [RM] in {
129129
def LXSDX : XX1Form_memOp<31, 588,
130130
(outs vsfrc:$XT), (ins memrr:$src),
131131
"lxsdx $XT, $src", IIC_LdStLFD,
132-
[(set f64:$XT, (load xoaddr:$src))]>;
132+
[]>;
133133

134134
// Pseudo instruction XFLOADf64 will be expanded to LXSDX or LFDX later
135135
let isPseudo = 1, CodeSize = 3 in
@@ -160,7 +160,7 @@ let Uses = [RM] in {
160160
def STXSDX : XX1Form_memOp<31, 716,
161161
(outs), (ins vsfrc:$XT, memrr:$dst),
162162
"stxsdx $XT, $dst", IIC_LdStSTFD,
163-
[(store f64:$XT, xoaddr:$dst)]>;
163+
[]>;
164164

165165
// Pseudo instruction XFSTOREf64 will be expanded to STXSDX or STFDX later
166166
let isPseudo = 1, CodeSize = 3 in

‎llvm/test/CodeGen/PowerPC/bitcasts-direct-move.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ define i64 @f64toi64(double %a) {
1818
entry:
1919
%0 = bitcast double %a to i64
2020
ret i64 %0
21-
; CHECK-P7: stxsdx 1,
21+
; CHECK-P7: stfdx 1,
2222
; CHECK-P7: ld 3,
2323
; CHECK: mffprd 3, 1
2424
}
@@ -39,7 +39,7 @@ entry:
3939
%0 = bitcast i64 %a to double
4040
ret double %0
4141
; CHECK-P7: std 3,
42-
; CHECK-P7: lxsdx 1,
42+
; CHECK-P7: lfdx 1,
4343
; CHECK: mtvsrd 1, 3
4444
}
4545

@@ -58,7 +58,7 @@ define i64 @f64toi64u(double %a) {
5858
entry:
5959
%0 = bitcast double %a to i64
6060
ret i64 %0
61-
; CHECK-P7: stxsdx 1,
61+
; CHECK-P7: stfdx 1,
6262
; CHECK-P7: ld 3,
6363
; CHECK: mffprd 3, 1
6464
}
@@ -79,6 +79,6 @@ entry:
7979
%0 = bitcast i64 %a to double
8080
ret double %0
8181
; CHECK-P7: std 3,
82-
; CHECK-P7: lxsdx 1,
82+
; CHECK-P7: lfdx 1,
8383
; CHECK: mtvsrd 1, 3
8484
}

‎llvm/test/CodeGen/PowerPC/branch_coalesce.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -15,8 +15,8 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
1515
; CHECK-NOT: beq
1616
; CHECK-DAG: addi [[LD1BASE:[0-9]+]], [[LD1REG]]
1717
; CHECK-DAG: addi [[LD2BASE:[0-9]+]], [[LD2REG]]
18-
; CHECK-DAG: lxsdx 1, 0, [[LD1BASE]]
19-
; CHECK-DAG: lxsdx 3, 0, [[LD2BASE]]
18+
; CHECK-DAG: lfdx 1, 0, [[LD1BASE]]
19+
; CHECK-DAG: lfdx 3, 0, [[LD2BASE]]
2020
; CHECK: .LBB[[LAB1]]
2121
; CHECK: xsadddp 0, 1, 2
2222
; CHECK: xsadddp 1, 0, 3
@@ -33,15 +33,15 @@ define double @testBranchCoal(double %a, double %b, double %c, i32 %x) {
3333
; CHECK-NOCOALESCE-NEXT: .LBB0_3: # %entry
3434
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_1@toc@ha
3535
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_1@toc@l
36-
; CHECK-NOCOALESCE-NEXT: lxsdx 3, 0, 3
36+
; CHECK-NOCOALESCE-NEXT: lfdx 3, 0, 3
3737
; CHECK-NOCOALESCE-NEXT: .LBB0_4: # %entry
3838
; CHECK-NOCOALESCE-NEXT: xsadddp 0, 1, 2
3939
; CHECK-NOCOALESCE-NEXT: xsadddp 1, 0, 3
4040
; CHECK-NOCOALESCE-NEXT: blr
4141
; CHECK-NOCOALESCE-NEXT: .LBB0_5: # %entry
4242
; CHECK-NOCOALESCE-NEXT: addis 3, 2, .LCPI0_0@toc@ha
4343
; CHECK-NOCOALESCE-NEXT: addi 3, 3, .LCPI0_0@toc@l
44-
; CHECK-NOCOALESCE-NEXT: lxsdx 1, 0, 3
44+
; CHECK-NOCOALESCE-NEXT: lfdx 1, 0, 3
4545
; CHECK-NOCOALESCE-NEXT: beq 0, .LBB0_2
4646
; CHECK-NOCOALESCE-NEXT: .LBB0_6: # %entry
4747
; CHECK-NOCOALESCE-NEXT: xxlxor 2, 2, 2

‎llvm/test/CodeGen/PowerPC/build-vector-tests.ll

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -1667,20 +1667,20 @@ entry:
16671667
; P9LE: xvcvdpsp
16681668
; P9LE: vmrgew
16691669
; P9LE: xvcvspsxws v2
1670-
; P8BE: lxsdx
1671-
; P8BE: lxsdx
1672-
; P8BE: lxsdx
1673-
; P8BE: lxsdx
1670+
; P8BE: lfdx
1671+
; P8BE: lfd
1672+
; P8BE: lfd
1673+
; P8BE: lfd
16741674
; P8BE: xxmrghd
16751675
; P8BE: xxmrghd
16761676
; P8BE: xvcvdpsp
16771677
; P8BE: xvcvdpsp
16781678
; P8BE: vmrgew
16791679
; P8BE: xvcvspsxws v2
1680-
; P8LE: lxsdx
1681-
; P8LE: lxsdx
1682-
; P8LE: lxsdx
1683-
; P8LE: lxsdx
1680+
; P8LE: lfdx
1681+
; P8LE: lfd
1682+
; P8LE: lfd
1683+
; P8LE: lfd
16841684
; P8LE: xxmrghd
16851685
; P8LE: xxmrghd
16861686
; P8LE: xvcvdpsp
@@ -1741,19 +1741,19 @@ entry:
17411741
; P9LE: vmrgew
17421742
; P9LE: xvcvspsxws v2
17431743
; P8BE: lfdux
1744-
; P8BE: lxsdx
1745-
; P8BE: lxsdx
1746-
; P8BE: lxsdx
1744+
; P8BE: lfd
1745+
; P8BE: lfd
1746+
; P8BE: lfd
17471747
; P8BE: xxmrghd
17481748
; P8BE: xxmrghd
17491749
; P8BE: xvcvdpsp
17501750
; P8BE: xvcvdpsp
17511751
; P8BE: vmrgew
17521752
; P8BE: xvcvspsxws v2
17531753
; P8LE: lfdux
1754-
; P8LE: lxsdx
1755-
; P8LE: lxsdx
1756-
; P8LE: lxsdx
1754+
; P8LE: lfd
1755+
; P8LE: lfd
1756+
; P8LE: lfd
17571757
; P8LE: xxmrghd
17581758
; P8LE: xxmrghd
17591759
; P8LE: xvcvdpsp
@@ -1814,19 +1814,19 @@ entry:
18141814
; P9LE: vmrgew
18151815
; P9LE: xvcvspsxws v2
18161816
; P8BE: lfdux
1817-
; P8BE: lxsdx
1818-
; P8BE: lxsdx
1819-
; P8BE: lxsdx
1817+
; P8BE: lfd
1818+
; P8BE: lfd
1819+
; P8BE: lfd
18201820
; P8BE: xxmrghd
18211821
; P8BE: xxmrghd
18221822
; P8BE: xvcvdpsp
18231823
; P8BE: xvcvdpsp
18241824
; P8BE: vmrgew
18251825
; P8BE: xvcvspsxws v2
18261826
; P8LE: lfdux
1827-
; P8LE: lxsdx
1828-
; P8LE: lxsdx
1829-
; P8LE: lxsdx
1827+
; P8LE: lfd
1828+
; P8LE: lfd
1829+
; P8LE: lfd
18301830
; P8LE: xxmrghd
18311831
; P8LE: xxmrghd
18321832
; P8LE: xvcvdpsp
@@ -2827,20 +2827,20 @@ entry:
28272827
; P9LE: xvcvdpsp
28282828
; P9LE: vmrgew
28292829
; P9LE: xvcvspuxws v2
2830-
; P8BE: lxsdx
2831-
; P8BE: lxsdx
2832-
; P8BE: lxsdx
2833-
; P8BE: lxsdx
2830+
; P8BE: lfdx
2831+
; P8BE: lfd
2832+
; P8BE: lfd
2833+
; P8BE: lfd
28342834
; P8BE: xxmrghd
28352835
; P8BE: xxmrghd
28362836
; P8BE: xvcvdpsp
28372837
; P8BE: xvcvdpsp
28382838
; P8BE: vmrgew
28392839
; P8BE: xvcvspuxws v2
2840-
; P8LE: lxsdx
2841-
; P8LE: lxsdx
2842-
; P8LE: lxsdx
2843-
; P8LE: lxsdx
2840+
; P8LE: lfdx
2841+
; P8LE: lfd
2842+
; P8LE: lfd
2843+
; P8LE: lfd
28442844
; P8LE: xxmrghd
28452845
; P8LE: xxmrghd
28462846
; P8LE: xvcvdpsp
@@ -2901,19 +2901,19 @@ entry:
29012901
; P9LE: vmrgew
29022902
; P9LE: xvcvspuxws v2
29032903
; P8BE: lfdux
2904-
; P8BE: lxsdx
2905-
; P8BE: lxsdx
2906-
; P8BE: lxsdx
2904+
; P8BE: lfd
2905+
; P8BE: lfd
2906+
; P8BE: lfd
29072907
; P8BE: xxmrghd
29082908
; P8BE: xxmrghd
29092909
; P8BE: xvcvdpsp
29102910
; P8BE: xvcvdpsp
29112911
; P8BE: vmrgew
29122912
; P8BE: xvcvspuxws v2
29132913
; P8LE: lfdux
2914-
; P8LE: lxsdx
2915-
; P8LE: lxsdx
2916-
; P8LE: lxsdx
2914+
; P8LE: lfd
2915+
; P8LE: lfd
2916+
; P8LE: lfd
29172917
; P8LE: xxmrghd
29182918
; P8LE: xxmrghd
29192919
; P8LE: xvcvdpsp
@@ -2974,19 +2974,19 @@ entry:
29742974
; P9LE: vmrgew
29752975
; P9LE: xvcvspuxws v2
29762976
; P8BE: lfdux
2977-
; P8BE: lxsdx
2978-
; P8BE: lxsdx
2979-
; P8BE: lxsdx
2977+
; P8BE: lfd
2978+
; P8BE: lfd
2979+
; P8BE: lfd
29802980
; P8BE: xxmrghd
29812981
; P8BE: xxmrghd
29822982
; P8BE: xvcvdpsp
29832983
; P8BE: xvcvdpsp
29842984
; P8BE: vmrgew
29852985
; P8BE: xvcvspuxws v2
29862986
; P8LE: lfdux
2987-
; P8LE: lxsdx
2988-
; P8LE: lxsdx
2989-
; P8LE: lxsdx
2987+
; P8LE: lfd
2988+
; P8LE: lfd
2989+
; P8LE: lfd
29902990
; P8LE: xxmrghd
29912991
; P8LE: xxmrghd
29922992
; P8LE: xvcvdpsp

‎llvm/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,7 @@ entry:
1717
%this.addr = alloca %SomeStruct*, align 8
1818
%V.addr = alloca double, align 8
1919
store %SomeStruct* %this, %SomeStruct** %this.addr, align 8
20-
; ELF64VSX: stxsdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
20+
; ELF64VSX: stfdx {{[0-9][0-9]?}}, 0, {{[1-9][0-9]?}}
2121
store double %V, double* %V.addr, align 8
2222
%this1 = load %SomeStruct*, %SomeStruct** %this.addr
2323
%Val = getelementptr inbounds %SomeStruct, %SomeStruct* %this1, i32 0, i32 0

‎llvm/test/CodeGen/PowerPC/float-to-int.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@ define i64 @foo(float %a) nounwind {
2121

2222
; CHECK-VSX: @foo
2323
; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
24-
; CHECK-VSX: stxsdx [[REG]],
24+
; CHECK-VSX: stfdx [[REG]],
2525
; CHECK-VSX: ld 3,
2626
; CHECK-VSX: blr
2727

@@ -44,7 +44,7 @@ define i64 @foo2(double %a) nounwind {
4444

4545
; CHECK-VSX: @foo2
4646
; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1
47-
; CHECK-VSX: stxsdx [[REG]],
47+
; CHECK-VSX: stfdx [[REG]],
4848
; CHECK-VSX: ld 3,
4949
; CHECK-VSX: blr
5050

@@ -67,7 +67,7 @@ define i64 @foo3(float %a) nounwind {
6767

6868
; CHECK-VSX: @foo3
6969
; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
70-
; CHECK-VSX: stxsdx [[REG]],
70+
; CHECK-VSX: stfdx [[REG]],
7171
; CHECK-VSX: ld 3,
7272
; CHECK-VSX: blr
7373

@@ -90,7 +90,7 @@ define i64 @foo4(double %a) nounwind {
9090

9191
; CHECK-VSX: @foo4
9292
; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1
93-
; CHECK-VSX: stxsdx [[REG]],
93+
; CHECK-VSX: stfdx [[REG]],
9494
; CHECK-VSX: ld 3,
9595
; CHECK-VSX: blr
9696

‎llvm/test/CodeGen/PowerPC/fp128-bitcast-after-operation.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7,8 +7,8 @@
77
define i128 @test_abs(ppc_fp128 %x) nounwind {
88
entry:
99
; PPC64-LABEL: test_abs:
10-
; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
11-
; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
10+
; PPC64-DAG: stfdx 2, 0, [[ADDR_HI:[0-9]+]]
11+
; PPC64-DAG: stfdx 1, 0, [[ADDR_LO:[0-9]+]]
1212
; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
1313
; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
1414
; PPC64-DAG: ld [[HI:[0-9]+]], [[OFFSET_LO]]([[SP]])
@@ -45,8 +45,8 @@ entry:
4545
define i128 @test_neg(ppc_fp128 %x) nounwind {
4646
entry:
4747
; PPC64-LABEL: test_neg:
48-
; PPC64-DAG: stxsdx 2, 0, [[ADDR_HI:[0-9]+]]
49-
; PPC64-DAG: stxsdx 1, 0, [[ADDR_LO:[0-9]+]]
48+
; PPC64-DAG: stfdx 2, 0, [[ADDR_HI:[0-9]+]]
49+
; PPC64-DAG: stfdx 1, 0, [[ADDR_LO:[0-9]+]]
5050
; PPC64-DAG: addi [[ADDR_HI]], [[SP:[0-9]+]], [[OFFSET_HI:-?[0-9]+]]
5151
; PPC64-DAG: addi [[ADDR_LO]], [[SP]], [[OFFSET_LO:-?[0-9]+]]
5252
; PPC64-DAG: li [[FLIP_BIT:[0-9]+]], 1
@@ -87,7 +87,7 @@ entry:
8787
define i128 @test_copysign(ppc_fp128 %x) nounwind {
8888
entry:
8989
; PPC64-LABEL: test_copysign:
90-
; PPC64-DAG: stxsdx 1, 0, [[ADDR_REG:[0-9]+]]
90+
; PPC64-DAG: stfdx 1, 0, [[ADDR_REG:[0-9]+]]
9191
; PPC64-DAG: addi [[ADDR_REG]], 1, [[OFFSET:-?[0-9]+]]
9292
; PPC64-DAG: li [[HI_TMP:[0-9]+]], 16399
9393
; PPC64-DAG: sldi [[CST_HI:[0-9]+]], [[HI_TMP]], 48

‎llvm/test/CodeGen/PowerPC/i64-to-float.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@ entry:
2020

2121
; CHECK-VSX: @foo
2222
; CHECK-VSX: std 3,
23-
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
23+
; CHECK-VSX: lfdx [[REG:[0-9]+]],
2424
; CHECK-VSX: fcfids 1, [[REG]]
2525
; CHECK-VSX: blr
2626

@@ -44,7 +44,7 @@ entry:
4444

4545
; CHECK-VSX: @goo
4646
; CHECK-VSX: std 3,
47-
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
47+
; CHECK-VSX: lfdx [[REG:[0-9]+]],
4848
; CHECK-VSX: xscvsxddp 1, [[REG]]
4949
; CHECK-VSX: blr
5050

@@ -68,7 +68,7 @@ entry:
6868

6969
; CHECK-VSX: @foou
7070
; CHECK-VSX: std 3,
71-
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
71+
; CHECK-VSX: lfdx [[REG:[0-9]+]],
7272
; CHECK-VSX: fcfidus 1, [[REG]]
7373
; CHECK-VSX: blr
7474

@@ -92,7 +92,7 @@ entry:
9292

9393
; CHECK-VSX: @goou
9494
; CHECK-VSX: std 3,
95-
; CHECK-VSX: lxsdx [[REG:[0-9]+]],
95+
; CHECK-VSX: lfdx [[REG:[0-9]+]],
9696
; CHECK-VSX: xscvuxddp 1, [[REG]]
9797
; CHECK-VSX: blr
9898

‎llvm/test/CodeGen/PowerPC/mcm-12.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ entry:
2727
; CHECK-VSX-LABEL: test_double_const:
2828
; CHECK-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
2929
; CHECK-VSX: addi [[REG1]], {{[0-9]+}}, [[VAR]]@toc@l
30-
; CHECK-VSX: lxsdx {{[0-9]+}}, 0, [[REG1]]
30+
; CHECK-VSX: lfdx {{[0-9]+}}, 0, [[REG1]]
3131

3232
; CHECK-P9: [[VAR:[a-z0-9A-Z_.]+]]:
3333
; CHECK-P9: .quad 4562098671269285104

‎llvm/test/CodeGen/PowerPC/mcm-4.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,7 +34,7 @@ entry:
3434
; MEDIUM-VSX-LABEL: test_double_const:
3535
; MEDIUM-VSX: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
3636
; MEDIUM-VSX: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
37-
; MEDIUM-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
37+
; MEDIUM-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
3838

3939
; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
4040
; LARGE: .quad 4562098671269285104
@@ -48,7 +48,7 @@ entry:
4848
; LARGE-VSX-LABEL: test_double_const:
4949
; LARGE-VSX: addis [[REG1:[0-9]+]], 2, [[VAR2:[a-z0-9A-Z_.]+]]@toc@ha
5050
; LARGE-VSX: ld [[REG2:[0-9]+]], [[VAR2]]@toc@l([[REG1]])
51-
; LARGE-VSX: lxsdx {{[0-9]+}}, 0, [[REG2]]
51+
; LARGE-VSX: lfdx {{[0-9]+}}, 0, [[REG2]]
5252

5353
; MEDIUM-P9: [[VAR:[a-z0-9A-Z_.]+]]:
5454
; MEDIUM-P9: .quad 4562098671269285104

‎llvm/test/CodeGen/PowerPC/ppc64-align-long-double.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -46,8 +46,8 @@ entry:
4646
; CHECK-VSX-DAG: std 6, -8(1)
4747
; CHECK-VSX-DAG: addi [[REG1:[0-9]+]], 1, -16
4848
; CHECK-VSX-DAG: addi 3, 1, -8
49-
; CHECK-VSX: lxsdx 1, 0, [[REG1]]
50-
; CHECK-VSX: lxsdx 2, 0, 3
49+
; CHECK-VSX: lfdx 1, 0, [[REG1]]
50+
; CHECK-VSX: lfdx 2, 0, 3
5151

5252
; FIXME-VSX: addi 4, 1, 48
5353
; FIXME-VSX: lxsdx 1, 4, 3

‎llvm/test/CodeGen/PowerPC/pr30715.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -67,7 +67,7 @@ for.body: ; preds = %for.body.preheader,
6767
%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
6868
%exitcond = icmp eq i64 %indvars.iv.next, %wide.trip.count
6969
br i1 %exitcond, label %for.cond.cleanup.loopexit, label %for.body
70-
; CHECK: stxsdx
70+
; CHECK: stfdx
7171
; CHECK: lxvd2x
7272
}
7373

‎llvm/test/CodeGen/PowerPC/select_const.ll

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -652,7 +652,7 @@ define double @sel_constants_fadd_constant(i1 %cond) {
652652
; ISEL-NEXT: addi 4, 4, .LCPI34_0@toc@l
653653
; ISEL-NEXT: addi 3, 3, .LCPI34_1@toc@l
654654
; ISEL-NEXT: isel 3, 3, 4, 1
655-
; ISEL-NEXT: lxsdx 1, 0, 3
655+
; ISEL-NEXT: lfdx 1, 0, 3
656656
; ISEL-NEXT: blr
657657
;
658658
; NO_ISEL-LABEL: sel_constants_fadd_constant:
@@ -667,7 +667,7 @@ define double @sel_constants_fadd_constant(i1 %cond) {
667667
; NO_ISEL-NEXT: ori 3, 4, 0
668668
; NO_ISEL-NEXT: b .LBB34_2
669669
; NO_ISEL-NEXT: .LBB34_2:
670-
; NO_ISEL-NEXT: lxsdx 1, 0, 3
670+
; NO_ISEL-NEXT: lfdx 1, 0, 3
671671
; NO_ISEL-NEXT: blr
672672
%sel = select i1 %cond, double -4.0, double 23.3
673673
%bo = fadd double %sel, 5.1
@@ -683,7 +683,7 @@ define double @sel_constants_fsub_constant(i1 %cond) {
683683
; ISEL-NEXT: addi 4, 4, .LCPI35_0@toc@l
684684
; ISEL-NEXT: addi 3, 3, .LCPI35_1@toc@l
685685
; ISEL-NEXT: isel 3, 3, 4, 1
686-
; ISEL-NEXT: lxsdx 1, 0, 3
686+
; ISEL-NEXT: lfdx 1, 0, 3
687687
; ISEL-NEXT: blr
688688
;
689689
; NO_ISEL-LABEL: sel_constants_fsub_constant:
@@ -698,7 +698,7 @@ define double @sel_constants_fsub_constant(i1 %cond) {
698698
; NO_ISEL-NEXT: ori 3, 4, 0
699699
; NO_ISEL-NEXT: b .LBB35_2
700700
; NO_ISEL-NEXT: .LBB35_2:
701-
; NO_ISEL-NEXT: lxsdx 1, 0, 3
701+
; NO_ISEL-NEXT: lfdx 1, 0, 3
702702
; NO_ISEL-NEXT: blr
703703
%sel = select i1 %cond, double -4.0, double 23.3
704704
%bo = fsub double %sel, 5.1
@@ -714,7 +714,7 @@ define double @sel_constants_fmul_constant(i1 %cond) {
714714
; ISEL-NEXT: addi 4, 4, .LCPI36_0@toc@l
715715
; ISEL-NEXT: addi 3, 3, .LCPI36_1@toc@l
716716
; ISEL-NEXT: isel 3, 3, 4, 1
717-
; ISEL-NEXT: lxsdx 1, 0, 3
717+
; ISEL-NEXT: lfdx 1, 0, 3
718718
; ISEL-NEXT: blr
719719
;
720720
; NO_ISEL-LABEL: sel_constants_fmul_constant:
@@ -729,7 +729,7 @@ define double @sel_constants_fmul_constant(i1 %cond) {
729729
; NO_ISEL-NEXT: ori 3, 4, 0
730730
; NO_ISEL-NEXT: b .LBB36_2
731731
; NO_ISEL-NEXT: .LBB36_2:
732-
; NO_ISEL-NEXT: lxsdx 1, 0, 3
732+
; NO_ISEL-NEXT: lfdx 1, 0, 3
733733
; NO_ISEL-NEXT: blr
734734
%sel = select i1 %cond, double -4.0, double 23.3
735735
%bo = fmul double %sel, 5.1
@@ -745,7 +745,7 @@ define double @sel_constants_fdiv_constant(i1 %cond) {
745745
; ISEL-NEXT: addi 4, 4, .LCPI37_0@toc@l
746746
; ISEL-NEXT: addi 3, 3, .LCPI37_1@toc@l
747747
; ISEL-NEXT: isel 3, 3, 4, 1
748-
; ISEL-NEXT: lxsdx 1, 0, 3
748+
; ISEL-NEXT: lfdx 1, 0, 3
749749
; ISEL-NEXT: blr
750750
;
751751
; NO_ISEL-LABEL: sel_constants_fdiv_constant:
@@ -760,7 +760,7 @@ define double @sel_constants_fdiv_constant(i1 %cond) {
760760
; NO_ISEL-NEXT: ori 3, 4, 0
761761
; NO_ISEL-NEXT: b .LBB37_2
762762
; NO_ISEL-NEXT: .LBB37_2:
763-
; NO_ISEL-NEXT: lxsdx 1, 0, 3
763+
; NO_ISEL-NEXT: lfdx 1, 0, 3
764764
; NO_ISEL-NEXT: blr
765765
%sel = select i1 %cond, double -4.0, double 23.3
766766
%bo = fdiv double %sel, 5.1
@@ -775,7 +775,7 @@ define double @sel_constants_frem_constant(i1 %cond) {
775775
; ALL-NEXT: # %bb.1:
776776
; ALL-NEXT: addis 3, 2, .LCPI38_0@toc@ha
777777
; ALL-NEXT: addi 3, 3, .LCPI38_0@toc@l
778-
; ALL-NEXT: lxsdx 1, 0, 3
778+
; ALL-NEXT: lfdx 1, 0, 3
779779
; ALL-NEXT: blr
780780
; ALL-NEXT: .LBB38_2:
781781
; ALL-NEXT: addis 3, 2, .LCPI38_1@toc@ha

‎llvm/test/CodeGen/PowerPC/store_fptoi.ll

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -22,7 +22,7 @@ entry:
2222
; CHECK-NEXT: blr
2323

2424
; CHECK-PWR8-LABEL: dpConv2sdw
25-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
25+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
2626
; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
2727
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
2828
; CHECK-PWR8-NEXT: blr
@@ -43,7 +43,7 @@ entry:
4343
; CHECK-NEXT: blr
4444

4545
; CHECK-PWR8-LABEL: dpConv2sw
46-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
46+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
4747
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
4848
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
4949
; CHECK-PWR8-NEXT: blr
@@ -64,7 +64,7 @@ entry:
6464
; CHECK-NEXT: blr
6565

6666
; CHECK-PWR8-LABEL: dpConv2shw
67-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
67+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
6868
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
6969
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
7070
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
@@ -86,7 +86,7 @@ entry:
8686
; CHECK-NEXT: blr
8787

8888
; CHECK-PWR8-LABEL: dpConv2sb
89-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
89+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
9090
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
9191
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
9292
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
@@ -198,7 +198,7 @@ entry:
198198
; CHECK-NEXT: blr
199199

200200
; CHECK-PWR8-LABEL: dpConv2sdw_x
201-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
201+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
202202
; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
203203
; CHECK-PWR8-NEXT: xscvdpsxds [[CONV:[0-9]+]], [[LD]]
204204
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
@@ -224,7 +224,7 @@ entry:
224224
; CHECK-NEXT: blr
225225

226226
; CHECK-PWR8-LABEL: dpConv2sw_x
227-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
227+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
228228
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
229229
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
230230
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
@@ -250,7 +250,7 @@ entry:
250250
; CHECK-NEXT: blr
251251

252252
; CHECK-PWR8-LABEL: dpConv2shw_x
253-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
253+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
254254
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
255255
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
256256
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
@@ -276,7 +276,7 @@ entry:
276276
; CHECK-NEXT: blr
277277

278278
; CHECK-PWR8-LABEL: dpConv2sb_x
279-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
279+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
280280
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
281281
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
282282
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5
@@ -406,7 +406,7 @@ entry:
406406
; CHECK-NEXT: blr
407407

408408
; CHECK-PWR8-LABEL: dpConv2udw
409-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
409+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
410410
; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
411411
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 0, 4
412412
; CHECK-PWR8-NEXT: blr
@@ -427,7 +427,7 @@ entry:
427427
; CHECK-NEXT: blr
428428

429429
; CHECK-PWR8-LABEL: dpConv2uw
430-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
430+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
431431
; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
432432
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 0, 4
433433
; CHECK-PWR8-NEXT: blr
@@ -448,7 +448,7 @@ entry:
448448
; CHECK-NEXT: blr
449449

450450
; CHECK-PWR8-LABEL: dpConv2uhw
451-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
451+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
452452
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
453453
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
454454
; CHECK-PWR8-NEXT: sth [[REG]], 0(4)
@@ -470,7 +470,7 @@ entry:
470470
; CHECK-NEXT: blr
471471

472472
; CHECK-PWR8-LABEL: dpConv2ub
473-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
473+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
474474
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
475475
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
476476
; CHECK-PWR8-NEXT: stb [[REG]], 0(4)
@@ -582,7 +582,7 @@ entry:
582582
; CHECK-NEXT: blr
583583

584584
; CHECK-PWR8-LABEL: dpConv2udw_x
585-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
585+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
586586
; CHECK-PWR8: sldi [[REG:[0-9]+]], 5, 3
587587
; CHECK-PWR8-NEXT: xscvdpuxds [[CONV:[0-9]+]], [[LD]]
588588
; CHECK-PWR8-NEXT: stxsdx [[CONV]], 4, [[REG]]
@@ -608,7 +608,7 @@ entry:
608608
; CHECK-NEXT: blr
609609

610610
; CHECK-PWR8-LABEL: dpConv2uw_x
611-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
611+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
612612
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 2
613613
; CHECK-PWR8-NEXT: xscvdpuxws [[CONV:[0-9]+]], [[LD]]
614614
; CHECK-PWR8-NEXT: stfiwx [[CONV]], 4, [[REG]]
@@ -634,7 +634,7 @@ entry:
634634
; CHECK-NEXT: blr
635635

636636
; CHECK-PWR8-LABEL: dpConv2uhw_x
637-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
637+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
638638
; CHECK-PWR8-NEXT: sldi [[REG:[0-9]+]], 5, 1
639639
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
640640
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
@@ -660,7 +660,7 @@ entry:
660660
; CHECK-NEXT: blr
661661

662662
; CHECK-PWR8-LABEL: dpConv2ub_x
663-
; CHECK-PWR8: lxsdx [[LD:[0-9]+]], 0, 3
663+
; CHECK-PWR8: lfdx [[LD:[0-9]+]], 0, 3
664664
; CHECK-PWR8-NEXT: xscvdpsxws [[CONV:[0-9]+]], [[LD]]
665665
; CHECK-PWR8-NEXT: mfvsrwz [[REG:[0-9]+]], [[CONV]]
666666
; CHECK-PWR8-NEXT: stbx [[REG]], 4, 5

‎llvm/test/CodeGen/PowerPC/swaps-le-6.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ entry:
2727

2828
; CHECK-LABEL: @bar0
2929
; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
30-
; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
30+
; CHECK-DAG: lfdx [[REG2:[0-9]+]]
3131
; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
3232
; CHECK: xxpermdi [[REG5:[0-9]+]], [[REG4]], [[REG1]], 1
3333
; CHECK: stxvd2x [[REG5]]
@@ -50,7 +50,7 @@ entry:
5050

5151
; CHECK-LABEL: @bar1
5252
; CHECK-DAG: lxvd2x [[REG1:[0-9]+]]
53-
; CHECK-DAG: lxsdx [[REG2:[0-9]+]]
53+
; CHECK-DAG: lfdx [[REG2:[0-9]+]]
5454
; CHECK: xxspltd [[REG4:[0-9]+]], [[REG2]], 0
5555
; CHECK: xxmrghd [[REG5:[0-9]+]], [[REG1]], [[REG4]]
5656
; CHECK: stxvd2x [[REG5]]

‎llvm/test/CodeGen/PowerPC/unaligned.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -74,8 +74,8 @@ entry:
7474
; CHECK: stfd
7575

7676
; CHECK-VSX: @foo5
77-
; CHECK-VSX: lxsdx
78-
; CHECK-VSX: stxsdx
77+
; CHECK-VSX: lfdx
78+
; CHECK-VSX: stfdx
7979
}
8080

8181
define void @foo6(<4 x float>* %p, <4 x float>* %r) nounwind {

‎llvm/test/CodeGen/PowerPC/vsx_insert_extract_le.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@ define <2 x double> @testi0(<2 x double>* %p1, double* %p2) {
1616

1717
; CHECK-LABEL: testi0
1818
; CHECK: lxvd2x 0, 0, 3
19-
; CHECK: lxsdx 1, 0, 4
19+
; CHECK: lfdx 1, 0, 4
2020
; CHECK-DAG: xxspltd 1, 1, 0
2121
; CHECK-DAG: xxswapd 0, 0
2222
; CHECK: xxpermdi 34, 0, 1, 1
@@ -36,7 +36,7 @@ define <2 x double> @testi1(<2 x double>* %p1, double* %p2) {
3636

3737
; CHECK-LABEL: testi1
3838
; CHECK: lxvd2x 0, 0, 3
39-
; CHECK: lxsdx 1, 0, 4
39+
; CHECK: lfdx 1, 0, 4
4040
; CHECK-DAG: xxspltd 1, 1, 0
4141
; CHECK-DAG: xxswapd 0, 0
4242
; CHECK: xxmrgld 34, 1, 0

‎llvm/test/CodeGen/PowerPC/vsx_scalar_ld_st.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -123,7 +123,7 @@ entry:
123123
store volatile float %conv, float* %ff, align 4
124124
ret void
125125
; CHECK-LABEL: @dblToFloat
126-
; CHECK: lxsdx [[REGLD5:[0-9]+]],
126+
; CHECK: lfdx [[REGLD5:[0-9]+]],
127127
; CHECK: stfsx [[REGLD5]],
128128
; CHECK-P9-LABEL: @dblToFloat
129129
; CHECK-P9: lfd [[REGLD5:[0-9]+]],
@@ -140,7 +140,7 @@ entry:
140140
ret void
141141
; CHECK-LABEL: @floatToDbl
142142
; CHECK: lfsx [[REGLD5:[0-9]+]],
143-
; CHECK: stxsdx [[REGLD5]],
143+
; CHECK: stfdx [[REGLD5]],
144144
; CHECK-P9-LABEL: @floatToDbl
145145
; CHECK-P9: lfs [[REGLD5:[0-9]+]],
146146
; CHECK-P9: stfd [[REGLD5]],

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