[Power9]Legalize and emit code for round & convert quad-precision values

[lei]

Summary

Legalize and emit code for round & convert float128 to double precision and single precision.

[nemanjai]

lib/Target/PowerPC/PPCInstrVSX.td

442

This should probably have a pattern (the same pattern as the definition of FRSP) so that we can do these conversions in all 64 registers without having to move stuff around.

Of course, doing that will probably change behaviour of a number of test cases that will have to be updated. It will probably require a change in PPCMIPeephole.cpp since we explicitly check for PPC::FRSP.
But it does need to be done. We clearly missed this instruction when we implemented support for ISA 2.07.

Finally, I think this is in the wrong place. This was introduced in ISA 2.07 (Power8) so it needs to be in a HasP8Vector block.

2374

What does the acronym VFSR stand for? Is it meant to be VSFR (as in vector-scalar FP register)?

3378

The storage patterns seem redundant. Won't we emit the exact same code even without them?

[lei]

lib/Target/PowerPC/PPCInstrVSX.td

442

I will move this definition to down to the ISA 2.07 instruction implementation block. However I will leave out the pattern for implementation in a different, non float128, patch.

2374

ops.. yes it was meant to be VSFR

3378

The output register for the X_VT5_XO5_VB5_VFSR class was wrong. Will update to vfrc from vsfrc and remove these storage patterns.

[nemanjai]

LGTM.

lib/Target/PowerPC/P9InstrResources.td

def : InstRW<[P9_DP_7C, IP_EXEC_1C, DISP_1C, DISP_1C],
     XSRDPIP,
     XSRDPIZ,
     XSREDP,
     XSRESP,
     XSRSQRTEDP,
     XSRSQRTESP,
     XSSUBDP,
     XSSUBSP,
-    XSCVDPSPN
+    XSCVDPSPN,
+    XSRSP
 )>;
 
 // Three Cycle PM operation. Only one PM unit per superslice so we use the whole
 //  superslice. That includes both exec pipelines (EXECO, EXECE) and all three
 //  dispatches.
 def : InstRW<[P9_PM_3C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     (instregex "LVS(L|R)$"),

lib/Target/PowerPC/PPCISelLowering.cpp

if (Subtarget.hasP9Vector()) {
         addRegisterClass(MVT::f128, &PPC::VRRCRegClass);
         setOperationAction(ISD::FADD, MVT::f128, Legal);
         setOperationAction(ISD::FSUB, MVT::f128, Legal);
         setOperationAction(ISD::FDIV, MVT::f128, Legal);
         setOperationAction(ISD::FMUL, MVT::f128, Legal);
         setOperationAction(ISD::FP_EXTEND, MVT::f128, Legal);
         setLoadExtAction(ISD::EXTLOAD, MVT::f128, MVT::f64, Expand);
         setOperationAction(ISD::FMA, MVT::f128, Legal);
+        setOperationAction(ISD::FP_ROUND, MVT::f64, Legal);
+        setOperationAction(ISD::FP_ROUND, MVT::f32, Legal);
+        setTruncStoreAction(MVT::f128, MVT::f64, Expand);
+        setTruncStoreAction(MVT::f128, MVT::f32, Expand);
       }
 
     }
 
     if (Subtarget.hasP9Altivec()) {
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
       setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
     }

lib/Target/PowerPC/PPCInstrVSX.td

def XSSQRTDP : XX2Form<60, 75,
                         [(set f64:$XT, (fsqrt f64:$XB))]>;
 
   def XSREDP : XX2Form<60, 90,
                         (outs vsfrc:$XT), (ins vsfrc:$XB),
                         "xsredp $XT, $XB", IIC_VecFP,
                         [(set f64:$XT, (PPCfre f64:$XB))]>;
   def XSRSQRTEDP : XX2Form<60, 74,
                            (outs vsfrc:$XT), (ins vsfrc:$XB),
                            "xsrsqrtedp $XT, $XB", IIC_VecFP,
                            [(set f64:$XT, (PPCfrsqrte f64:$XB))]>;
 
   def XSTDIVDP : XX3Form_1<60, 61,
                          (outs crrc:$crD), (ins vsfrc:$XA, vsfrc:$XB),
                          "xstdivdp $crD, $XA, $XB", IIC_FPCompare, []>;
   def XSTSQRTDP : XX2Form_1<60, 106,
                           (outs crrc:$crD), (ins vsfrc:$XB),
                           "xstsqrtdp $crD, $XB", IIC_FPCompare, []>;
let AddedComplexity = 400 in { // Prefer VSX patterns over non-VSX patterns.
   def XSDIVSP : XX3Form<60, 24,
                         (outs vssrc:$XT), (ins vssrc:$XA, vssrc:$XB),
                         "xsdivsp $XT, $XA, $XB", IIC_FPDivS,
                         [(set f32:$XT, (fdiv f32:$XA, f32:$XB))]>;
   def XSRESP : XX2Form<60, 26,
                         (outs vssrc:$XT), (ins vssrc:$XB),
                         "xsresp $XT, $XB", IIC_VecFP,
                         [(set f32:$XT, (PPCfre f32:$XB))]>;
+  def XSRSP : XX2Form<60, 281,
+                        (outs vssrc:$XT), (ins vsfrc:$XB),
+                        "xsrsp $XT, $XB", IIC_VecFP, []>;
   def XSSQRTSP : XX2Form<60, 11,
                         (outs vssrc:$XT), (ins vssrc:$XB),
                         "xssqrtsp $XT, $XB", IIC_FPSqrtS,
                         [(set f32:$XT, (fsqrt f32:$XB))]>;
   def XSRSQRTESP : XX2Form<60, 10,
                            (outs vssrc:$XT), (ins vssrc:$XB),
                            "xsrsqrtesp $XT, $XB", IIC_VecFP,
                            [(set f32:$XT, (PPCfrsqrte f32:$XB))]>;
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
 
   // [PO VRT XO VRB XO /], but the VRB is only used the left 64 bits (or less),
   // So we use different operand class for VRB
   class X_VT5_XO5_VB5_TyVB<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
                            RegisterOperand vbtype, list<dag> pattern>
     : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vrrc:$vT), (ins vbtype:$vB),
                     !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
 
+  // [PO VRT XO VRB XO /]
+  class X_VT5_XO5_VB5_VSFR<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
+                      list<dag> pattern>
+    : X_RD5_XO5_RS5<opcode, xo2, xo, (outs vfrc:$vT), (ins vrrc:$vB),
+                    !strconcat(opc, " $vT, $vB"), IIC_VecFP, pattern>;
+
+  // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
+  class X_VT5_XO5_VB5_VSFR_Ro<bits<6> opcode, bits<5> xo2, bits<10> xo, string opc,
+                         list<dag> pattern>
+    : X_VT5_XO5_VB5_VSFR<opcode, xo2, xo, opc, pattern>, isDOT;
+
   let UseVSXReg = 1 in {
   // [PO T XO B XO BX /]
   class XX2_RT5_XO5_XB6<bits<6> opcode, bits<5> xo2, bits<9> xo, string opc,
                         list<dag> pattern>
     : XX2_RD5_XO5_RS6<opcode, xo2, xo, (outs g8rc:$rT), (ins vsfrc:$XB),
                       !strconcat(opc, " $rT, $XB"), IIC_VecFP, pattern>;
 
   // [PO T XO B XO BX TX]
let AddedComplexity = 400, Predicates = [HasP9Vector] in {
   //===--------------------------------------------------------------------===//
   // Quad-Precision Floating-Point Conversion Instructions:
 
   // Convert DP -> QP
   def XSCVDPQP  : X_VT5_XO5_VB5_TyVB<63, 22, 836, "xscvdpqp", vfrc, []>;
   def : Pat<(f128 (fpextend f64:$src)), (f128 (XSCVDPQP $src))>;
 
   // Round & Convert QP -> DP (dword[1] is set to zero)
-  def XSCVQPDP  : X_VT5_XO5_VB5   <63, 20, 836, "xscvqpdp" , []>;
-  def XSCVQPDPO : X_VT5_XO5_VB5_Ro<63, 20, 836, "xscvqpdpo", []>;
+  def XSCVQPDP  : X_VT5_XO5_VB5_VSFR<63, 20, 836, "xscvqpdp" , []>;
+  def XSCVQPDPO : X_VT5_XO5_VB5_VSFR_Ro<63, 20, 836, "xscvqpdpo", []>;
 
   // Truncate & Convert QP -> (Un)Signed (D)Word (dword[1] is set to zero)
   def XSCVQPSDZ : X_VT5_XO5_VB5<63, 25, 836, "xscvqpsdz", []>;
   def XSCVQPSWZ : X_VT5_XO5_VB5<63,  9, 836, "xscvqpswz", []>;
   def XSCVQPUDZ : X_VT5_XO5_VB5<63, 17, 836, "xscvqpudz", []>;
   def XSCVQPUWZ : X_VT5_XO5_VB5<63,  1, 836, "xscvqpuwz", []>;
 
   // Convert (Un)Signed DWord -> QP.
def : Pat<(PPCstore_scal_int_from_vsr
             (STXSD (XSCVDPUXDS f64:$src), ixaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 2),
             (STXSIHX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
   def : Pat<(PPCstore_scal_int_from_vsr
               (f64 (PPCcv_fp_to_uint_in_vsr f64:$src)), xoaddr:$dst, 1),
             (STXSIBX (XSCVDPUXWS f64:$src), xoaddr:$dst)>;
 
+  // Round & Convert QP -> DP/SP
+  def : Pat<(f64 (fpround f128:$src)), (f64 (XSCVQPDP $src))>;
+  def : Pat<(f32 (fpround f128:$src)), (f32 (XSRSP (XSCVQPDPO $src)))>;
 } // end HasP9Vector, AddedComplexity
+
 let Predicates = [HasP9Vector] in {
   let isPseudo = 1 in {
     let mayStore = 1 in {
       def SPILLTOVSR_STX : PseudoXFormMemOp<(outs),
                                             (ins spilltovsrrc:$XT, memrr:$dst),
                                             "#SPILLTOVSR_STX", []>;
       def SPILLTOVSR_ST : Pseudo<(outs), (ins spilltovsrrc:$XT, memrix:$dst),
                                 "#SPILLTOVSR_ST", []>;

test/CodeGen/PowerPC/f128-conv.ll

 ; CHECK-LABEL: ubConv2qp_04
 ; CHECK: lbz [[REG0:[0-9]+]], 0(5)
 ; CHECK: add 4, [[REG0]], 4
 ; CHECK: mtvsrwa [[REG:[0-9]+]], 4
 ; CHECK-NEXT: xscvsdqp [[CONV:[0-9]+]], [[REG]]
 ; CHECK-NEXT: stxv [[CONV]], 0(3)
 ; CHECK-NEXT: blr
 }
+
+;  Convert QP to DP
+
+@f128Array = global [4 x fp128]
+                      [fp128 0xL00000000000000004004C00000000000,
+                       fp128 0xLF000000000000000400808AB851EB851,
+                       fp128 0xL5000000000000000400E0C26324C8366,
+                       fp128 0xL8000000000000000400A24E2E147AE14], align 16
+@f128global = global fp128 0xL300000000000000040089CA8F5C28F5C, align 16
+
+; Function Attrs: norecurse nounwind readonly
+define double @qpConv2dp(fp128* nocapture readonly %a) {
+; CHECK-LABEL: qpConv2dp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv 2, 0(3)
+; CHECK-NEXT:    xscvqpdp 2, 2
+; CHECK-NEXT:    xxlor 1, 2, 2
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptrunc fp128 %0 to double
+  ret double %conv
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2dp_02(double* nocapture %res) {
+; CHECK-LABEL: qpConv2dp_02:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 4, 2, .LC6@toc@ha
+; CHECK-NEXT:    ld 4, .LC6@toc@l(4)
+; CHECK-NEXT:    lxvx 2, 0, 4
+; CHECK-NEXT:    xscvqpdp 2, 2
+; CHECK-NEXT:    stxsd 2, 0(3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* @f128global, align 16
+  %conv = fptrunc fp128 %0 to double
+  store double %conv, double* %res, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2dp_03(double* nocapture %res, i32 signext %idx) {
+; CHECK-LABEL: qpConv2dp_03:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 5, 2, .LC7@toc@ha
+; CHECK-NEXT:    sldi 4, 4, 3
+; CHECK-NEXT:    ld 5, .LC7@toc@l(5)
+; CHECK-NEXT:    lxvx 2, 0, 5
+; CHECK-NEXT:    xscvqpdp 2, 2
+; CHECK-NEXT:    stxsdx 2, 3, 4
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 0), align 16
+  %conv = fptrunc fp128 %0 to double
+  %idxprom = sext i32 %idx to i64
+  %arrayidx = getelementptr inbounds double, double* %res, i64 %idxprom
+  store double %conv, double* %arrayidx, align 8
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2dp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, double* nocapture %res) {
+; CHECK-LABEL: qpConv2dp_04:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv 2, 0(3)
+; CHECK-NEXT:    lxv 3, 0(4)
+; CHECK-NEXT:    xsaddqp 2, 2, 3
+; CHECK-NEXT:    xscvqpdp 2, 2
+; CHECK-NEXT:    stxsd 2, 0(5)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* %b, align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptrunc fp128 %add to double
+  store double %conv, double* %res, align 8
+  ret void
+}
+
+;  Convert QP to SP
+
+; Function Attrs: norecurse nounwind readonly
+define float @qpConv2sp(fp128* nocapture readonly %a) {
+; CHECK-LABEL: qpConv2sp:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv 2, 0(3)
+; CHECK-NEXT:    xscvqpdpo 2, 2
+; CHECK-NEXT:    xsrsp 1, 2
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %conv = fptrunc fp128 %0 to float
+  ret float %conv
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sp_02(float* nocapture %res) {
+; CHECK-LABEL: qpConv2sp_02:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 4, 2, .LC6@toc@ha
+; CHECK-NEXT:    ld 4, .LC6@toc@l(4)
+; CHECK-NEXT:    lxvx 2, 0, 4
+; CHECK-NEXT:    xscvqpdpo 2, 2
+; CHECK-NEXT:    xsrsp 0, 2
+; CHECK-NEXT:    stfs 0, 0(3)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* @f128global, align 16
+  %conv = fptrunc fp128 %0 to float
+  store float %conv, float* %res, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sp_03(float* nocapture %res, i32 signext %idx) {
+; CHECK-LABEL: qpConv2sp_03:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    addis 5, 2, .LC7@toc@ha
+; CHECK-NEXT:    sldi 4, 4, 2
+; CHECK-NEXT:    ld 5, .LC7@toc@l(5)
+; CHECK-NEXT:    lxv 2, 48(5)
+; CHECK-NEXT:    xscvqpdpo 2, 2
+; CHECK-NEXT:    xsrsp 0, 2
+; CHECK-NEXT:    stfsx 0, 3, 4
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* getelementptr inbounds ([4 x fp128], [4 x fp128]* @f128Array, i64 0, i64 3), align 16
+  %conv = fptrunc fp128 %0 to float
+  %idxprom = sext i32 %idx to i64
+  %arrayidx = getelementptr inbounds float, float* %res, i64 %idxprom
+  store float %conv, float* %arrayidx, align 4
+  ret void
+}
+
+; Function Attrs: norecurse nounwind
+define void @qpConv2sp_04(fp128* nocapture readonly %a, fp128* nocapture readonly %b, float* nocapture %res) {
+; CHECK-LABEL: qpConv2sp_04:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    lxv 2, 0(3)
+; CHECK-NEXT:    lxv 3, 0(4)
+; CHECK-NEXT:    xsaddqp 2, 2, 3
+; CHECK-NEXT:    xscvqpdpo 2, 2
+; CHECK-NEXT:    xsrsp 0, 2
+; CHECK-NEXT:    stfs 0, 0(5)
+; CHECK-NEXT:    blr
+entry:
+  %0 = load fp128, fp128* %a, align 16
+  %1 = load fp128, fp128* %b, align 16
+  %add = fadd fp128 %0, %1
+  %conv = fptrunc fp128 %add to float
+  store float %conv, float* %res, align 4
+  ret void
+}