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[Power9]Legalize and emit code for round & convert quad-precision values
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Authored by lei on May 16 2018, 9:09 PM.

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rL LLVM

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lei created this revision.May 16 2018, 9:09 PM
nemanjai added inline comments.May 23 2018, 7:58 PM
lib/Target/PowerPC/PPCInstrVSX.td
442 ↗(On Diff #147234)

This should probably have a pattern (the same pattern as the definition of FRSP) so that we can do these conversions in all 64 registers without having to move stuff around.

Of course, doing that will probably change behaviour of a number of test cases that will have to be updated. It will probably require a change in PPCMIPeephole.cpp since we explicitly check for PPC::FRSP.
But it does need to be done. We clearly missed this instruction when we implemented support for ISA 2.07.

Finally, I think this is in the wrong place. This was introduced in ISA 2.07 (Power8) so it needs to be in a HasP8Vector block.

2374 ↗(On Diff #147234)

What does the acronym VFSR stand for? Is it meant to be VSFR (as in vector-scalar FP register)?

3378 ↗(On Diff #147234)

The storage patterns seem redundant. Won't we emit the exact same code even without them?

lei updated this revision to Diff 148612.May 25 2018, 8:29 AM
lei added inline comments.
lib/Target/PowerPC/PPCInstrVSX.td
442 ↗(On Diff #147234)

I will move this definition to down to the ISA 2.07 instruction implementation block. However I will leave out the pattern for implementation in a different, non float128, patch.

2374 ↗(On Diff #147234)

ops.. yes it was meant to be VSFR

3378 ↗(On Diff #147234)

The output register for the X_VT5_XO5_VB5_VFSR class was wrong. Will update to vfrc from vsfrc and remove these storage patterns.

lei marked 3 inline comments as done.May 25 2018, 8:30 AM
nemanjai accepted this revision.Jul 4 2018, 7:58 AM

LGTM.

This revision is now accepted and ready to land.Jul 4 2018, 7:58 AM
This revision was automatically updated to reflect the committed changes.