[mips] Correct the predicates for a number of instructions.

[sdardis]

Summary

Previously, their listed predicates were overridden at the scope level.

[atanasyan]

LGTM

llvm/trunk/lib/Target/Mips/MicroMipsInstrInfo.td

 def LWSP_MM : LoadSPMM16<"lw", GPR32Opnd, II_LW, mem_mm_sp_imm5_lsl2>,
               LOAD_STORE_SP_FM_MM16<0x12>;
 def SWSP_MM : StoreSPMM16<"sw", GPR32Opnd, II_SW, mem_mm_sp_imm5_lsl2>,
               LOAD_STORE_SP_FM_MM16<0x32>;
 def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16;
 def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16;
 def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16;
 def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16;
-def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>;
-def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>;
+def MFHI16_MM : MoveFromHILOMM<"mfhi16", GPR32Opnd, AC0>,
+                MFHILO_FM_MM16<0x10>;
+def MFLO16_MM : MoveFromHILOMM<"mflo16", GPR32Opnd, AC0>,
+                MFHILO_FM_MM16<0x12>;
 def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>;
 def MOVEP_MM : MovePMM16<"movep", GPRMM16OpndMoveP>, MOVEP_FM_MM16,
                ISA_MICROMIPS_NOT_32R6;
 def LI16_MM : LoadImmMM16<"li16", li16_imm, GPRMM16Opnd>, LI_FM_MM16,
               IsAsCheapAsAMove;
 def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>,
                 ISA_MICROMIPS32_NOT_MIPS32R6;
 def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>;
def LWR_MM : MMRel, LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12,
                ISA_MICROMIPS32_NOT_MIPS32R6;
   def SWL_MM : MMRel, StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12,
                                        II_SWL>, LWL_FM_MM<0x8>,
                ISA_MICROMIPS32_NOT_MIPS32R6;
   def SWR_MM : MMRel, StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12,
                                        II_SWR>, LWL_FM_MM<0x9>,
                ISA_MICROMIPS32_NOT_MIPS32R6;
 }
-let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
+let DecoderNamespace = "MicroMips" in {
   /// Load and Store Instructions - multiple
   def SWM32_MM  : StoreMultMM<"swm32", II_SWM>, LWM_FM_MM<0xd>, ISA_MICROMIPS;
   def LWM32_MM  : LoadMultMM<"lwm32", II_LWM>, LWM_FM_MM<0x5>, ISA_MICROMIPS;
 
   /// Load and Store Pair Instructions
   def SWP_MM  : StorePairMM<"swp">, LWM_FM_MM<0x9>, ISA_MICROMIPS;
   def LWP_MM  : LoadPairMM<"lwp">, LWM_FM_MM<0x1>, ISA_MICROMIPS;
 
def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd,
                   ISA_MICROMIPS32_NOT_MIPS32R6;
   def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd,
                                      II_MOVN>, ADD_FM_MM<0, 0x18>,
                   ISA_MICROMIPS32_NOT_MIPS32R6;
   def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT, MipsCMovFP_T>,
                   CMov_F_I_FM_MM<0x25>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF, MipsCMovFP_F>,
                   CMov_F_I_FM_MM<0x5>, ISA_MICROMIPS32_NOT_MIPS32R6;
-
   /// Move to/from HI/LO
   def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>,
-                MTLO_FM_MM<0x0b5>;
+                MTLO_FM_MM<0x0b5>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>,
-                MTLO_FM_MM<0x0f5>;
+                MTLO_FM_MM<0x0f5>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>,
-                MFLO_FM_MM<0x035>;
+                MFLO_FM_MM<0x035>, ISA_MICROMIPS32_NOT_MIPS32R6;
   def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>,
-                MFLO_FM_MM<0x075>;
+                MFLO_FM_MM<0x075>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
   /// Multiply Add/Sub Instructions
-  def MADD_MM  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>;
-  def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>;
-  def MSUB_MM  : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>;
-  def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>;
+  def MADD_MM  : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
+  def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
+  def MSUB_MM  : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
+  def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>,
+                 ISA_MICROMIPS32_NOT_MIPS32R6;
 
   /// Count Leading
   def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd, II_CLZ>, CLO_FM_MM<0x16c>,
                ISA_MICROMIPS;
   def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd, II_CLO>, CLO_FM_MM<0x12c>,
                ISA_MICROMIPS;
 
   /// Sign Ext In Register Instructions.
   def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
                SEB_FM_MM<0x0ac>, ISA_MICROMIPS;
   def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
                SEB_FM_MM<0x0ec>, ISA_MICROMIPS;
 
   /// Word Swap Bytes Within Halfwords
   def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>,
-                SEB_FM_MM<0x1ec>, ISA_MIPS32R2;
+                SEB_FM_MM<0x1ec>, ISA_MICROMIPS;
   // TODO: Add '0 < pos+size <= 32' constraint check to ext instruction
   def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, uimm5_plus1, immZExt5,
-                              immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>;
+                              immZExt5Plus1, MipsExt>, EXT_FM_MM<0x2c>,
+               ISA_MICROMIPS32_NOT_MIPS32R6;
   def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, uimm5_inssize_plus1,
                               immZExt5, immZExt5Plus1>,
-               EXT_FM_MM<0x0c>;
+               EXT_FM_MM<0x0c>, ISA_MICROMIPS32_NOT_MIPS32R6;
 
   /// Jump Instructions
-}
-let DecoderNamespace = "MicroMips", DecoderMethod = "DecodeJumpTargetMM" in
+  let DecoderMethod = "DecodeJumpTargetMM" in
     def J_MM          : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">,
                         J_FM_MM<0x35>, AdditionalRequires<[RelocNotPIC]>,
                         IsBranch, ISA_MICROMIPS32_NOT_MIPS32R6;
 
-let DecoderNamespace = "MicroMips" in {
   let DecoderMethod = "DecodeJumpTargetMM" in {
     def JAL_MM      : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>,
                       ISA_MICROMIPS32_NOT_MIPS32R6;
     def JALX_MM     : MMRel, JumpLink<"jalx", calltarget>, J_FM_MM<0x3c>,
                       ISA_MICROMIPS32_NOT_MIPS32R6;
   }
   def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>,
               ISA_MICROMIPS32_NOT_MIPS32R6;

llvm/trunk/test/CodeGen/Mips/llvm-ir/mul.ll

; ALL-LABEL: mul_i64:
   ; M4:         mflo    $2
 
   ; 64R1-R5:    dmult   $4, $5
   ; 64R1-R5:    mflo    $2
 
   ; 64R6:       dmul    $2, $4, $5
 
   ; MM32R3:     multu   $[[T0:[0-9]+]], $7
-  ; MM32R3:     mflo    $[[T1:[0-9]+]]
-  ; MM32R3:     mfhi    $[[T2:[0-9]+]]
+  ; MM32R3:     mflo16  $[[T1:[0-9]+]]
+  ; MM32R3:     mfhi16  $[[T2:[0-9]+]]
   ; MM32R3:     mul     $[[T0]], $[[T0]], $6
   ; MM32R3:     addu16  $2, $[[T2]], $[[T0]]
   ; MM32R3:     mul     $[[T3:[0-9]+]], $4, $7
   ; MM32R3:     addu16  $[[T2]], $[[T2]], $[[T3]]
 
   ; MM32R6:     mul     $[[T0:[0-9]+]], $5, $6
   ; MM32R6:     muhu    $[[T1:[0-9]+]], $5, $7
   ; MM32R6:     addu16  $[[T2:[0-9]+]], $[[T1]], $[[T0]]

llvm/trunk/test/CodeGen/Mips/llvm-ir/sdiv.ll

; ALL-LABEL: sdiv_i1:
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; FIXME: The andi/negu instructions are redundant since div is signed.
   ; R6:           andi    $[[T0]], $[[T0]], 1
   ; R6:           negu    $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $[[T0:[0-9]+]]
+  ; MMR3:         mflo16  $[[T0:[0-9]+]]
   ; MMR3:         andi16  $[[T0]], $[[T0]], 1
   ; MMR3:         li16    $[[T1:[0-9]+]], 0
   ; MMR3:         subu16  $2, $[[T1]], $[[T0]]
 
   ; MMR6:         div     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
   ; MMR6:         andi16  $[[T0]], $[[T0]], 1
   ; MMR6:         li16    $[[T1:[0-9]+]], 0
; ALL-LABEL: sdiv_i8:
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; FIXME: This instruction is redundant.
   ; R6:           seb     $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $[[T0:[0-9]+]]
+  ; MMR3:         mflo16  $[[T0:[0-9]+]]
   ; MMR3:         seb     $2, $[[T0]]
 
   ; MMR6:         div     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
   ; MMR6:         seb     $2, $[[T0]]
 
   %r = sdiv i8 %a, %b
   ret i8 %r
; ALL-LABEL: sdiv_i16:
 
   ; R6:           div     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; FIXME: This is instruction is redundant since div is signed.
   ; R6:           seh     $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $[[T0:[0-9]+]]
+  ; MMR3:         mflo16  $[[T0:[0-9]+]]
   ; MMR3:         seh     $2, $[[T0]]
 
   ; MMR6:         div     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
   ; MMR6:         seh     $2, $[[T0]]
 
   %r = sdiv i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @sdiv_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: sdiv_i32:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           div     $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $2
+  ; MMR3:         mflo16 $2
 
   ; MMR6:         div     $2, $4, $5
   ; MMR6:         teq     $5, $zero, 7
 
   %r = sdiv i32 %a, %b
   ret i32 %r
 }
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/srem.ll

; ALL-LABEL: srem_i1:
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; R6:           andi    $[[T0]], $[[T0]], 1
   ; R6:           negu    $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mfhi    $[[T0:[0-9]+]]
+  ; MMR3:         mfhi16  $[[T0:[0-9]+]]
   ; MMR3:         andi16  $[[T0]], $[[T0]], 1
   ; MMR3:         li16    $[[T1:[0-9]+]], 0
   ; MMR3:         subu16  $2, $[[T1]], $[[T0]]
 
   ; MMR6:         mod     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
   ; MMR6:         andi16  $[[T0]], $[[T0]], 1
   ; MMR6:         li16    $[[T1:[0-9]+]], 0
; ALL-LABEL: srem_i8:
   ; R2-R5:        seb     $2, $[[T0]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; R6:           seb     $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mfhi    $[[T0:[0-9]+]]
+  ; MMR3:         mfhi16  $[[T0:[0-9]+]]
   ; MMR3:         seb     $2, $[[T0]]
 
   ; MMR6:         mod     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
   ; MMR6:         seb     $2, $[[T0]]
 
   %r = srem i8 %a, %b
   ret i8 %r
; ALL-LABEL: srem_i16:
   ; R2-R5:        seh     $2, $[[T0]]
 
   ; R6:           mod     $[[T0:[0-9]+]], $4, $5
   ; R6:           teq     $5, $zero, 7
   ; R6:           seh     $2, $[[T0]]
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mfhi    $[[T0:[0-9]+]]
+  ; MMR3:         mfhi16  $[[T0:[0-9]+]]
   ; MMR3:         seh     $2, $[[T0]]
 
   ; MMR6:         mod     $[[T0:[0-9]+]], $4, $5
   ; MMR6:         teq     $5, $zero, 7
   ; MMR6:         seh     $2, $[[T0]]
 
   %r = srem i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @srem_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: srem_i32:
 
   ; NOT-R6:       div     $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mfhi    $2
 
   ; R6:           mod     $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
   ; MMR3:         div     $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mfhi    $2
+  ; MMR3:         mfhi16  $2
 
   ; MMR6:         mod     $2, $4, $5
   ; MMR6:         teq     $5, $zero, 7
 
   %r = srem i32 %a, %b
   ret i32 %r
 }
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/udiv.ll

; ALL-LABEL: udiv_i1:
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
   ; MMR3:         divu    $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $2
+  ; MMR3:         mflo16  $2
 
   ; MMR6:         divu    $2, $4, $5
   ; MMR6:         teq     $5, $zero, 7
 
   %r = udiv i1 %a, %b
   ret i1 %r
 }
 
 define zeroext i8 @udiv_i8(i8 zeroext %a, i8 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i8:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
   ; MMR3:         divu    $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $2
+  ; MMR3:         mflo16  $2
 
   ; MMR6:         divu    $2, $4, $5
   ; MMR6:         teq     $5, $zero, 7
 
   %r = udiv i8 %a, %b
   ret i8 %r
 }
 
 define zeroext i16 @udiv_i16(i16 zeroext %a, i16 zeroext %b) {
 entry:
 ; ALL-LABEL: udiv_i16:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
   ; MMR3:         divu    $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $2
+  ; MMR3:         mflo16  $2
 
   ; MMR6:         divu    $2, $4, $5
   ; MMR6:         teq     $5, $zero, 7
 
   %r = udiv i16 %a, %b
   ret i16 %r
 }
 
 define signext i32 @udiv_i32(i32 signext %a, i32 signext %b) {
 entry:
 ; ALL-LABEL: udiv_i32:
 
   ; NOT-R6:       divu    $zero, $4, $5
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mflo    $2
 
   ; R6:           divu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
   ; MMR3:         divu    $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mflo    $2
+  ; MMR3:         mflo16  $2
 
   ; MMR6:         divu    $2, $4, $5
   ; MMR6:         teq     $5, $zero, 7
 
   %r = udiv i32 %a, %b
   ret i32 %r
 }
 

llvm/trunk/test/CodeGen/Mips/llvm-ir/urem.ll

; ALL-LABEL: urem_i1:
   ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; R6:           teq     $[[T0]], $zero, 7
   ; R6:           negu    $2, $[[T2]]
 
   ; MMR3:         andi16  $[[T0:[0-9]+]], $5, 1
   ; MMR3:         andi16  $[[T1:[0-9]+]], $4, 1
   ; MMR3:         divu    $zero, $[[T1]], $[[T0]]
   ; MMR3:         teq     $[[T0]], $zero, 7
-  ; MMR3:         mfhi    $[[T2:[0-9]+]]
+  ; MMR3:         mfhi16  $[[T2:[0-9]+]]
   ; MMR3:         andi16  $[[T0]], $[[T0]], 1
   ; MMR3:         li16    $[[T1:[0-9]+]], 0
   ; MMR3:         subu16  $2, $[[T1]], $[[T0]]
 
   ; MMR6:         andi16  $[[T0:[0-9]+]], $5, 1
   ; MMR6:         andi16  $[[T1:[0-9]+]], $4, 1
   ; MMR6:         modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; MMR6:         teq     $[[T0]], $zero, 7
; ALL-LABEL: urem_i8:
   ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; R6:           teq     $[[T0]], $zero, 7
   ; R6:           seb     $2, $[[T2]]
 
   ; MMR3:         andi16  $[[T0:[0-9]+]], $5, 255
   ; MMR3:         andi16  $[[T1:[0-9]+]], $4, 255
   ; MMR3:         divu    $zero, $[[T1]], $[[T0]]
   ; MMR3:         teq     $[[T0]], $zero, 7
-  ; MMR3:         mfhi    $[[T2:[0-9]+]]
+  ; MMR3:         mfhi16  $[[T2:[0-9]+]]
   ; MMR3:         seb     $2, $[[T2]]
 
   ; MMR6:         andi16  $[[T0:[0-9]+]], $5, 255
   ; MMR6:         andi16  $[[T1:[0-9]+]], $4, 255
   ; MMR6:         modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; MMR6:         teq     $[[T0]], $zero, 7
   ; MMR6:         seb     $2, $[[T2]]
 
; ALL-LABEL: urem_i16:
   ; R6:           modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; R6:           teq     $[[T0]], $zero, 7
   ; R6:           seh     $2, $[[T2]]
 
   ; MMR3:         andi16  $[[T0:[0-9]+]], $5, 65535
   ; MMR3:         andi16  $[[T1:[0-9]+]], $4, 65535
   ; MMR3:         divu    $zero, $[[T1]], $[[T0]]
   ; MMR3:         teq     $[[T0]], $zero, 7
-  ; MMR3:         mfhi    $[[T2:[0-9]+]]
+  ; MMR3:         mfhi16  $[[T2:[0-9]+]]
   ; MMR3:         seh     $2, $[[T2]]
 
   ; MMR6:         andi16  $[[T0:[0-9]+]], $5, 65535
   ; MMR6:         andi16  $[[T1:[0-9]+]], $4, 65535
   ; MMR6:         modu    $[[T2:[0-9]+]], $[[T1]], $[[T0]]
   ; MMR6:         teq     $[[T0]], $zero, 7
   ; MMR6:         seh     $2, $[[T2]]
 
; ALL-LABEL: urem_i32:
   ; NOT-R6:       teq     $5, $zero, 7
   ; NOT-R6:       mfhi    $2
 
   ; R6:           modu    $2, $4, $5
   ; R6:           teq     $5, $zero, 7
 
   ; MMR3:         divu    $zero, $4, $5
   ; MMR3:         teq     $5, $zero, 7
-  ; MMR3:         mfhi    $2
+  ; MMR3:         mfhi16  $2
 
   ; MMR6:         modu    $2, $4, $5
   ; MMR6:         teq     $5, $zero, 7
 
   %r = urem i32 %a, %b
   ret i32 %r
 }
 

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

 0x94 0x09 # CHECK: lbu16 $3, 4($17)
 0x8f 0x09 # CHECK: lbu16 $3, -1($16)
 0x82 0x29 # CHECK: lhu16 $3, 4($16)
 0x12 0x6a # CHECK: lw16 $4, 8($17)
 0x84 0x89 # CHECK: sb16 $3, 4($16)
 0x14 0xaa # CHECK: sh16 $4, 8($17)
 0x11 0xea # CHECK: sw16 $4, 4($17)
 0x11 0xe8 # CHECK: sw16 $zero, 4($17)
-0x09 0x46 # CHECK: mfhi $9
-0x49 0x46 # CHECK: mflo $9
+0x09 0x46 # CHECK: mfhi16 $9
+0x49 0x46 # CHECK: mflo16 $9
 0x21 0x0f # CHECK: move $25, $1
 0x9a 0x85 # CHECK: movep $4, $21, $18, $17
 0xa9 0x45 # CHECK: jrc $9
 0xc9 0x45 # CHECK: jalr $9
 0xe9 0x45 # CHECK: jalrs16 $9
 0x89 0x45 # CHECK: jr16 $9
 0xff 0xed # CHECK: li16 $3, -1
 0xfe 0xed # CHECK: li16 $3, 126

llvm/trunk/test/MC/Disassembler/Mips/micromips32r3/valid.txt

 0x09 0x94 # CHECK: lbu16 $3, 4($17)
 0x09 0x8f # CHECK: lbu16 $3, -1($16)
 0x29 0x82 # CHECK: lhu16 $3, 4($16)
 0x6a 0x12 # CHECK: lw16 $4, 8($17)
 0x89 0x84 # CHECK: sb16 $3, 4($16)
 0xaa 0x14 # CHECK: sh16 $4, 8($17)
 0xea 0x11 # CHECK: sw16 $4, 4($17)
 0xe8 0x11 # CHECK: sw16 $zero, 4($17)
-0x46 0x09 # CHECK: mfhi $9
-0x46 0x49 # CHECK: mflo $9
+0x46 0x09 # CHECK: mfhi16 $9
+0x46 0x49 # CHECK: mflo16 $9
 0x0f 0x21 # CHECK: move $25, $1
 0x85 0x9a # CHECK: movep $4, $21, $18, $17
 0x45 0xa9 # CHECK: jrc $9
 0x45 0xc9 # CHECK: jalr $9
 0x45 0xe9 # CHECK: jalrs16 $9
 0x45 0x89 # CHECK: jr16 $9
 0xed 0xff # CHECK: li16 $3, -1
 0xed 0xfe # CHECK: li16 $3, 126

llvm/trunk/test/MC/Mips/micromips-16-bit-instructions.s

 # CHECK-EL: addiur2 $6, $7, -1      # encoding: [0x7e,0x6f]
 # CHECK-EL: addiur2 $6, $7, 12      # encoding: [0x76,0x6f]
 # CHECK-EL: addius5 $7, -2          # encoding: [0xfc,0x4c]
 # CHECK-EL: addiusp -1028           # encoding: [0xff,0x4f]
 # CHECK-EL: addiusp -1032           # encoding: [0xfd,0x4f]
 # CHECK-EL: addiusp 1024            # encoding: [0x01,0x4c]
 # CHECK-EL: addiusp 1028            # encoding: [0x03,0x4c]
 # CHECK-EL: addiusp -16             # encoding: [0xf9,0x4f]
-# CHECK-EL: mfhi    $9              # encoding: [0x09,0x46]
-# CHECK-EL: mflo    $9              # encoding: [0x49,0x46]
+# CHECK-EL: mfhi16  $9              # encoding: [0x09,0x46]
+# CHECK-EL: mflo16  $9              # encoding: [0x49,0x46]
 # CHECK-EL: move    $25, $1         # encoding: [0x21,0x0f]
 # CHECK-EL: movep   $5, $6, $2, $3  # encoding: [0x34,0x84]
 # CHECK-EL: jrc     $9              # encoding: [0xa9,0x45]
 # CHECK-NEXT: jalr    $9            # encoding: [0xc9,0x45]
 # CHECK-EL: jraddiusp 20            # encoding: [0x05,0x47]
 # CHECK-NEXT: jalrs16 $9            # encoding: [0xe9,0x45]
 # CHECK-EL: nop                     # encoding: [0x00,0x0c]
 # CHECK-EL: jr16    $9              # encoding: [0x89,0x45]

 # CHECK-EB: addiur2 $6, $7, -1      # encoding: [0x6f,0x7e]
 # CHECK-EB: addiur2 $6, $7, 12      # encoding: [0x6f,0x76]
 # CHECK-EB: addius5 $7, -2          # encoding: [0x4c,0xfc]
 # CHECK-EB: addiusp -1028           # encoding: [0x4f,0xff]
 # CHECK-EB: addiusp -1032           # encoding: [0x4f,0xfd]
 # CHECK-EB: addiusp 1024            # encoding: [0x4c,0x01]
 # CHECK-EB: addiusp 1028            # encoding: [0x4c,0x03]
 # CHECK-EB: addiusp -16             # encoding: [0x4f,0xf9]
-# CHECK-EB: mfhi    $9              # encoding: [0x46,0x09]
-# CHECK-EB: mflo    $9              # encoding: [0x46,0x49]
+# CHECK-EB: mfhi16  $9              # encoding: [0x46,0x09]
+# CHECK-EB: mflo16  $9              # encoding: [0x46,0x49]
 # CHECK-EB: move    $25, $1         # encoding: [0x0f,0x21]
 # CHECK-EB: movep   $5, $6, $2, $3  # encoding: [0x84,0x34]
 # CHECK-EB: jrc     $9              # encoding: [0x45,0xa9]
 # CHECK-NEXT: jalr    $9            # encoding: [0x45,0xc9]
 # CHECK-EB: jraddiusp 20            # encoding: [0x47,0x05]
 # CHECK-NEXT: jalrs16 $9            # encoding: [0x45,0xe9]
 # CHECK-EB: nop                     # encoding: [0x0c,0x00]
 # CHECK-EB: jr16    $9              # encoding: [0x45,0x89]
# CHECK-EB: sdbbp16 14              # encoding: [0x46,0xce]
     addiur2 $6, $7, -1
     addiur2 $6, $7, 12
     addius5 $7, -2
     addiusp -1028
     addiusp -1032
     addiusp 1024
     addiusp 1028
     addiusp -16
-    mfhi    $9
-    mflo    $9
+    mfhi16  $9
+    mflo16  $9
     move    $25, $1
     movep   $5, $6, $2, $3
     jrc     $9
     jalr    $9
     jraddiusp 20
     jalrs16 $9
     jr16    $9
     beqz16 $6, 20
     bnez16 $6, 20
     b   132
     b16 132
     break16 8
     sdbbp16 14

llvm/trunk/test/MC/Mips/micromips/valid.s

 lbu16 $3, 4($17)            # CHECK: lbu16 $3, 4($17)   # encoding: [0x09,0x94]
 lbu16 $3, -1($16)           # CHECK: lbu16 $3, -1($16)  # encoding: [0x09,0x8f]
 lhu16 $3, 4($16)            # CHECK: lhu16 $3, 4($16)   # encoding: [0x29,0x82]
 lw16 $4, 8($17)             # CHECK: lw16 $4, 8($17)    # encoding: [0x6a,0x12]
 sb16 $3, 4($16)             # CHECK: sb16 $3, 4($16)    # encoding: [0x89,0x84]
 sh16 $4, 8($17)             # CHECK: sh16 $4, 8($17)    # encoding: [0xaa,0x14]
 sw16 $4, 4($17)             # CHECK: sw16 $4, 4($17)    # encoding: [0xea,0x11]
 sw16 $zero, 4($17)          # CHECK: sw16 $zero, 4($17) # encoding: [0xe8,0x11]
-mfhi $9                     # CHECK: mfhi $9            # encoding: [0x46,0x09]
-mflo $9                     # CHECK: mflo $9            # encoding: [0x46,0x49]
+mfhi16 $9                   # CHECK: mfhi16 $9          # encoding: [0x46,0x09]
+mflo16 $9                   # CHECK: mflo16 $9          # encoding: [0x46,0x49]
 move $25, $1                # CHECK: move $25, $1       # encoding: [0x0f,0x21]
 jrc $9                      # CHECK: jrc $9             # encoding: [0x45,0xa9]
 jalr $9                     # CHECK: jalr $9            # encoding: [0x45,0xc9]
 jalrs16 $9                  # CHECK: jalrs16 $9         # encoding: [0x45,0xe9]
 jr16 $9                     # CHECK: jr16 $9            # encoding: [0x45,0x89]
 li16 $3, -1                 # CHECK: li16 $3, -1        # encoding: [0xed,0xff]
 li16 $3, 126                # CHECK: li16 $3, 126       # encoding: [0xed,0xfe]
 addiur1sp $7, 4             # CHECK: addiur1sp $7, 4    # encoding: [0x6f,0x83]

 mov.d $f0, $f2              # CHECK: mov.d $f0, $f2         # encoding: [0x54,0x02,0x20,0x7b]
                             # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} FMOV_D32_MM
 movz $9, $6, $7             # CHECK: movz $9, $6, $7        # encoding: [0x00,0xe6,0x48,0x58]
 movn $9, $6, $7             # CHECK: movn $9, $6, $7        # encoding: [0x00,0xe6,0x48,0x18]
 movt $9, $6, $fcc0          # CHECK: movt $9, $6, $fcc0     # encoding: [0x55,0x26,0x09,0x7b]
 movf $9, $6, $fcc0          # CHECK: movf $9, $6, $fcc0     # encoding: [0x55,0x26,0x01,0x7b]
 # FIXME: MTHI should also have its 16 bit implementation selected in micromips
 mthi   $6                   # CHECK: mthi   $6              # encoding: [0x00,0x06,0x2d,0x7c]
-mfhi   $6                   # CHECK: mfhi   $6              # encoding: [0x46,0x06]
+mfhi   $6                   # CHECK: mfhi   $6              # encoding: [0x00,0x06,0x0d,0x7c]
 # FIXME: MTLO should also have its 16 bit implementation selected in micromips
 mtlo   $6                   # CHECK: mtlo   $6              # encoding: [0x00,0x06,0x3d,0x7c]
-mflo   $6                   # CHECK: mflo   $6              # encoding: [0x46,0x46]
+mflo   $6                   # CHECK: mflo   $6              # encoding: [0x00,0x06,0x1d,0x7c]
 mfhc1 $4, $f0               # CHECK: mfhc1 $4, $f0          # encoding: [0x54,0x80,0x30,0x3b]
                             # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} MFHC1_D32_MM
 mthc1 $4, $f0               # CHECK: mthc1 $4, $f0          # encoding: [0x54,0x80,0x38,0x3b]
                             # CHECK-NEXT:                   # <MCInst #{{[0-9]+}} MTHC1_D32_MM
 madd   $4, $5               # CHECK: madd   $4, $5          # encoding: [0x00,0xa4,0xcb,0x3c]
 maddu  $4, $5               # CHECK: maddu  $4, $5          # encoding: [0x00,0xa4,0xdb,0x3c]
 msub   $4, $5               # CHECK: msub   $4, $5          # encoding: [0x00,0xa4,0xeb,0x3c]
 msubu  $4, $5               # CHECK: msubu  $4, $5          # encoding: [0x00,0xa4,0xfb,0x3c]

llvm/trunk/test/MC/Mips/micromips32r6/invalid-wrong-error.s

# RUN: FileCheck %s < %t1
   swc2 $1, -2049($17)      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   swc2 $1, 2048($17)       # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   lwc2 $11, -1025($12)     # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
   lwc2 $11, 1024($12)      # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
   sc $4, 512($5)           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   sc $4, -513($5)          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ll $4, 512($5)           # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
   ll $4, -513($5)          # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  lwr $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  lwl $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  swr $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction
+  swl $4, 1($5)            # CHECK: :[[@LINE]]:11: error: invalid operand for instruction

llvm/trunk/test/MC/Mips/micromips32r6/invalid.s

# RUN: FileCheck %s < %t1
   tltiu $4, 5              # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
   tnei $4, 5               # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
   syscall -1               # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
   syscall $4               # CHECK: :[[@LINE]]:11: error: expected 10-bit unsigned immediate
   ldc2 $1, 1023($32)       # CHECK: :[[@LINE]]:17: error: invalid register number
   lwc2 $1, 16($32)         # CHECK: :[[@LINE]]:15: error: invalid register number
   sdc2 $1, 8($32)          # CHECK: :[[@LINE]]:14: error: invalid register number
   swc2 $1, 777($32)        # CHECK: :[[@LINE]]:16: error: invalid register number
+  movn  $3, $3, $4         # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  movz  $3, $3, $4         # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  movt  $4, $5, $fcc0      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  movf  $4, $5, $fcc0      # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  madd  $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  maddu $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  msub  $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled
+  msubu $4, $5             # CHECK: :[[@LINE]]:3: error: instruction requires a CPU feature not currently enabled

llvm/trunk/test/MC/Mips/micromips32r6/valid.s

# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   nop                      # CHECK: nop                 # encoding: [0x00,0x00,0x00,0x00]
   nor $3, $4, $5           # CHECK: nor $3, $4, $5      # encoding: [0x00,0xa4,0x1a,0xd0]
   or $3, $4, $5            # CHECK: or $3, $4, $5       # encoding: [0x00,0xa4,0x1a,0x90]
   ori $3, $4, 1234         # CHECK: ori $3, $4, 1234    # encoding: [0x50,0x64,0x04,0xd2]
   pref 1, 8($5)            # CHECK: pref 1, 8($5)       # encoding: [0x60,0x25,0x20,0x08]
                            # CHECK-NEXT:                # <MCInst #{{.*}} PREF_MMR6
   sb16 $3, 4($16)          # CHECK: sb16 $3, 4($16)     # encoding: [0x89,0x84]
   seb $3, $4               # CHECK: seb $3, $4          # encoding: [0x00,0x64,0x2b,0x3c]
+                           # CHECK-NEXT:                # <MCInst #{{.*}} SEB_MM
   seb $3                   # CHECK: seb $3, $3          # encoding: [0x00,0x63,0x2b,0x3c]
   seh $3, $4               # CHECK: seh $3, $4          # encoding: [0x00,0x64,0x3b,0x3c]
+                           # CHECK-NEXT:                # <MCInst #{{.*}} SEH_MM
   seh $3                   # CHECK: seh $3, $3          # encoding: [0x00,0x63,0x3b,0x3c]
   seleqz $2,$3,$4          # CHECK: seleqz $2, $3, $4   # encoding: [0x00,0x83,0x11,0x40]
   selnez $2,$3,$4          # CHECK: selnez $2, $3, $4   # encoding: [0x00,0x83,0x11,0x80]
   sh16 $4, 8($17)          # CHECK: sh16 $4, 8($17)     # encoding: [0xaa,0x14]
   sll $4, $3, 7            # CHECK: sll $4, $3, 7       # encoding: [0x00,0x83,0x38,0x00]
   sub $3, $4, $5           # CHECK: sub $3, $4, $5      # encoding: [0x00,0xa4,0x19,0x90]
   subu $3, $4, $5          # CHECK: subu $3, $4, $5     # encoding: [0x00,0xa4,0x19,0xd0]
   sw $4, 124($sp)          # CHECK: sw $4, 124($sp)     # encoding: [0xc8,0x9f]
# RUN: llvm-mc %s -triple=mips-unknown-linux -show-encoding -show-inst -mcpu=mips32r6 -mattr=micromips | FileCheck %s
   srl $3, 7                # CHECK: srl $3, $3, 7          # encoding: [0x00,0x63,0x38,0x40]
   lwp $16, 8($4)           # CHECK: lwp $16, 8($4)         # encoding: [0x22,0x04,0x10,0x08]
   swp $16, 8($4)           # CHECK: swp $16, 8($4)         # encoding: [0x22,0x04,0x90,0x08]
   bc1eqzc $f31, 4          # CHECK: bc1eqzc $f31, 4        # encoding: [0x41,0x1f,0x00,0x02]
   bc1nezc $f31, 4          # CHECK: bc1nezc $f31, 4        # encoding: [0x41,0x3f,0x00,0x02]
   bc2eqzc $31, 8           # CHECK: bc2eqzc $31, 8         # encoding: [0x41,0x5f,0x00,0x04]
   bc2nezc $31, 8           # CHECK: bc2nezc $31, 8         # encoding: [0x41,0x7f,0x00,0x04]
   ins $9, $6, 3, 7         # CHECK: ins $9, $6, 3, 7       # encoding: [0x01,0x26,0x48,0xcc]
+                           # CHECK-NEXT:                   # <MCInst #{{.*}} INS_MMR6
   jalrc $4, $5             # CHECK: jalrc $4, $5           # encoding: [0x00,0x85,0x0f,0x3c]
   jalrc $5                 # CHECK: jalrc $5               # encoding: [0x03,0xe5,0x0f,0x3c]
   ext $9, $6, 3, 7         # CHECK: ext $9, $6, 3, 7       # encoding: [0x01,0x26,0x30,0xec]
+                           # CHECK-NEXT:                   # <MCInst #{{.*}} EXT_MMR6
   bovc $2, $4, 24          # CHECK: bovc $2, $4, 24        # encoding: [0x74,0x44,0x00,0x0c]
   bovc $4, $2, 24          # CHECK: bovc $4, $2, 24        # encoding: [0x74,0x44,0x00,0x0c]
   bnvc $2, $4, 24          # CHECK: bnvc $2, $4, 24        # encoding: [0x7c,0x44,0x00,0x0c]
   bnvc $4, $2, 24          # CHECK: bnvc $4, $2, 24        # encoding: [0x7c,0x44,0x00,0x0c]
   and $3, 5                # CHECK: andi $3, $3, 5         # encoding: [0xd0,0x63,0x00,0x05]
   and $3, $4, 5            # CHECK: andi $3, $4, 5         # encoding: [0xd0,0x64,0x00,0x05]
   not $3, $4               # CHECK: not $3, $4             # encoding: [0x00,0x04,0x1a,0xd0]
   not $3                   # CHECK: not $3, $3             # encoding: [0x00,0x03,0x1a,0xd0]