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Differential D46744

AMDGPU: Make undef legal for v2i16/v2f16
ClosedPublic

Authored by arsenm on May 11 2018, 1:22 AM.

Details

Reviewers
rampitec
kzhuravl
cfang
Summary

This is apparently necessary to stop undef from being
turned into a build_vector of 0s.

Diff Detail

Event Timeline

arsenm created this revision.May 11 2018, 1:22 AM
Herald added subscribers: t-tye, tpr, dstuttard and 3 others. · View Herald TranscriptMay 11 2018, 1:22 AM
kzhuravl accepted this revision.May 11 2018, 1:39 AM

LGTM

This revision is now accepted and ready to land.May 11 2018, 1:39 AM
arsenm closed this revision.May 13 2018, 3:08 AM

r332195

Revision Contents

PathSize
lib/
Target/
AMDGPU/
3 lines
test/
CodeGen/
AMDGPU/
5 lines

Diff 146288

lib/Target/AMDGPU/SIISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 435 Lines • ▼ Show 20 Lines for (MVT VT : {MVT::v2i16, MVT::v2f16}) {
} }
} }
} }
// XXX - Do these do anything? Vector constants turn into build_vector. // XXX - Do these do anything? Vector constants turn into build_vector.
setOperationAction(ISD::Constant, MVT::v2i16, Legal); setOperationAction(ISD::Constant, MVT::v2i16, Legal);
setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal); setOperationAction(ISD::ConstantFP, MVT::v2f16, Legal);
setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
setOperationAction(ISD::STORE, MVT::v2i16, Promote); setOperationAction(ISD::STORE, MVT::v2i16, Promote);
AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32); AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
setOperationAction(ISD::STORE, MVT::v2f16, Promote); setOperationAction(ISD::STORE, MVT::v2f16, Promote);
AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32); AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
setOperationAction(ISD::LOAD, MVT::v2i16, Promote); setOperationAction(ISD::LOAD, MVT::v2i16, Promote);
AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32); AddPromotedToType(ISD::LOAD, MVT::v2i16, MVT::i32);
setOperationAction(ISD::LOAD, MVT::v2f16, Promote); setOperationAction(ISD::LOAD, MVT::v2f16, Promote);
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test/CodeGen/AMDGPU/llvm.amdgcn.cvt.pkrtz.ll

Show All 17 Lines
; GCN: s_load_dword [[X:s[0-9]+]] ; GCN: s_load_dword [[X:s[0-9]+]]
; GCN: v_cvt_pkrtz_f16_f32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]] ; GCN: v_cvt_pkrtz_f16_f32{{(_e64)*}} v{{[0-9]+}}, [[X]], [[X]]
define amdgpu_kernel void @s_cvt_pkrtz_samereg_v2f16_f32(<2 x half> addrspace(1)* %out, float %x) #0 { define amdgpu_kernel void @s_cvt_pkrtz_samereg_v2f16_f32(<2 x half> addrspace(1)* %out, float %x) #0 {
%result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float %x) %result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %x, float %x)
store <2 x half> %result, <2 x half> addrspace(1)* %out store <2 x half> %result, <2 x half> addrspace(1)* %out
ret void ret void
} }
; FIXME: Folds to 0 on gfx9
; GCN-LABEL: {{^}}s_cvt_pkrtz_undef_undef: ; GCN-LABEL: {{^}}s_cvt_pkrtz_undef_undef:
; GCN-NEXT: ; %bb.0 ; GCN-NEXT: ; %bb.0
; SI-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
; VI-NEXT: s_endpgm
; GFX9: v_mov_b32_e32 v{{[0-9]+}}, 0{{$}}
define amdgpu_kernel void @s_cvt_pkrtz_undef_undef(<2 x half> addrspace(1)* %out) #0 { define amdgpu_kernel void @s_cvt_pkrtz_undef_undef(<2 x half> addrspace(1)* %out) #0 {
%result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float undef) %result = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float undef)
store <2 x half> %result, <2 x half> addrspace(1)* %out store <2 x half> %result, <2 x half> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_cvt_pkrtz_v2f16_f32: ; GCN-LABEL: {{^}}v_cvt_pkrtz_v2f16_f32:
; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]] ; GCN: {{buffer|flat|global}}_load_dword [[A:v[0-9]+]]
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