[AMDGPU] Optimzed old value for dpp if unused

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

7402–7418

Can this be done earlier before selection?

[rampitec]

lib/Target/AMDGPU/SIISelLowering.cpp

7402–7418

Theoretically this can be done as early as in the AMDGPULibCalls. Unused old value can be replaced with undef.

Why do you think it is better? I do not see any optimization which may be done based on that. At the same time before the selection we have to work with an intrinsic and after we are working with the instruction itself. Given that we may have several intrinsics leading here in the future that maybe less code potentially.

[rampitec]

lib/Target/AMDGPU/SIISelLowering.cpp

7402–7418

Please check D46596, it is InstCombine based implementation.
It can be used separately or in conjunction with this one in case instruction [will] came from not from that intrinsic.

[rampitec]

Ping.

[arsenm]

lib/Target/AMDGPU/SIISelLowering.cpp

7402–7418

I really dislike doing anything in the awkward machine-selected DAG, and it's usually a last resort if nothing else works. Doing in the DAG or on the final machine instruction would be better if you think a later pass besides instcombine is helpful. Plus more code in the DAG is more code that needs to be rewritten on machine instructions in the future

[rampitec]

D46596 was committed instead.

lib/Target/AMDGPU/SIISelLowering.cpp

case AMDGPU::V_DIV_SCALE_F64: {
 
     SmallVector<SDValue, 4> Ops = { Src0, Src1, Src2 };
     for (unsigned I = 3, N = Node->getNumOperands(); I != N; ++I)
       Ops.push_back(Node->getOperand(I));
 
     Ops.push_back(ImpDef.getValue(1));
     return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
   }
+  case AMDGPU::V_MOV_B32_dpp: {
+    ConstantSDNode *RM = cast<ConstantSDNode>(Node->getOperand(3));
+    ConstantSDNode *BM = cast<ConstantSDNode>(Node->getOperand(4));
+    ConstantSDNode *BC = cast<ConstantSDNode>(Node->getOperand(5));
+    if (!BC->getZExtValue() ||
+        RM->getZExtValue() != 0xf || BM->getZExtValue() != 0xf)
+      break;
+    SDValue Old = Node->getOperand(0);
+    if (Old.isMachineOpcode() && Old.getMachineOpcode() == AMDGPU::IMPLICIT_DEF)
+      break;
+    MachineSDNode *ImpDef = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF,
+                                               SDLoc(Node), MVT::i32);
+    SmallVector<SDValue, 6> Ops = { SDValue(ImpDef, 0), Node->getOperand(1),
+                                    Node->getOperand(2), SDValue(RM, 0),
+                                    SDValue(BM, 0), SDValue(BC, 0) };
+    return DAG.getMachineNode(Opcode, SDLoc(Node), Node->getVTList(), Ops);
+  }
   default:
     break;
   }
 
   return Node;
 }
 
 /// Assign the register class depending on the number of

test/CodeGen/AMDGPU/llvm.amdgcn.update.dpp.ll

-; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-OPT %s
-; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=VI-NOOPT %s
+; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck --check-prefixes=GCN,GFX8 %s
 
-; VI-LABEL: {{^}}dpp_test:
-; VI: v_mov_b32_e32 v0, s{{[0-9]+}}
-; VI: v_mov_b32_e32 v1, s{{[0-9]+}}
-; VI: s_nop 1
-; VI: v_mov_b32_dpp v0, v1 quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0 ; encoding: [0xfa,0x02,0x00,0x7e,0x01,0x01,0x08,0x11]
+; GCN-LABEL: {{^}}dpp_test:
+; GCN: v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
+; GCN: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
+; GCN: s_nop 1
+; GCN: v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[1,0,0,0] row_mask:0x1 bank_mask:0x1{{$}}
 define amdgpu_kernel void @dpp_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
-  %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 1) #0
+  %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 1, i32 1, i32 1, i1 0) #0
+  store i32 %tmp0, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}dpp_test_bc:
+; GCN: v_mov_b32_e32 [[DST:v[0-9]+]], s{{[0-9]+}}
+; GCN: v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
+; GCN: s_nop 1
+; GCN: v_mov_b32_dpp [[DST]], [[SRC]] quad_perm:[2,0,0,0] row_mask:0x1 bank_mask:0x1 bound_ctrl:0{{$}}
+define amdgpu_kernel void @dpp_test_bc(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
+  %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 2, i32 1, i32 1, i1 1) #0
+  store i32 %tmp0, i32 addrspace(1)* %out
+  ret void
+}
+
+; GCN-LABEL: {{^}}dpp_noold_test:
+; GCN-NOT: v_mov_b32_e32
+; GCN:     v_mov_b32_e32 [[SRC:v[0-9]+]], s{{[0-9]+}}
+; GCN:     s_nop 1
+; GCN:     v_mov_b32_dpp v{{[0-9]+}}, [[SRC]] quad_perm:[3,0,0,0] row_mask:0xf bank_mask:0xf bound_ctrl:0{{$}}
+define amdgpu_kernel void @dpp_noold_test(i32 addrspace(1)* %out, i32 %in1, i32 %in2) {
+  %tmp0 = call i32 @llvm.amdgcn.update.dpp.i32(i32 %in1, i32 %in2, i32 3, i32 15, i32 15, i1 1) #0
   store i32 %tmp0, i32 addrspace(1)* %out
   ret void
 }
 
 declare i32 @llvm.amdgcn.update.dpp.i32(i32, i32, i32, i32, i32, i1) #0
 
 attributes #0 = { nounwind readnone convergent }