Add support for scalarizing ctlz_zero_undef

[petarj]

Summary

Fix the missing case in ScalarizeVectorResult() that was exposed with
libclcore.bc in Android.

[petarj]

ping

[arsenm]

LGTM

[chandlerc]

This seems fine (as Matt said) but don't you need to do the same for CTTZ?

[petarj]

In D4645#12, @chandlerc wrote:

This seems fine (as Matt said) but don't you need to do the same for CTTZ?

I was solving a particular failure, so this is why I have not included CTTZ_ZERO_UNDEF. But, yes, it should be done for CTTZ too.

I can update the case in ScalarizeVectorResult() with CTTZ.
(Or it should be another patch with additional test case?)

[petarj]

Closed by commit rL214266 (authored by @petarj).

llvm/trunk/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

#endif
   case ISD::SELECT:            R = ScalarizeVecRes_SELECT(N); break;
   case ISD::SELECT_CC:         R = ScalarizeVecRes_SELECT_CC(N); break;
   case ISD::SETCC:             R = ScalarizeVecRes_SETCC(N); break;
   case ISD::UNDEF:             R = ScalarizeVecRes_UNDEF(N); break;
   case ISD::VECTOR_SHUFFLE:    R = ScalarizeVecRes_VECTOR_SHUFFLE(N); break;
   case ISD::ANY_EXTEND:
   case ISD::BSWAP:
   case ISD::CTLZ:
+  case ISD::CTLZ_ZERO_UNDEF:
   case ISD::CTPOP:
   case ISD::CTTZ:
   case ISD::FABS:
   case ISD::FCEIL:
   case ISD::FCOS:
   case ISD::FEXP:
   case ISD::FEXP2:
   case ISD::FFLOOR:

llvm/trunk/test/CodeGen/Mips/ctlz-v.ll

+; RUN: llc  < %s -march=mipsel -mcpu=mips32r2 | FileCheck %s -check-prefix=MIPS32
+; RUN: llc  < %s -march=mips64el -mcpu=mips64r2 | FileCheck %s -check-prefix=MIPS64
+
+declare <2 x i32> @llvm.ctlz.v2i32(<2 x i32>, i1)
+
+define <2 x i32> @ctlzv2i32(<2 x i32> %x) {
+entry:
+; MIPS32: clz     $2, $4
+; MIPS32: jr      $ra
+; MIPS32: clz     $3, $5
+
+; MIPS64: clz     $2, $4
+; MIPS64: jr      $ra
+; MIPS64: clz     $3, $5
+
+  %ret = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true)
+  ret <2 x i32> %ret
+}
+