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Differential D46392

[mips] Enable disassembly of fused (negative) multiply add/sub instructions
ClosedPublic

Authored by sdardis on May 3 2018, 7:35 AM.

Details

Reviewers
atanasyan
smaksimovic
abeserminji
Commits
rGd4169ad7c149: [mips] Enable disassembly of fused (negative) multiply add/sub instructions
rL332097: [mips] Enable disassembly of fused (negative) multiply add/sub instructions

Diff Detail

Event Timeline

sdardis created this revision.May 3 2018, 7:35 AM
Herald added a subscriber: arichardson. · View Herald TranscriptMay 3 2018, 7:35 AM
atanasyan accepted this revision.May 4 2018, 12:24 AM

LGTM

This revision is now accepted and ready to land.May 4 2018, 12:24 AM
Closed by commit rL332097: [mips] Enable disassembly of fused (negative) multiply add/sub instructions (authored by sdardis). · Explain WhyMay 11 2018, 8:25 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
41 lines
41 lines
test/
MC/
Disassembler/
Mips/
micromips32r3/
8 lines
8 lines
Mips/
7 lines

Diff 145017

lib/Target/Mips/MicroMipsInstrFPU.td

Show First 20 Lines • Show All 191 Lines • ▼ Show 20 Lines
} }
let isCodeGenOnly = 1 in { let isCodeGenOnly = 1 in {
def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd, def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
II_MFC1, bitconvert>, MFC1_FM_MM<0x80>, II_MFC1, bitconvert>, MFC1_FM_MM<0x80>,
ISA_MICROMIPS; ISA_MICROMIPS;
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd, def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>, II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
ISA_MICROMIPS; ISA_MICROMIPS;
}
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, let DecoderNamespace = "MicroMips" in {
MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6; def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>,
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6; def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>,
MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6; MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>,
MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6; MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6;
}
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>,
MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, MADD4;
MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>,
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
MADD4;
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>,
MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>,
MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32; MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
} }
}
def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd, def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,
II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>, II_FLOOR>, ROUND_W_FM_MM<0, 0x2c>,
ISA_MICROMIPS; ISA_MICROMIPS;
def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd, def TRUNC_W_S_MM : MMRel, StdMMR6Rel, ABSS_FT<"trunc.w.s", FGR32Opnd,
FGR32Opnd, II_TRUNC>, FGR32Opnd, II_TRUNC>,
ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS; ROUND_W_FM_MM<0, 0xac>, ISA_MICROMIPS;
def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>, def CEIL_W_S_MM : MMRel, ABSS_FT<"ceil.w.s", FGR32Opnd, FGR32Opnd, II_CEIL>,
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lib/Target/Mips/MipsInstrFPU.td

Show First 20 Lines • Show All 600 Lines • ▼ Show 20 Lineslet AdditionalPredicates = [NotInMicroMips] in {
def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>, def FMUL_S : MMRel, ADDS_FT<"mul.s", FGR32Opnd, II_MUL_S, 1, fmul>,
ADDS_FM<0x02, 16>; ADDS_FM<0x02, 16>;
defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>; defm FMUL : ADDS_M<"mul.d", II_MUL_D, 1, fmul>, ADDS_FM<0x02, 17>;
def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>, def FSUB_S : MMRel, ADDS_FT<"sub.s", FGR32Opnd, II_SUB_S, 0, fsub>,
ADDS_FM<0x01, 16>; ADDS_FM<0x01, 16>;
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>; defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
} }
let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>, def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>, def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4; MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
}
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>, def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>, def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6; MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
} }
let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>, def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4; MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>, def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4; MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
}
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in { let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>, def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>, def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32; MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
} }
let AdditionalPredicates = [NotInMicroMips, HasMadd4, NotInMicroMips],
let DecoderNamespace = "MipsFP64" in { DecoderNamespace = "MipsFP64" in {
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>, def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>, def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4; MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
} }
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips],
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
DecoderNamespace = "MipsFP64" in { DecoderNamespace = "MipsFP64" in {
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>, def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>, def NMSUB_D64 : NMADDS_FT<"nmsub.d", FGR64Opnd, II_NMSUB_D, fsub>,
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64; MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
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test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

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0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2 0x02 0x54 0x7b 0x20 # CHECK: mov.d $f0, $f2
0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2 0x02 0x54 0x7b 0x2b # CHECK: neg.d $f0, $f2
0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2 0x02 0x54 0x3b 0x49 # CHECK: cvt.w.d $f0, $f2
0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2 0x02 0x54 0x7b 0x13 # CHECK: cvt.d.s $f0, $f2
0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2 0x02 0x54 0x7b 0x33 # CHECK: cvt.d.w $f0, $f2
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2 0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
0x07 0x00 0x7c 0x6b # CHECK: sync 7 0x07 0x00 0x7c 0x6b # CHECK: sync 7
0x03 0x42 0x00 0x04 # CHECK: synci 1024($3) 0x03 0x42 0x00 0x04 # CHECK: synci 1024($3)
0xc4 0x54 0x81 0x00 # CHECK: madd.s $f0, $f2, $f4, $f6
0xc4 0x54 0x89 0x00 # CHECK: madd.d $f0, $f2, $f4, $f6
0xc4 0x54 0x82 0x00 # CHECK: nmadd.s $f0, $f2, $f4, $f6
0xc4 0x54 0x8a 0x00 # CHECK: nmadd.d $f0, $f2, $f4, $f6
0xc4 0x54 0xa1 0x00 # CHECK: msub.s $f0, $f2, $f4, $f6
0xc4 0x54 0xa9 0x00 # CHECK: msub.d $f0, $f2, $f4, $f6
0xc4 0x54 0xa2 0x00 # CHECK: nmsub.s $f0, $f2, $f4, $f6
0xc4 0x54 0xaa 0x00 # CHECK: nmsub.d $f0, $f2, $f4, $f6

test/MC/Disassembler/Mips/micromips32r3/valid.txt

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0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4 0x54 0x82 0x01 0xb0 # CHECK: mul.d $f0, $f2, $f4
0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4 0x54 0x82 0x01 0xf0 # CHECK: div.d $f0, $f2, $f4
0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2 0x54 0x02 0x20 0x7b # CHECK: mov.d $f0, $f2
0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2 0x54 0x02 0x2b 0x7b # CHECK: neg.d $f0, $f2
0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2 0x54 0x02 0x49 0x3b # CHECK: cvt.w.d $f0, $f2
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2 0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2 0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2 0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
0x54 0xc4 0x00 0x81 # CHECK: madd.s $f0, $f2, $f4, $f6
0x54 0xc4 0x00 0x89 # CHECK: madd.d $f0, $f2, $f4, $f6
0x54 0xc4 0x00 0x82 # CHECK: nmadd.s $f0, $f2, $f4, $f6
0x54 0xc4 0x00 0x8a # CHECK: nmadd.d $f0, $f2, $f4, $f6
0x54 0xc4 0x00 0xa1 # CHECK: msub.s $f0, $f2, $f4, $f6
0x54 0xc4 0x00 0xa9 # CHECK: msub.d $f0, $f2, $f4, $f6
0x54 0xc4 0x00 0xa2 # CHECK: nmsub.s $f0, $f2, $f4, $f6
0x54 0xc4 0x00 0xaa # CHECK: nmsub.d $f0, $f2, $f4, $f6

test/MC/Mips/micromips-fpu-instructions.s

Show First 20 Lines • Show All 147 Lines • ▼ Show 20 Lines
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_S_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_S_MM
# CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60] # CHECK-EB: movt.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x60]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_D32_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVT_D32_MM
# CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20] # CHECK-EB: movf.s $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x00,0x20]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_S_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_S_MM
# CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20] # CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM # CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM
# CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01] # CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MADD_S_MM
# CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09] # CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MADD_D32_MM
# CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21] # CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MSUB_S_MM
# CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29] # CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MSUB_D32_MM
# CHECK-EB: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x02] # CHECK-EB: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x02]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMADD_S_MM
# CHECK-EB: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x0a] # CHECK-EB: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x0a]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMADD_D32_MM
# CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22] # CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22]
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMSUB_S_MM
# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a] # CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
add.s $f4, $f6, $f8 add.s $f4, $f6, $f8
add.d $f4, $f6, $f8 add.d $f4, $f6, $f8
div.s $f4, $f6, $f8 div.s $f4, $f6, $f8
div.d $f4, $f6, $f8 div.d $f4, $f6, $f8
mul.s $f4, $f6, $f8 mul.s $f4, $f6, $f8
mul.d $f4, $f6, $f8 mul.d $f4, $f6, $f8
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