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Commit d4169ad

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author
Simon Dardis
committedMay 11, 2018
[mips] Enable disassembly of fused (negative) multiply add/sub instructions
Reviewers: atanasyan, smaksimovic, abeserminji Differential Revision: https://reviews.llvm.org/D46392 llvm-svn: 332097
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-37
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‎llvm/lib/Target/Mips/MicroMipsInstrFPU.td

+24-17
Original file line numberDiff line numberDiff line change
@@ -197,24 +197,31 @@ def MFC1_MM : MMRel, MFC1_FT<"mfc1", GPR32Opnd, FGR32Opnd,
197197
def MTC1_MM : MMRel, MTC1_FT<"mtc1", FGR32Opnd, GPR32Opnd,
198198
II_MTC1, bitconvert>, MFC1_FM_MM<0xa0>,
199199
ISA_MICROMIPS;
200+
}
200201

201-
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
202-
MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6;
203-
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
204-
MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6;
205-
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
206-
MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
207-
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
208-
MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6;
209-
210-
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
211-
MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
212-
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
213-
MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
214-
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
215-
MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
216-
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
217-
MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
202+
let DecoderNamespace = "MicroMips" in {
203+
def MADD_S_MM : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S>,
204+
MADDS_FM_MM<0x1>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
205+
def MSUB_S_MM : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S>,
206+
MADDS_FM_MM<0x21>, ISA_MICROMIPS32_NOT_MIPS32R6, MADD4;
207+
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
208+
def NMADD_S_MM : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S>,
209+
MADDS_FM_MM<0x2>, ISA_MICROMIPS32_NOT_MIPS32R6;
210+
def NMSUB_S_MM : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S>,
211+
MADDS_FM_MM<0x22>, ISA_MICROMIPS32_NOT_MIPS32R6;
212+
}
213+
def MADD_D32_MM : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D>,
214+
MADDS_FM_MM<0x9>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
215+
MADD4;
216+
def MSUB_D32_MM : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D>,
217+
MADDS_FM_MM<0x29>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32,
218+
MADD4;
219+
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
220+
def NMADD_D32_MM : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D>,
221+
MADDS_FM_MM<0xa>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
222+
def NMSUB_D32_MM : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D>,
223+
MADDS_FM_MM<0x2a>, ISA_MICROMIPS32_NOT_MIPS32R6, FGR_32;
224+
}
218225
}
219226

220227
def FLOOR_W_S_MM : MMRel, ABSS_FT<"floor.w.s", FGR32Opnd, FGR32Opnd,

‎llvm/lib/Target/Mips/MipsInstrFPU.td

+21-20
Original file line numberDiff line numberDiff line change
@@ -606,38 +606,39 @@ let AdditionalPredicates = [NotInMicroMips] in {
606606
defm FSUB : ADDS_M<"sub.d", II_SUB_D, 0, fsub>, ADDS_FM<0x01, 17>;
607607
}
608608

609-
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
610-
MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
611-
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
612-
MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6, MADD4;
609+
let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
610+
def MADD_S : MMRel, MADDS_FT<"madd.s", FGR32Opnd, II_MADD_S, fadd>,
611+
MADDS_FM<4, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
612+
def MSUB_S : MMRel, MADDS_FT<"msub.s", FGR32Opnd, II_MSUB_S, fsub>,
613+
MADDS_FM<5, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
614+
}
613615

614-
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
616+
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
615617
def NMADD_S : MMRel, NMADDS_FT<"nmadd.s", FGR32Opnd, II_NMADD_S, fadd>,
616618
MADDS_FM<6, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
617619
def NMSUB_S : MMRel, NMADDS_FT<"nmsub.s", FGR32Opnd, II_NMSUB_S, fsub>,
618620
MADDS_FM<7, 0>, INSN_MIPS4_32R2_NOT_32R6_64R6;
619621
}
620-
621-
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
622-
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
623-
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
624-
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32, MADD4;
625-
626-
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4] in {
622+
let AdditionalPredicates = [NotInMicroMips, HasMadd4] in {
623+
def MADD_D32 : MMRel, MADDS_FT<"madd.d", AFGR64Opnd, II_MADD_D, fadd>,
624+
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
625+
def MSUB_D32 : MMRel, MADDS_FT<"msub.d", AFGR64Opnd, II_MSUB_D, fsub>,
626+
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
627+
}
628+
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips] in {
627629
def NMADD_D32 : MMRel, NMADDS_FT<"nmadd.d", AFGR64Opnd, II_NMADD_D, fadd>,
628630
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
629631
def NMSUB_D32 : MMRel, NMADDS_FT<"nmsub.d", AFGR64Opnd, II_NMSUB_D, fsub>,
630632
MADDS_FM<7, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_32;
631633
}
632-
633-
let DecoderNamespace = "MipsFP64" in {
634-
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
635-
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
636-
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
637-
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64, MADD4;
634+
let AdditionalPredicates = [NotInMicroMips, HasMadd4, NotInMicroMips],
635+
DecoderNamespace = "MipsFP64" in {
636+
def MADD_D64 : MADDS_FT<"madd.d", FGR64Opnd, II_MADD_D, fadd>,
637+
MADDS_FM<4, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
638+
def MSUB_D64 : MADDS_FT<"msub.d", FGR64Opnd, II_MSUB_D, fsub>,
639+
MADDS_FM<5, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;
638640
}
639-
640-
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4],
641+
let AdditionalPredicates = [NoNaNsFPMath, HasMadd4, NotInMicroMips],
641642
DecoderNamespace = "MipsFP64" in {
642643
def NMADD_D64 : NMADDS_FT<"nmadd.d", FGR64Opnd, II_NMADD_D, fadd>,
643644
MADDS_FM<6, 1>, INSN_MIPS4_32R2_NOT_32R6_64R6, FGR_64;

‎llvm/test/MC/Disassembler/Mips/micromips32r3/valid-el.txt

+8
Original file line numberDiff line numberDiff line change
@@ -234,3 +234,11 @@
234234
0x02 0x54 0x7b 0x1b # CHECK: cvt.s.d $f0, $f2
235235
0x07 0x00 0x7c 0x6b # CHECK: sync 7
236236
0x03 0x42 0x00 0x04 # CHECK: synci 1024($3)
237+
0xc4 0x54 0x81 0x00 # CHECK: madd.s $f0, $f2, $f4, $f6
238+
0xc4 0x54 0x89 0x00 # CHECK: madd.d $f0, $f2, $f4, $f6
239+
0xc4 0x54 0x82 0x00 # CHECK: nmadd.s $f0, $f2, $f4, $f6
240+
0xc4 0x54 0x8a 0x00 # CHECK: nmadd.d $f0, $f2, $f4, $f6
241+
0xc4 0x54 0xa1 0x00 # CHECK: msub.s $f0, $f2, $f4, $f6
242+
0xc4 0x54 0xa9 0x00 # CHECK: msub.d $f0, $f2, $f4, $f6
243+
0xc4 0x54 0xa2 0x00 # CHECK: nmsub.s $f0, $f2, $f4, $f6
244+
0xc4 0x54 0xaa 0x00 # CHECK: nmsub.d $f0, $f2, $f4, $f6

‎llvm/test/MC/Disassembler/Mips/micromips32r3/valid.txt

+8
Original file line numberDiff line numberDiff line change
@@ -236,3 +236,11 @@
236236
0x54 0x02 0x13 0x7b # CHECK: cvt.d.s $f0, $f2
237237
0x54 0x02 0x33 0x7b # CHECK: cvt.d.w $f0, $f2
238238
0x54 0x02 0x1b 0x7b # CHECK: cvt.s.d $f0, $f2
239+
0x54 0xc4 0x00 0x81 # CHECK: madd.s $f0, $f2, $f4, $f6
240+
0x54 0xc4 0x00 0x89 # CHECK: madd.d $f0, $f2, $f4, $f6
241+
0x54 0xc4 0x00 0x82 # CHECK: nmadd.s $f0, $f2, $f4, $f6
242+
0x54 0xc4 0x00 0x8a # CHECK: nmadd.d $f0, $f2, $f4, $f6
243+
0x54 0xc4 0x00 0xa1 # CHECK: msub.s $f0, $f2, $f4, $f6
244+
0x54 0xc4 0x00 0xa9 # CHECK: msub.d $f0, $f2, $f4, $f6
245+
0x54 0xc4 0x00 0xa2 # CHECK: nmsub.s $f0, $f2, $f4, $f6
246+
0x54 0xc4 0x00 0xaa # CHECK: nmsub.d $f0, $f2, $f4, $f6

‎llvm/test/MC/Mips/micromips-fpu-instructions.s

+7
Original file line numberDiff line numberDiff line change
@@ -153,12 +153,19 @@
153153
# CHECK-EB: movf.d $f4, $f6, $fcc0 # encoding: [0x54,0x86,0x02,0x20]
154154
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MOVF_D32_MM
155155
# CHECK-EB: madd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x01]
156+
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MADD_S_MM
156157
# CHECK-EB: madd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x09]
158+
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MADD_D32_MM
157159
# CHECK-EB: msub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x21]
160+
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MSUB_S_MM
158161
# CHECK-EB: msub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x29]
162+
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} MSUB_D32_MM
159163
# CHECK-EB: nmadd.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x02]
164+
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMADD_S_MM
160165
# CHECK-EB: nmadd.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x0a]
166+
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMADD_D32_MM
161167
# CHECK-EB: nmsub.s $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x22]
168+
# CHECK-EB-NEXT: # <MCInst #{{[0-9]+}} NMSUB_S_MM
162169
# CHECK-EB: nmsub.d $f2, $f4, $f6, $f8 # encoding: [0x55,0x06,0x11,0x2a]
163170

164171
add.s $f4, $f6, $f8

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