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Differential D46154

[AMDGPU][Waitcnt] Update a few lit tests to use the default waitcnt pass
ClosedPublic

Authored by msearles on Apr 26 2018, 4:41 PM.

Details

Reviewers
cfang
FarhanaAleen
Commits
rGa6322924e698: [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert…
rL331062: [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert…
Summary

Update a few tests to use default waitcnt pass (si-insert-waitcnts) rather than old pass (si-insert-waits); this is a small step towards the overall goal of removing the old waitcnt pass, which is no longer maintained.

Note for the reviewer: For the renamed files, the only changes to those files are within the RUN cmds: s/si-insert-waits/si-insert-waitcnts

Diff Detail

Repository
rL LLVM

Event Timeline

msearles created this revision.Apr 26 2018, 4:41 PM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptApr 26 2018, 4:41 PM
msearles added reviewers: cfang, FarhanaAleen.Apr 26 2018, 4:42 PM
msearles added a project: Restricted Project.
msearles added a subscriber: llvm-commits.
cfang accepted this revision.Apr 27 2018, 9:51 AM

LGTM

This revision is now accepted and ready to land.Apr 27 2018, 9:51 AM
Closed by commit rL331062: [AMDGPU][Waitcnt] Update a few tests to use default waitcnt pass (si-insert… (authored by msearles). · Explain WhyApr 27 2018, 11:02 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

Diff 144370

llvm/trunk/test/CodeGen/AMDGPU/insert-waitcnts-callee.mir

# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s
--- |
define float @entry_callee_wait(float %arg) #0 {
ret float %arg
}
attributes #0 = { nounwind }
...
---
# CHECK-LABEL: name: entry_callee_wait{{$}}
# CHECK: bb.0:
# CHECK-NEXT: S_WAITCNT 0{{$}}
# CHECK-NEXT: V_ADD_F32
# CHECK-NEXT: S_SETPC_B64
liveins:
- { reg: '$sgpr0_sgpr1' }
- { reg: '$vgpr0' }
name: entry_callee_wait
body: |
bb.0:
$vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $exec
S_SETPC_B64 killed $sgpr0_sgpr1
...

llvm/trunk/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir

# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s
--- |
define amdgpu_ps <4 x float> @exp_done_waitcnt(<4 x i32> inreg, <4 x
i32> inreg, i32 inreg %w, float %v) #0 {
%a = load volatile float, float addrspace(1)* undef
%b = load volatile float, float addrspace(1)* undef
%c = load volatile float, float addrspace(1)* undef
%d = load volatile float, float addrspace(1)* undef
call void @llvm.amdgcn.exp.f32(i32 15, i32 1, float %a, float %b, float %c, float %d, i1 true, i1 false)
ret <4 x float> <float 5.000000e-01, float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>
}
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
attributes #0 = { nounwind }
...
---
# CHECK-LABEL: name: exp_done_waitcnt{{$}}
# CHECK: EXP_DONE
# CHECK-NEXT: S_WAITCNT 3855
# CHECK: $vgpr0 = V_MOV_B32
# CHECK: $vgpr1 = V_MOV_B32
# CHECK: $vgpr2 = V_MOV_B32
# CHECK: $vgpr3 = V_MOV_B32
name: exp_done_waitcnt
alignment: 0
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.2):
$sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr3 = BUFFER_LOAD_DWORD_OFFSET killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
EXP_DONE 0, killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3, -1, -1, 15, implicit $exec
$vgpr0 = V_MOV_B32_e32 1056964608, implicit $exec
$vgpr1 = V_MOV_B32_e32 1065353216, implicit $exec
$vgpr2 = V_MOV_B32_e32 1073741824, implicit $exec
$vgpr3 = V_MOV_B32_e32 1082130432, implicit $exec
SI_RETURN_TO_EPILOG killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3
...

llvm/trunk/test/CodeGen/AMDGPU/insert-waits-callee.mir

# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -run-pass si-insert-waits -o - %s | FileCheck %s
--- |
define float @entry_callee_wait(float %arg) #0 {
ret float %arg
}
attributes #0 = { nounwind }
...
---
# CHECK-LABEL: name: entry_callee_wait{{$}}
# CHECK: bb.0:
# CHECK-NEXT: S_WAITCNT 0{{$}}
# CHECK-NEXT: V_ADD_F32
# CHECK-NEXT: S_SETPC_B64
liveins:
- { reg: '$sgpr0_sgpr1' }
- { reg: '$vgpr0' }
name: entry_callee_wait
body: |
bb.0:
$vgpr0 = V_ADD_F32_e32 $vgpr0, $vgpr0, implicit $exec
S_SETPC_B64 killed $sgpr0_sgpr1
...

llvm/trunk/test/CodeGen/AMDGPU/insert-waits-exp.mir

# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-insert-waits -o - %s | FileCheck %s
--- |
define amdgpu_ps <4 x float> @exp_done_waitcnt(<4 x i32> inreg, <4 x
i32> inreg, i32 inreg %w, float %v) #0 {
%a = load volatile float, float addrspace(1)* undef
%b = load volatile float, float addrspace(1)* undef
%c = load volatile float, float addrspace(1)* undef
%d = load volatile float, float addrspace(1)* undef
call void @llvm.amdgcn.exp.f32(i32 15, i32 1, float %a, float %b, float %c, float %d, i1 true, i1 false)
ret <4 x float> <float 5.000000e-01, float 1.000000e+00, float 2.000000e+00, float 4.000000e+00>
}
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
attributes #0 = { nounwind }
...
---
# CHECK-LABEL: name: exp_done_waitcnt{{$}}
# CHECK: EXP_DONE
# CHECK-NEXT: S_WAITCNT 3855
# CHECK: $vgpr0 = V_MOV_B32
# CHECK: $vgpr1 = V_MOV_B32
# CHECK: $vgpr2 = V_MOV_B32
# CHECK: $vgpr3 = V_MOV_B32
name: exp_done_waitcnt
alignment: 0
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
tracksRegLiveness: true
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 0
offsetAdjustment: 0
maxAlignment: 0
adjustsStack: false
hasCalls: false
maxCallFrameSize: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
body: |
bb.0 (%ir-block.2):
$sgpr3 = S_MOV_B32 61440
$sgpr2 = S_MOV_B32 -1
$vgpr0 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr2 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
$vgpr3 = BUFFER_LOAD_DWORD_OFFSET killed $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, 0, implicit $exec :: (volatile load 4 from `float addrspace(1)* undef`)
EXP_DONE 0, killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3, -1, -1, 15, implicit $exec
$vgpr0 = V_MOV_B32_e32 1056964608, implicit $exec
$vgpr1 = V_MOV_B32_e32 1065353216, implicit $exec
$vgpr2 = V_MOV_B32_e32 1073741824, implicit $exec
$vgpr3 = V_MOV_B32_e32 1082130432, implicit $exec
SI_RETURN_TO_EPILOG killed $vgpr0, killed $vgpr1, killed $vgpr2, killed $vgpr3
...

llvm/trunk/test/CodeGen/AMDGPU/scalar-store-cache-flush.mir

# RUN: llc -march=amdgcn -run-pass si-insert-waits %s -o - | FileCheck %s # RUN: llc -march=amdgcn -run-pass si-insert-waitcnts %s -o - | FileCheck %s
--- | --- |
define amdgpu_kernel void @basic_insert_dcache_wb() { define amdgpu_kernel void @basic_insert_dcache_wb() {
ret void ret void
} }
define amdgpu_kernel void @explicit_flush_after() { define amdgpu_kernel void @explicit_flush_after() {
ret void ret void
▲ Show 20 Lines • Show All 164 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/waitcnt-permute.mir

# RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass si-insert-waits -o - %s | FileCheck %s # RUN: llc -mtriple=amdgcn -mcpu=fiji -verify-machineinstrs -run-pass si-insert-waitcnts -o - %s | FileCheck %s
... ...
# CHECK-LABEL: name: waitcnt-permute{{$}} # CHECK-LABEL: name: waitcnt-permute{{$}}
# CHECK: DS_BPERMUTE_B32 # CHECK: DS_BPERMUTE_B32
# CHECK-NEXT: S_WAITCNT 127 # CHECK-NEXT: S_WAITCNT 127
name: waitcnt-permute name: waitcnt-permute
liveins: liveins:
Show All 12 Lines
llvm/trunk/test/CodeGen/AMDGPU/insert-waitcnts-exp.mir