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Differential D46151

AMDGPU/GlobalISel: Implement select() for COPY
ClosedPublic

Authored by tstellar on Apr 26 2018, 4:16 PM.

Details

Reviewers
arsenm
nhaehnle
Commits
rG7712ee8891dc: AMDGPU/GlobalISel: Implement select() for COPY
rL335315: AMDGPU/GlobalISel: Implement select() for COPY

Diff Detail

Repository
rL LLVM

Event Timeline

tstellar created this revision.Apr 26 2018, 4:16 PM
Herald added subscribers: t-tye, tpr, dstuttard and 5 others. · View Herald TranscriptApr 26 2018, 4:16 PM
Harbormaster completed remote builds in B17476: Diff 144234.Apr 26 2018, 4:17 PM
nhaehnle accepted this revision.Apr 30 2018, 1:11 AM

LGTM

This revision is now accepted and ready to land.Apr 30 2018, 1:11 AM
Closed by commit rL335315: AMDGPU/GlobalISel: Implement select() for COPY (authored by tstellar). · Explain WhyJun 21 2018, 5:49 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
llvm/
trunk/
lib/
Target/
AMDGPU/
5 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
27 lines

Diff 152417

llvm/trunk/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Show First 20 Lines • Show All 522 Lines • ▼ Show 20 Linesbool AMDGPUInstructionSelector::selectG_LOAD(MachineInstr &I) const {
bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI); bool Ret = constrainSelectedInstRegOperands(*Flat, TII, TRI, RBI);
I.eraseFromParent(); I.eraseFromParent();
return Ret; return Ret;
} }
bool AMDGPUInstructionSelector::select(MachineInstr &I, bool AMDGPUInstructionSelector::select(MachineInstr &I,
CodeGenCoverage &CoverageInfo) const { CodeGenCoverage &CoverageInfo) const {
if (!isPreISelGenericOpcode(I.getOpcode())) if (!isPreISelGenericOpcode(I.getOpcode())) {
if (I.isCopy())
return selectCOPY(I);
return true; return true;
}
switch (I.getOpcode()) { switch (I.getOpcode()) {
default: default:
break; break;
case TargetOpcode::G_FMUL: case TargetOpcode::G_FMUL:
case TargetOpcode::G_FADD: case TargetOpcode::G_FADD:
case TargetOpcode::G_FPTOUI: case TargetOpcode::G_FPTOUI:
case TargetOpcode::G_OR: case TargetOpcode::G_OR:
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

llvm/trunk/test/CodeGen/AMDGPU/GlobalISel/inst-select-copy.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN
--- |
define amdgpu_kernel void @copy(i32 addrspace(1)* %global0) {ret void}
...
---
name: copy
legalized: true
regBankSelected: true
body: |
bb.0:
liveins: $sgpr2_sgpr3
; GCN-LABEL: name: copy
; GCN: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr2_sgpr3
; GCN: [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; GCN: FLAT_STORE_DWORD [[COPY1]], [[DEF]], 0, 0, 0, implicit $exec, implicit $flat_scr
%0:sgpr(s64) = COPY $sgpr2_sgpr3
%1:vgpr(s64) = COPY %0
%2:vgpr(s32) = G_IMPLICIT_DEF
G_STORE %2, %1 :: (store 4 into %ir.global0)
...
---