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Differential D46055

[mips] Fix microMIPS loads and stores.
ClosedPublic

Authored by sdardis on Apr 25 2018, 6:04 AM.

Details

Reviewers
atanasyan
smaksimovic
abeserminji
Commits
rG57c2095d1b40: [mips] Fix microMIPS loads and stores.
rL331165: [mips] Fix microMIPS loads and stores.
Summary

Previously these instructions were unselectable and instead were generated
through the instruction mapping tables.

Diff Detail

Event Timeline

sdardis created this revision.Apr 25 2018, 6:04 AM
Herald added a subscriber: arichardson. · View Herald TranscriptApr 25 2018, 6:04 AM
Harbormaster completed remote builds in B17406: Diff 143913.Apr 25 2018, 6:05 AM
atanasyan added a comment.Apr 27 2018, 12:09 AM

Please rebase the patch.

sdardis updated this revision to Diff 144329.Apr 27 2018, 6:37 AM

Rebase and fix check lines for error messages.

atanasyan accepted this revision.Apr 28 2018, 12:15 AM

LGTM

This revision is now accepted and ready to land.Apr 28 2018, 12:15 AM
Closed by commit rL331165: [mips] Fix microMIPS loads and stores. (authored by sdardis). · Explain WhyApr 30 2018, 2:48 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
Mips/
44 lines
30 lines
test/
CodeGen/
Mips/
llvm-ir/
1022 lines
494 lines

Diff 143913

lib/Target/Mips/MicroMipsInstrInfo.td

Show First 20 Lines • Show All 762 Lines • ▼ Show 20 Lineslet DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in {
def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>, def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>,
SRLV_FM_MM<0xd0, 0> { SRLV_FM_MM<0xd0, 0> {
list<dag> Pattern = [(set GPR32Opnd:$rd, list<dag> Pattern = [(set GPR32Opnd:$rd,
(rotr GPR32Opnd:$rt, GPR32Opnd:$rs))]; (rotr GPR32Opnd:$rt, GPR32Opnd:$rs))];
} }
/// Load and Store Instructions - aligned /// Load and Store Instructions - aligned
let DecoderMethod = "DecodeMemMMImm16" in { let DecoderMethod = "DecodeMemMMImm16" in {
def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, null_frag, II_LB>, def LB_MM : LoadMemory<"lb", GPR32Opnd, mem_mm_16, sextloadi8, II_LB>,
MMRel, LW_FM_MM<0x7>; MMRel, LW_FM_MM<0x7>, ISA_MICROMIPS;
def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, null_frag, II_LBU>, def LBu_MM : LoadMemory<"lbu", GPR32Opnd, mem_mm_16, zextloadi8, II_LBU>,
MMRel, LW_FM_MM<0x5>; MMRel, LW_FM_MM<0x5>, ISA_MICROMIPS;
def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, def LH_MM : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
addrDefault>, MMRel, LW_FM_MM<0xf>; addrDefault>, MMRel, LW_FM_MM<0xf>, ISA_MICROMIPS;
def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, def LHu_MM : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
MMRel, LW_FM_MM<0xd>; MMRel, LW_FM_MM<0xd>, ISA_MICROMIPS;
def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>; def LW_MM : Load<"lw", GPR32Opnd, null_frag, II_LW>, MMRel, LW_FM_MM<0x3f>,
def SB_MM : Store<"sb", GPR32Opnd, null_frag, II_SB>, MMRel, ISA_MICROMIPS;
LW_FM_MM<0x6>; def SB_MM : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
def SH_MM : Store<"sh", GPR32Opnd, null_frag, II_SH>, MMRel, LW_FM_MM<0x6>, ISA_MICROMIPS;
LW_FM_MM<0xe>; def SH_MM : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel,
LW_FM_MM<0xe>, ISA_MICROMIPS;
def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel, def SW_MM : Store<"sw", GPR32Opnd, null_frag, II_SW>, MMRel,
LW_FM_MM<0x3e>; LW_FM_MM<0x3e>, ISA_MICROMIPS;
} }
} }
let DecoderNamespace = "MicroMips" in { let DecoderNamespace = "MicroMips" in {
let DecoderMethod = "DecodeMemMMImm9" in { let DecoderMethod = "DecodeMemMMImm9" in {
def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>, def LBE_MM : MMRel, Load<"lbe", GPR32Opnd, null_frag, II_LBE>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA; POOL32C_LHUE_FM_MM<0x18, 0x6, 0x4>, ISA_MICROMIPS, ASE_EVA;
def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>, def LBuE_MM : MMRel, Load<"lbue", GPR32Opnd, null_frag, II_LBUE>,
POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA; POOL32C_LHUE_FM_MM<0x18, 0x6, 0x0>, ISA_MICROMIPS, ASE_EVA;
▲ Show 20 Lines • Show All 332 Lines • ▼ Show 20 Lines def : MipsPat<(store GPR32:$src, addr:$addr),
(SW_MM GPR32:$src, addr:$addr)>; (SW_MM GPR32:$src, addr:$addr)>;
def : MipsPat<(load addrimm4lsl2:$addr), def : MipsPat<(load addrimm4lsl2:$addr),
(LW16_MM addrimm4lsl2:$addr)>; (LW16_MM addrimm4lsl2:$addr)>;
def : MipsPat<(load addr:$addr), def : MipsPat<(load addr:$addr),
(LW_MM addr:$addr)>; (LW_MM addr:$addr)>;
def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs), def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
(SUBu_MM GPR32:$lhs, GPR32:$rhs)>; (SUBu_MM GPR32:$lhs, GPR32:$rhs)>;
def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_MM addr:$src)>,
ISA_MICROMIPS;
def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_MM addr:$src)>,
ISA_MICROMIPS;
def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_MM addr:$src)>,
ISA_MICROMIPS;
let AddedComplexity = 40 in
def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
(LH_MM addrRegImm:$a)>, ISA_MICROMIPS;
} }
def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>, def : MipsPat<(bswap GPR32:$rt), (ROTR_MM (WSBH_MM GPR32:$rt), 16)>,
ISA_MICROMIPS; ISA_MICROMIPS;
def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)), def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
(TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6; (TAILCALL_MM tglobaladdr:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)), def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
(TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6; (TAILCALL_MM texternalsym:$dst)>, ISA_MICROMIPS32_NOT_MIPS32R6;
let AddedComplexity = 40 in {
def : MipsPat<(i32 (sextloadi16 addrRegImm:$a)),
(LH_MM addrRegImm:$a)>;
}
def : MipsPat<(atomic_load_16 addr:$a), def : MipsPat<(atomic_load_16 addr:$a),
(LH_MM addr:$a)>; (LH_MM addr:$a)>;
def : MipsPat<(i32 (extloadi16 addr:$src)),
(LHu_MM addr:$src)>;
defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM, defm : BrcondPats<GPR32, BEQ_MM, BEQ_MM, BNE_MM, SLT_MM, SLTu_MM, SLTi_MM,
SLTiu_MM, ZERO>; SLTiu_MM, ZERO>;
defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>; defm : SeteqPats<GPR32, SLTiu_MM, XOR_MM, SLTu_MM, ZERO>;
defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; defm : SetlePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>; defm : SetgtPats<GPR32, SLT_MM, SLTu_MM>;
defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>; defm : SetgePats<GPR32, XORi_MM, SLT_MM, SLTu_MM>;
▲ Show 20 Lines • Show All 105 Lines • Show Last 20 Lines

lib/Target/Mips/MipsInstrInfo.td

Show First 20 Lines • Show All 1,991 Lines • ▼ Show 20 Lines def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
immZExt5>, immZExt5>,
SRA_FM<2, 1>, ISA_MIPS32R2; SRA_FM<2, 1>, ISA_MIPS32R2;
def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>, def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
SRLV_FM<6, 1>, ISA_MIPS32R2; SRLV_FM<6, 1>, ISA_MIPS32R2;
} }
/// Load and Store Instructions /// Load and Store Instructions
/// aligned /// aligned
let AdditionalPredicates = [NotInMicroMips] in {
def LB : LoadMemory<"lb", GPR32Opnd, mem_simm16, sextloadi8, II_LB>, MMRel, def LB : LoadMemory<"lb", GPR32Opnd, mem_simm16, sextloadi8, II_LB>, MMRel,
LW_FM<0x20>; LW_FM<0x20>;
def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simm16, zextloadi8, II_LBU, def LBu : LoadMemory<"lbu", GPR32Opnd, mem_simm16, zextloadi8, II_LBU,
addrDefault>, MMRel, LW_FM<0x24>; addrDefault>, MMRel, LW_FM<0x24>;
let AdditionalPredicates = [NotInMicroMips] in {
def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH, def LH : LoadMemory<"lh", GPR32Opnd, mem_simm16, sextloadi16, II_LH,
addrDefault>, MMRel, LW_FM<0x21>; addrDefault>, MMRel, LW_FM<0x21>;
def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>, def LHu : LoadMemory<"lhu", GPR32Opnd, mem_simm16, zextloadi16, II_LHU>,
MMRel, LW_FM<0x25>; MMRel, LW_FM<0x25>;
def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel, def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
LW_FM<0x23>; LW_FM<0x23>;
}
def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
LW_FM<0x28>; LW_FM<0x28>;
def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>; def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
let AdditionalPredicates = [NotInMicroMips] in {
def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>; def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
} }
/// load/store left/right /// load/store left/right
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>, def LWL : MMRel, LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>, def LWR : MMRel, LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
ISA_MIPS1_NOT_32R6_64R6; ISA_MIPS1_NOT_32R6_64R6;
▲ Show 20 Lines • Show All 902 Lines • ▼ Show 20 Lines
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
// Mips does not have "not", so we expand our way // Mips does not have "not", so we expand our way
def : MipsPat<(not GPR32:$in), def : MipsPat<(not GPR32:$in),
(NOR GPR32Opnd:$in, ZERO)>; (NOR GPR32Opnd:$in, ZERO)>;
} }
// extended loads // extended loads
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>; def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>; def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>; def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
} }
// peepholes // peepholes
def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>; def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
// brcond patterns // brcond patterns
multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1, multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BEQOp1,
▲ Show 20 Lines • Show All 86 Lines • ▼ Show 20 Lineslet AdditionalPredicates = [NotInMicroMips] in {
defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>; defm : SetgeImmPats<GPR32, XORi, SLTi, SLTiu>;
// bswap pattern // bswap pattern
def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2; def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>, ISA_MIPS32R2;
} }
// Load halfword/word patterns. // Load halfword/word patterns.
let AddedComplexity = 40 in { let AddedComplexity = 40 in {
def : LoadRegImmPat<LBu, i32, zextloadi8>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : LoadRegImmPat<LH, i32, sextloadi16>; def : LoadRegImmPat<LBu, i32, zextloadi8>, ISA_MIPS1;
def : LoadRegImmPat<LW, i32, load>; def : LoadRegImmPat<LHu, i32, zextloadi16>, ISA_MIPS1;
def : LoadRegImmPat<LB, i32, sextloadi8>, ISA_MIPS1;
def : LoadRegImmPat<LH, i32, sextloadi16>, ISA_MIPS1;
def : LoadRegImmPat<LW, i32, load>, ISA_MIPS1;
} }
} }
// Atomic load patterns. // Atomic load patterns.
def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>; def : MipsPat<(atomic_load_8 addr:$a), (LB addr:$a)>;
let AdditionalPredicates = [NotInMicroMips] in { let AdditionalPredicates = [NotInMicroMips] in {
def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>; def : MipsPat<(atomic_load_16 addr:$a), (LH addr:$a)>;
} }
▲ Show 20 Lines • Show All 52 Lines • Show Last 20 Lines

test/CodeGen/Mips/llvm-ir/load.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips3 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS3
; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips64 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64
; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
; Test subword and word loads.
@a = common global i8 0, align 4
@b = common global i16 0, align 4
@c = common global i32 0, align 4
@d = common global i64 0, align 8
define i8 @f1() {
; MIPS32-LABEL: f1:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
; MIPS32-NEXT: # <MCOperand Reg:321>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MMR3-LABEL: f1:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS32R6-LABEL: f1:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
; MIPS32R6-NEXT: # <MCOperand Reg:321>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MMR6-LABEL: f1:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MMR6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu_MM
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS3-LABEL: f1:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS3-NEXT: # <MCOperand Reg:301>>
; MIPS3-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
; MIPS3-NEXT: # <MCOperand Reg:321>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS64-LABEL: f1:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS64-NEXT: # <MCOperand Reg:301>>
; MIPS64-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
; MIPS64-NEXT: # <MCOperand Reg:321>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS64R6-LABEL: f1:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: lbu $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LBu
; MIPS64R6-NEXT: # <MCOperand Reg:321>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>>
entry:
%0 = load i8, i8 * @a
ret i8 %0
}
define i32 @f2() {
; MIPS32-LABEL: f2:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
; MIPS32-NEXT: # <MCOperand Reg:321>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MMR3-LABEL: f2:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS32R6-LABEL: f2:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
; MIPS32R6-NEXT: # <MCOperand Reg:321>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MMR6-LABEL: f2:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MMR6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB_MM
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS3-LABEL: f2:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS3-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS3-NEXT: # <MCOperand Reg:301>>
; MIPS3-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
; MIPS3-NEXT: # <MCOperand Reg:321>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS64-LABEL: f2:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS64-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS64-NEXT: # <MCOperand Reg:301>>
; MIPS64-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
; MIPS64-NEXT: # <MCOperand Reg:321>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS64R6-LABEL: f2:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: lb $2, %lo(a)($1) # <MCInst #{{[0-9]+}} LB
; MIPS64R6-NEXT: # <MCOperand Reg:321>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>>
entry:
%0 = load i8, i8 * @a
%1 = sext i8 %0 to i32
ret i32 %1
}
define i16 @f3() {
; MIPS32-LABEL: f3:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
; MIPS32-NEXT: # <MCOperand Reg:321>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MMR3-LABEL: f3:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS32R6-LABEL: f3:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
; MIPS32R6-NEXT: # <MCOperand Reg:321>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MMR6-LABEL: f3:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MMR6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu_MM
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS3-LABEL: f3:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS3-NEXT: # <MCOperand Reg:301>>
; MIPS3-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
; MIPS3-NEXT: # <MCOperand Reg:321>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS64-LABEL: f3:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS64-NEXT: # <MCOperand Reg:301>>
; MIPS64-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
; MIPS64-NEXT: # <MCOperand Reg:321>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS64R6-LABEL: f3:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: lhu $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LHu
; MIPS64R6-NEXT: # <MCOperand Reg:321>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>>
entry:
%0 = load i16, i16 * @b
ret i16 %0
}
define i32 @f4() {
; MIPS32-LABEL: f4:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
; MIPS32-NEXT: # <MCOperand Reg:321>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MMR3-LABEL: f4:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS32R6-LABEL: f4:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
; MIPS32R6-NEXT: # <MCOperand Reg:321>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MMR6-LABEL: f4:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MMR6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH_MM
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS3-LABEL: f4:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS3-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS3-NEXT: # <MCOperand Reg:301>>
; MIPS3-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
; MIPS3-NEXT: # <MCOperand Reg:321>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS64-LABEL: f4:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS64-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS64-NEXT: # <MCOperand Reg:301>>
; MIPS64-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
; MIPS64-NEXT: # <MCOperand Reg:321>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS64R6-LABEL: f4:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: lh $2, %lo(b)($1) # <MCInst #{{[0-9]+}} LH
; MIPS64R6-NEXT: # <MCOperand Reg:321>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>>
entry:
%0 = load i16, i16 * @b
%1 = sext i16 %0 to i32
ret i32 %1
}
define i32 @f5() {
; MIPS32-LABEL: f5:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS32-NEXT: # <MCOperand Reg:321>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MMR3-LABEL: f5:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS32R6-LABEL: f5:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS32R6-NEXT: # <MCOperand Reg:321>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MMR6-LABEL: f5:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS3-LABEL: f5:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS3-NEXT: # <MCOperand Reg:301>>
; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS3-NEXT: # <MCOperand Reg:321>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS64-LABEL: f5:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS64-NEXT: # <MCOperand Reg:301>>
; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS64-NEXT: # <MCOperand Reg:321>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS64R6-LABEL: f5:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS64R6-NEXT: # <MCOperand Reg:321>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
entry:
%0 = load i32, i32 * @c
ret i32 %0
}
define i64 @f6() {
; MIPS32-LABEL: f6:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS32-NEXT: # <MCOperand Reg:322>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
; MIPS32-NEXT: # <MCOperand Reg:321>
; MIPS32-NEXT: # <MCOperand Reg:21>
; MIPS32-NEXT: # <MCOperand Imm:0>>
;
; MMR3-LABEL: f6:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR3-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Imm:0>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
; MMR3-NEXT: # <MCOperand Reg:322>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS32R6-LABEL: f6:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS32R6-NEXT: # <MCOperand Reg:322>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: addiu $2, $zero, 0 # <MCInst #{{[0-9]+}} ADDiu
; MIPS32R6-NEXT: # <MCOperand Reg:321>
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Imm:0>>
;
; MMR6-LABEL: f6:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
; MMR6-NEXT: # <MCOperand Reg:322>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
; MMR6-NEXT: li16 $2, 0 # <MCInst #{{[0-9]+}} LI16_MM
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Imm:0>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS3-LABEL: f6:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS3-NEXT: # <MCOperand Reg:301>>
; MIPS3-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
; MIPS3-NEXT: # <MCOperand Reg:416>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS64-LABEL: f6:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS64-NEXT: # <MCOperand Reg:301>>
; MIPS64-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
; MIPS64-NEXT: # <MCOperand Reg:416>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS64R6-LABEL: f6:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: lwu $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LWu
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
entry:
%0 = load i32, i32 * @c
%1 = zext i32 %0 to i64
ret i64 %1
}
define i64 @f7() {
; MIPS32-LABEL: f7:
; MIPS32: # %bb.0: # %entry
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS32-NEXT: # <MCOperand Reg:322>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
; MIPS32-NEXT: # <MCOperand Reg:321>
; MIPS32-NEXT: # <MCOperand Reg:322>
; MIPS32-NEXT: # <MCOperand Imm:31>>
;
; MMR3-LABEL: f7:
; MMR3: # %bb.0: # %entry
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR3-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
; MMR3-NEXT: # <MCOperand Reg:322>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Reg:322>
; MMR3-NEXT: # <MCOperand Imm:31>>
;
; MIPS32R6-LABEL: f7:
; MIPS32R6: # %bb.0: # %entry
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32R6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW
; MIPS32R6-NEXT: # <MCOperand Reg:322>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA
; MIPS32R6-NEXT: # <MCOperand Reg:321>
; MIPS32R6-NEXT: # <MCOperand Reg:322>
; MIPS32R6-NEXT: # <MCOperand Imm:31>>
;
; MMR6-LABEL: f7:
; MMR6: # %bb.0: # %entry
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR6-NEXT: lw $3, %lo(c)($1) # <MCInst #{{[0-9]+}} LW_MM
; MMR6-NEXT: # <MCOperand Reg:322>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
; MMR6-NEXT: sra $2, $3, 31 # <MCInst #{{[0-9]+}} SRA_MM
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:322>
; MMR6-NEXT: # <MCOperand Imm:31>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS3-LABEL: f7:
; MIPS3: # %bb.0: # %entry
; MIPS3-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS3-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS3-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Imm:16>>
; MIPS3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS3-NEXT: # <MCOperand Reg:301>>
; MIPS3-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
; MIPS3-NEXT: # <MCOperand Reg:416>
; MIPS3-NEXT: # <MCOperand Reg:30>
; MIPS3-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS64-LABEL: f7:
; MIPS64: # %bb.0: # %entry
; MIPS64-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS64-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS64-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Imm:16>>
; MIPS64-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS64-NEXT: # <MCOperand Reg:301>>
; MIPS64-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
; MIPS64-NEXT: # <MCOperand Reg:416>
; MIPS64-NEXT: # <MCOperand Reg:30>
; MIPS64-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS64R6-LABEL: f7:
; MIPS64R6: # %bb.0: # %entry
; MIPS64R6-NEXT: lui $1, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: lw $2, %lo(c)($1) # <MCInst #{{[0-9]+}} LW64
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
entry:
%0 = load i32, i32 * @c
%1 = sext i32 %0 to i64
ret i64 %1
}

test/CodeGen/Mips/llvm-ir/store.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32
; RUN: llc -mtriple=mips-mti-linux-gnu -mcpu=mips32r2 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR3
; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS32R6
; RUN: llc -mtriple=mips-img-linux-gnu -mcpu=mips32r6 -mattr=+micromips < %s -asm-show-inst | FileCheck %s --check-prefix=MMR6
; RUN: llc -mtriple=mips64-mti-linux-gnu -mcpu=mips4 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS4
; RUN: llc -mtriple=mips64-img-linux-gnu -mcpu=mips64r6 < %s -asm-show-inst | FileCheck %s --check-prefix=MIPS64R6
; Test subword and word stores.
@a = common global i8 0, align 4
@b = common global i16 0, align 4
@c = common global i32 0, align 4
@d = common global i64 0, align 8
define void @f1(i8 %a) {
; MIPS32-LABEL: f1:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
; MIPS32-NEXT: # <MCOperand Reg:22>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MMR3-LABEL: f1:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(a))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
; MMR3-NEXT: # <MCOperand Reg:22>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS32R6-LABEL: f1:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB
; MIPS32R6-NEXT: # <MCOperand Reg:22>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MMR6-LABEL: f1:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(a) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MMR6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB_MM
; MMR6-NEXT: # <MCOperand Reg:22>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(a))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS4-LABEL: f1:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS4-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS4-NEXT: # <MCOperand Reg:301>>
; MIPS4-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
; MIPS4-NEXT: # <MCOperand Reg:356>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%lo(a))>>
;
; MIPS64R6-LABEL: f1:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(a) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(a))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(a))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(a) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(a))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: sb $4, %lo(a)($1) # <MCInst #{{[0-9]+}} SB64
; MIPS64R6-NEXT: # <MCOperand Reg:356>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(a))>>
store i8 %a, i8 * @a
ret void
}
define void @f2(i16 %a) {
; MIPS32-LABEL: f2:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
; MIPS32-NEXT: # <MCOperand Reg:22>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MMR3-LABEL: f2:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(b))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
; MMR3-NEXT: # <MCOperand Reg:22>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS32R6-LABEL: f2:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH
; MIPS32R6-NEXT: # <MCOperand Reg:22>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MMR6-LABEL: f2:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(b) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MMR6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH_MM
; MMR6-NEXT: # <MCOperand Reg:22>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(b))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS4-LABEL: f2:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS4-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS4-NEXT: # <MCOperand Reg:301>>
; MIPS4-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
; MIPS4-NEXT: # <MCOperand Reg:356>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%lo(b))>>
;
; MIPS64R6-LABEL: f2:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(b) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(b))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(b))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(b) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(b))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: sh $4, %lo(b)($1) # <MCInst #{{[0-9]+}} SH64
; MIPS64R6-NEXT: # <MCOperand Reg:356>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(b))>>
store i16 %a, i16 * @b
ret void
}
define void @f3(i32 %a) {
; MIPS32-LABEL: f3:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
; MIPS32-NEXT: # <MCOperand Reg:22>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MMR3-LABEL: f3:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR3-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
; MMR3-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
; MMR3-NEXT: # <MCOperand Reg:22>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS32R6-LABEL: f3:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW
; MIPS32R6-NEXT: # <MCOperand Reg:22>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MMR6-LABEL: f3:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(c) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MMR6-NEXT: sw $4, %lo(c)($1) # <MCInst #{{[0-9]+}} SW_MM
; MMR6-NEXT: # <MCOperand Reg:22>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(c))>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS4-LABEL: f3:
; MIPS4: # %bb.0:
; MIPS4-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
; MIPS4-NEXT: # <MCOperand Reg:1>
; MIPS4-NEXT: # <MCOperand Reg:22>
; MIPS4-NEXT: # <MCOperand Imm:0>>
; MIPS4-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS4-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS4-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS4-NEXT: # <MCOperand Reg:301>>
; MIPS4-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
; MIPS4-NEXT: # <MCOperand Reg:1>
; MIPS4-NEXT: # <MCOperand Reg:416>
; MIPS4-NEXT: # <MCOperand Expr:(%lo(c))>>
;
; MIPS64R6-LABEL: f3:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: sll $1, $4, 0 # <MCInst #{{[0-9]+}} SLL
; MIPS64R6-NEXT: # <MCOperand Reg:1>
; MIPS64R6-NEXT: # <MCOperand Reg:22>
; MIPS64R6-NEXT: # <MCOperand Imm:0>>
; MIPS64R6-NEXT: lui $2, %highest(c) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(c))>>
; MIPS64R6-NEXT: daddiu $2, $2, %higher(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(c))>>
; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $2, $2, %hi(c) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(c))>>
; MIPS64R6-NEXT: dsll $2, $2, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: sw $1, %lo(c)($2) # <MCInst #{{[0-9]+}} SW
; MIPS64R6-NEXT: # <MCOperand Reg:1>
; MIPS64R6-NEXT: # <MCOperand Reg:416>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(c))>>
store i32 %a, i32 * @c
ret void
}
define void @f4(i64 %a) {
; MIPS32-LABEL: f4:
; MIPS32: # %bb.0:
; MIPS32-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%hi(d))>>
; MIPS32-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
; MIPS32-NEXT: # <MCOperand Reg:22>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>>
; MIPS32-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Expr:(%lo(d))>>
; MIPS32-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS32-NEXT: # <MCOperand Reg:19>>
; MIPS32-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
; MIPS32-NEXT: # <MCOperand Reg:23>
; MIPS32-NEXT: # <MCOperand Reg:1>
; MIPS32-NEXT: # <MCOperand Imm:4>>
;
; MMR3-LABEL: f4:
; MMR3: # %bb.0:
; MMR3-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%hi(d))>>
; MMR3-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
; MMR3-NEXT: # <MCOperand Reg:22>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>>
; MMR3-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Reg:1>
; MMR3-NEXT: # <MCOperand Expr:(%lo(d))>>
; MMR3-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
; MMR3-NEXT: # <MCOperand Reg:23>
; MMR3-NEXT: # <MCOperand Reg:321>
; MMR3-NEXT: # <MCOperand Imm:4>>
; MMR3-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR3-NEXT: # <MCOperand Reg:19>>
;
; MIPS32R6-LABEL: f4:
; MIPS32R6: # %bb.0:
; MIPS32R6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%hi(d))>>
; MIPS32R6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW
; MIPS32R6-NEXT: # <MCOperand Reg:22>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>>
; MIPS32R6-NEXT: addiu $1, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Expr:(%lo(d))>>
; MIPS32R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR
; MIPS32R6-NEXT: # <MCOperand Reg:21>
; MIPS32R6-NEXT: # <MCOperand Reg:19>>
; MIPS32R6-NEXT: sw $5, 4($1) # <MCInst #{{[0-9]+}} SW
; MIPS32R6-NEXT: # <MCOperand Reg:23>
; MIPS32R6-NEXT: # <MCOperand Reg:1>
; MIPS32R6-NEXT: # <MCOperand Imm:4>>
;
; MMR6-LABEL: f4:
; MMR6: # %bb.0:
; MMR6-NEXT: lui $1, %hi(d) # <MCInst #{{[0-9]+}} LUi
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%hi(d))>>
; MMR6-NEXT: sw $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SW_MM
; MMR6-NEXT: # <MCOperand Reg:22>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>>
; MMR6-NEXT: addiu $2, $1, %lo(d) # <MCInst #{{[0-9]+}} ADDiu
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Reg:1>
; MMR6-NEXT: # <MCOperand Expr:(%lo(d))>>
; MMR6-NEXT: sw16 $5, 4($2) # <MCInst #{{[0-9]+}} SW16_MM
; MMR6-NEXT: # <MCOperand Reg:23>
; MMR6-NEXT: # <MCOperand Reg:321>
; MMR6-NEXT: # <MCOperand Imm:4>>
; MMR6-NEXT: jrc $ra # <MCInst #{{[0-9]+}} JRC16_MM
; MMR6-NEXT: # <MCOperand Reg:19>>
;
; MIPS4-LABEL: f4:
; MIPS4: # %bb.0:
; MIPS4-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%highest(d))>>
; MIPS4-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%higher(d))>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%hi(d))>>
; MIPS4-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Imm:16>>
; MIPS4-NEXT: jr $ra # <MCInst #{{[0-9]+}} JR
; MIPS4-NEXT: # <MCOperand Reg:301>>
; MIPS4-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
; MIPS4-NEXT: # <MCOperand Reg:356>
; MIPS4-NEXT: # <MCOperand Reg:30>
; MIPS4-NEXT: # <MCOperand Expr:(%lo(d))>>
;
; MIPS64R6-LABEL: f4:
; MIPS64R6: # %bb.0:
; MIPS64R6-NEXT: lui $1, %highest(d) # <MCInst #{{[0-9]+}} LUi64
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%highest(d))>>
; MIPS64R6-NEXT: daddiu $1, $1, %higher(d) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%higher(d))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: daddiu $1, $1, %hi(d) # <MCInst #{{[0-9]+}} DADDiu
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%hi(d))>>
; MIPS64R6-NEXT: dsll $1, $1, 16 # <MCInst #{{[0-9]+}} DSLL
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Imm:16>>
; MIPS64R6-NEXT: jr $ra # <MCInst #{{[0-9]+}} JALR64
; MIPS64R6-NEXT: # <MCOperand Reg:355>
; MIPS64R6-NEXT: # <MCOperand Reg:301>>
; MIPS64R6-NEXT: sd $4, %lo(d)($1) # <MCInst #{{[0-9]+}} SD
; MIPS64R6-NEXT: # <MCOperand Reg:356>
; MIPS64R6-NEXT: # <MCOperand Reg:30>
; MIPS64R6-NEXT: # <MCOperand Expr:(%lo(d))>>
store i64 %a, i64 * @d
ret void
}