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AMDGPU: Fix SDWA peephole for V_AND_B32
ClosedPublic

Authored by nhaehnle on Apr 20 2018, 8:56 AM.

Reviewers

arsenm
rampitec

Commits

Summary

Found by inspection. We care about the operand that *doesn't*
contain the immediate.

I believe this is currently not hit because we fold 0xff / 0xffff
immediates only later.

Change-Id: Ic3cf8538bc7da5eff3200d96eccf9d339e6345a7

Repository

rL LLVM

Build Status

Buildable 17282
Build 17282: arc lint + arc unit

LGTM

This revision is now accepted and ready to land.Apr 20 2018, 9:21 AM

This revision was automatically updated to reflect the committed changes.

Path

Size

lib/

Target/

AMDGPU/

2 lines

Show First 20 Lines • Show All 693 Lines • ▼ Show 20 Lines	if (!Imm) {
ValSrc = Src0;		ValSrc = Src0;
}		}

if (!Imm \|\| (Imm != 0x0000ffff && Imm != 0x000000ff))		if (!Imm \|\| (Imm != 0x0000ffff && Imm != 0x000000ff))
break;		break;

MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);		MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);

if (TRI->isPhysicalRegister(Src1->getReg()) \|\|		if (TRI->isPhysicalRegister(ValSrc->getReg()) \|\|
TRI->isPhysicalRegister(Dst->getReg()))		TRI->isPhysicalRegister(Dst->getReg()))
break;		break;

return make_unique<SDWASrcOperand>(		return make_unique<SDWASrcOperand>(
ValSrc, Dst, *Imm == 0x0000ffff ? WORD_0 : BYTE_0);		ValSrc, Dst, *Imm == 0x0000ffff ? WORD_0 : BYTE_0);
}		}

case AMDGPU::V_OR_B32_e32:		case AMDGPU::V_OR_B32_e32:
▲ Show 20 Lines • Show All 446 Lines • Show Last 20 Lines