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Differential D45790

[AMDGPU] Use packed literals with zero either lower or hi part
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Authored by rampitec on Apr 18 2018, 5:14 PM.

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Reviewers
kzhuravl
arsenm
Commits
rG160f85794de3: [AMDGPU] Use packed literals with zero either lower or hi part
rL330365: [AMDGPU] Use packed literals with zero either lower or hi part

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Event Timeline

rampitec created this revision.Apr 18 2018, 5:14 PM
Herald added subscribers: t-tye, tpr, dstuttard and 3 others. · View Herald TranscriptApr 18 2018, 5:14 PM
kzhuravl accepted this revision.Apr 19 2018, 1:54 PM

LGTM

This revision is now accepted and ready to land.Apr 19 2018, 1:54 PM
Closed by commit rL330365: [AMDGPU] Use packed literals with zero either lower or hi part (authored by rampitec). · Explain WhyApr 19 2018, 2:20 PM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
14 lines
9 lines
test/
CodeGen/
AMDGPU/
3 lines
2 lines
95 lines
3 lines

Diff 143028

lib/Target/AMDGPU/SIFoldOperands.cpp

Show First 20 Lines • Show All 150 Lines • ▼ Show 20 Lines
static bool updateOperand(FoldCandidate &Fold, static bool updateOperand(FoldCandidate &Fold,
const TargetRegisterInfo &TRI) { const TargetRegisterInfo &TRI) {
MachineInstr *MI = Fold.UseMI; MachineInstr *MI = Fold.UseMI;
MachineOperand &Old = MI->getOperand(Fold.UseOpNo); MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
assert(Old.isReg()); assert(Old.isReg());
if (Fold.isImm()) { if (Fold.isImm()) {
if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked) { if (MI->getDesc().TSFlags & SIInstrFlags::IsPacked) {
// Set op_sel_hi on this operand or bail out if op_sel is already set. // Set op_sel/op_sel_hi on this operand or bail out if op_sel is
// already set.
unsigned Opcode = MI->getOpcode(); unsigned Opcode = MI->getOpcode();
int OpNo = MI->getOperandNo(&Old); int OpNo = MI->getOperandNo(&Old);
int ModIdx = -1; int ModIdx = -1;
if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0)) if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0))
ModIdx = AMDGPU::OpName::src0_modifiers; ModIdx = AMDGPU::OpName::src0_modifiers;
else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1)) else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1))
ModIdx = AMDGPU::OpName::src1_modifiers; ModIdx = AMDGPU::OpName::src1_modifiers;
else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2)) else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2))
ModIdx = AMDGPU::OpName::src2_modifiers; ModIdx = AMDGPU::OpName::src2_modifiers;
assert(ModIdx != -1); assert(ModIdx != -1);
ModIdx = AMDGPU::getNamedOperandIdx(Opcode, ModIdx); ModIdx = AMDGPU::getNamedOperandIdx(Opcode, ModIdx);
MachineOperand &Mod = MI->getOperand(ModIdx); MachineOperand &Mod = MI->getOperand(ModIdx);
unsigned Val = Mod.getImm(); unsigned Val = Mod.getImm();
if ((Val & SISrcMods::OP_SEL_0) || !(Val & SISrcMods::OP_SEL_1)) if ((Val & SISrcMods::OP_SEL_0) || !(Val & SISrcMods::OP_SEL_1))
return false; return false;
// If upper part is all zero we do not need op_sel_hi.
if (!isUInt<16>(Fold.ImmToFold)) {
if (!(Fold.ImmToFold & 0xffff)) {
Mod.setImm(Mod.getImm() | SISrcMods::OP_SEL_0);
Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1); Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
Old.ChangeToImmediate(Fold.ImmToFold >> 16);
return true;
}
Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
}
} }
Old.ChangeToImmediate(Fold.ImmToFold); Old.ChangeToImmediate(Fold.ImmToFold);
return true; return true;
} }
if (Fold.isFI()) { if (Fold.isFI()) {
Old.ChangeToFrameIndex(Fold.FrameIndexToFold); Old.ChangeToFrameIndex(Fold.FrameIndexToFold);
return true; return true;
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lib/Target/AMDGPU/SIInstrInfo.cpp

Show First 20 Lines • Show All 2,333 Lines • ▼ Show 20 Lines if (isInt<16>(Imm) || isUInt<16>(Imm)) {
return ST.has16BitInsts() && return ST.has16BitInsts() &&
AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm()); AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm());
} }
return false; return false;
} }
case AMDGPU::OPERAND_REG_INLINE_C_V2INT16: case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: { case AMDGPU::OPERAND_REG_INLINE_C_V2FP16: {
if (isUInt<16>(Imm)) {
int16_t Trunc = static_cast<int16_t>(Imm);
return ST.has16BitInsts() &&
AMDGPU::isInlinableLiteral16(Trunc, ST.hasInv2PiInlineImm());
}
if (!(Imm & 0xffff)) {
return ST.has16BitInsts() &&
AMDGPU::isInlinableLiteral16(Imm >> 16, ST.hasInv2PiInlineImm());
}
uint32_t Trunc = static_cast<uint32_t>(Imm); uint32_t Trunc = static_cast<uint32_t>(Imm);
return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm()); return AMDGPU::isInlinableLiteralV216(Trunc, ST.hasInv2PiInlineImm());
} }
default: default:
llvm_unreachable("invalid bitwidth"); llvm_unreachable("invalid bitwidth");
} }
} }
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test/CodeGen/AMDGPU/add.v2i16.ll

Show First 20 Lines • Show All 109 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_test_add_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = add <2 x i16> %a, <i16 -1, i16 -1> %add = add <2 x i16> %a, <i16 -1, i16 -1>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_test_add_v2i16_inline_lo_zero_hi: ; GCN-LABEL: {{^}}v_test_add_v2i16_inline_lo_zero_hi:
; GFX9: s_mov_b32 [[K:s[0-9]+]], 32{{$}} ; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}}
; GFX9: v_pk_add_u16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]{{$}}
; VI-NOT: v_add_u16 ; VI-NOT: v_add_u16
; VI: v_add_u16_e32 v{{[0-9]+}}, 32, v{{[0-9]+}} ; VI: v_add_u16_e32 v{{[0-9]+}}, 32, v{{[0-9]+}}
; VI-NOT: v_add_u16 ; VI-NOT: v_add_u16
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_e32 ; VI: v_or_b32_e32
define amdgpu_kernel void @v_test_add_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_add_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
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test/CodeGen/AMDGPU/immv216.ll

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; GCN: buffer_store_dword [[REG]] ; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @store_literal_imm_v2f16(<2 x half> addrspace(1)* %out) #0 { define amdgpu_kernel void @store_literal_imm_v2f16(<2 x half> addrspace(1)* %out) #0 {
store <2 x half> <half 4096.0, half 4096.0>, <2 x half> addrspace(1)* %out store <2 x half> <half 4096.0, half 4096.0>, <2 x half> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}add_inline_imm_0.0_v2f16: ; GCN-LABEL: {{^}}add_inline_imm_0.0_v2f16:
; GFX9: s_load_dword [[VAL:s[0-9]+]] ; GFX9: s_load_dword [[VAL:s[0-9]+]]
; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0 op_sel_hi:[1,0]{{$}} ; GFX9: v_pk_add_f16 [[REG:v[0-9]+]], [[VAL]], 0{{$}}
; GFX9: buffer_store_dword [[REG]] ; GFX9: buffer_store_dword [[REG]]
; VI: buffer_load_ushort [[VAL0:v[0-9]+]] ; VI: buffer_load_ushort [[VAL0:v[0-9]+]]
; VI: buffer_load_ushort [[VAL1:v[0-9]+]] ; VI: buffer_load_ushort [[VAL1:v[0-9]+]]
; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0, [[VAL0]] ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0, [[VAL0]]
; VI-DAG: v_mov_b32_e32 [[CONST0:v[0-9]+]], 0 ; VI-DAG: v_mov_b32_e32 [[CONST0:v[0-9]+]], 0
; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[VAL1]], [[CONST0]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD ; VI-DAG: v_add_f16_sdwa v{{[0-9]+}}, [[VAL1]], [[CONST0]] dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; VI: v_or_b32 ; VI: v_or_b32
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test/CodeGen/AMDGPU/pk_max_f16_literal.ll

  • This file was added.
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_1:
; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}
define amdgpu_kernel void @test_pk_max_f16_literal_0_1(<2 x half> addrspace(1)* nocapture %arg) {
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64
%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH3C00>)
store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
ret void
}
; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_0:
; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0{{$}}
define amdgpu_kernel void @test_pk_max_f16_literal_1_0(<2 x half> addrspace(1)* nocapture %arg) {
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64
%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH0000>)
store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
ret void
}
; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_1:
; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel_hi:[1,0]{{$}}
define amdgpu_kernel void @test_pk_max_f16_literal_1_1(<2 x half> addrspace(1)* nocapture %arg) {
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64
%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH3C00>)
store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
ret void
}
; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_m1:
; GFX9: v_pk_max_f16 v{{[0-9]+}}, -1.0, v{{[0-9]+}} op_sel:[1,0] op_sel_hi:[0,1]{{$}}
define amdgpu_kernel void @test_pk_max_f16_literal_0_m1(<2 x half> addrspace(1)* nocapture %arg) {
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64
%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xHBC00>)
store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
ret void
}
; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_0:
; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0{{$}}
define amdgpu_kernel void @test_pk_max_f16_literal_m1_0(<2 x half> addrspace(1)* nocapture %arg) {
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64
%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xH0000>)
store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
ret void
}
; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_m1:
; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel_hi:[1,0]{{$}}
define amdgpu_kernel void @test_pk_max_f16_literal_m1_m1(<2 x half> addrspace(1)* nocapture %arg) {
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64
%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xHBC00>)
store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
ret void
}
; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_0:
; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 0{{$}}
define amdgpu_kernel void @test_pk_max_f16_literal_0_0(<2 x half> addrspace(1)* nocapture %arg) {
bb:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64
%tmp2 = getelementptr inbounds <2 x half>, <2 x half> addrspace(1)* %arg, i64 %tmp1
%tmp3 = load <2 x half>, <2 x half> addrspace(1)* %tmp2, align 4
%tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH0000>)
store <2 x half> %tmp4, <2 x half> addrspace(1)* %tmp2, align 4
ret void
}
declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)
declare i32 @llvm.amdgcn.workitem.id.x()

test/CodeGen/AMDGPU/sub.v2i16.ll

Show First 20 Lines • Show All 106 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
%gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid %gep.in0 = getelementptr inbounds <2 x i16>, <2 x i16> addrspace(1)* %in0, i32 %tid
%a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0 %a = load volatile <2 x i16>, <2 x i16> addrspace(1)* %gep.in0
%add = sub <2 x i16> %a, <i16 -1, i16 -1> %add = sub <2 x i16> %a, <i16 -1, i16 -1>
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_lo_zero_hi: ; GCN-LABEL: {{^}}v_test_sub_v2i16_inline_lo_zero_hi:
; GFX9: s_mov_b32 [[K:s[0-9]+]], 32{{$}} ; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, 32{{$}}
; GFX9: v_pk_sub_i16 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
; VI-NOT: v_subrev_i16 ; VI-NOT: v_subrev_i16
; VI: v_add_u16_e32 v{{[0-9]+}}, 0xffffffe0, v{{[0-9]+}} ; VI: v_add_u16_e32 v{{[0-9]+}}, 0xffffffe0, v{{[0-9]+}}
; VI-NOT: v_subrev_i16 ; VI-NOT: v_subrev_i16
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_e32 ; VI: v_or_b32_e32
define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 { define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %in0) #1 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
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