[NEON] Support intrinsic for scalar and vector versions of the VRINTN instruction

[kosarev]

Summary

We need it to implement the vrndns_f32() NEON intrinsic.

[SjoerdMeijer]

Look like we need to add some tests too?

[efriedma]

Can you use llvm.rint.f32, instead of adding a new intrinsic?

[kosarev]

A test case added.

[kosarev]

Eli, the patch doesn't add new intrinsics, just allows scalar arguments for an existing one. Switching from existing ARM-specific intrinsics to some more generic ones seems to be out of scope of this change.

[efriedma]

Okay. Then LGTM.

llvm/trunk/include/llvm/IR/IntrinsicsARM.td

 class Neon_3Arg_Intrinsic
   : Intrinsic<[llvm_anyvector_ty],
               [LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
               [IntrNoMem]>;
 class Neon_3Arg_Long_Intrinsic
   : Intrinsic<[llvm_anyvector_ty],
               [LLVMMatchType<0>, LLVMTruncatedType<0>, LLVMTruncatedType<0>],
               [IntrNoMem]>;
+
+class Neon_1FloatArg_Intrinsic
+  : Intrinsic<[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
+
 class Neon_CvtFxToFP_Intrinsic
   : Intrinsic<[llvm_anyfloat_ty], [llvm_anyint_ty, llvm_i32_ty], [IntrNoMem]>;
 class Neon_CvtFPToFx_Intrinsic
   : Intrinsic<[llvm_anyint_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]>;
 class Neon_CvtFPtoInt_1Arg_Intrinsic
   : Intrinsic<[llvm_anyvector_ty], [llvm_anyvector_ty], [IntrNoMem]>;
 
 class Neon_Compare_Intrinsic

 // Some elements of the destination vector may not be updated, so the original
 // value of that vector is passed as the first argument.  The next 1-4
 // arguments after that are the table.
 def int_arm_neon_vtbx1 : Neon_Tbl3Arg_Intrinsic;
 def int_arm_neon_vtbx2 : Neon_Tbl4Arg_Intrinsic;
 def int_arm_neon_vtbx3 : Neon_Tbl5Arg_Intrinsic;
 def int_arm_neon_vtbx4 : Neon_Tbl6Arg_Intrinsic;
 
-// Vector Rounding
-def int_arm_neon_vrintn : Neon_1Arg_Intrinsic;
+// Vector and Scalar Rounding.
+def int_arm_neon_vrintn : Neon_1FloatArg_Intrinsic;
 def int_arm_neon_vrintx : Neon_1Arg_Intrinsic;
 def int_arm_neon_vrinta : Neon_1Arg_Intrinsic;
 def int_arm_neon_vrintz : Neon_1Arg_Intrinsic;
 def int_arm_neon_vrintm : Neon_1Arg_Intrinsic;
 def int_arm_neon_vrintp : Neon_1Arg_Intrinsic;
 
 // De-interleaving vector loads from N-element structures.
 // Source operands are the address and alignment.

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

def : InstAlias<!strconcat("vrint", opc, ".f32.f32\t$Sd, $Sm"),
                   (!cast<Instruction>(NAME#"S") SPR:$Sd, SPR:$Sm), 0>,
         Requires<[HasFPARMv8]>;
   def : InstAlias<!strconcat("vrint", opc, ".f64.f64\t$Dd, $Dm"),
                   (!cast<Instruction>(NAME#"D") DPR:$Dd, DPR:$Dm), 0>,
         Requires<[HasFPARMv8,HasDPVFP]>;
 }
 
 defm VRINTA : vrint_inst_anpm<"a", 0b00, fround>;
-defm VRINTN : vrint_inst_anpm<"n", 0b01>;
+defm VRINTN : vrint_inst_anpm<"n", 0b01, int_arm_neon_vrintn>;
 defm VRINTP : vrint_inst_anpm<"p", 0b10, fceil>;
 defm VRINTM : vrint_inst_anpm<"m", 0b11, ffloor>;
 
 def VSQRTD : ADuI<0b11101, 0b11, 0b0001, 0b11, 0,
                   (outs DPR:$Dd), (ins DPR:$Dm),
                   IIC_fpSQRT64, "vsqrt", ".f64\t$Dd, $Dm",
                   [(set DPR:$Dd, (fsqrt (f64 DPR:$Dm)))]>,
              Sched<[WriteFPSQRT64]>;

llvm/trunk/test/CodeGen/ARM/vrint.ll

+; RUN: llc -mtriple=armv8 -mattr=+neon %s -o - | FileCheck %s
+
+declare float @llvm.arm.neon.vrintn.f32(float) nounwind readnone
+
+; CHECK-LABEL: vrintn_f32:
+; CHECK: vrintn.f32
+define float @vrintn_f32(float* %A) nounwind {
+  %tmp1 = load float, float* %A
+  %tmp2 = call float @llvm.arm.neon.vrintn.f32(float %tmp1)
+  ret float %tmp2
+}