Attempt to fix Mips breakages.

[manojgupta]

Summary

Replace ArrayRefs by actual std::array objects so that there are
no dangling references.

[manojgupta]

Going to check it in to see if it fixes the builder issues.

lib/Target/Mips/MipsFastISel.cpp

 #include "llvm/Support/Casting.h"
 #include "llvm/Support/Compiler.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/ErrorHandling.h"
 #include "llvm/Support/MachineValueType.h"
 #include "llvm/Support/MathExtras.h"
 #include "llvm/Support/raw_ostream.h"
 #include <algorithm>
+#include <array>
 #include <cassert>
 #include <cstdint>
 
 #define DEBUG_TYPE "mips-fastisel"
 
 using namespace llvm;
 
 namespace {
bool MipsFastISel::fastLowerArguments() {
   }
 
   CallingConv::ID CC = F->getCallingConv();
   if (CC != CallingConv::C) {
     DEBUG(dbgs() << ".. gave up (calling convention is not C)\n");
     return false;
   }
 
-  const ArrayRef<MCPhysReg> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
-                                            Mips::A3};
-  const ArrayRef<MCPhysReg> FGR32ArgRegs = {Mips::F12, Mips::F14};
-  const ArrayRef<MCPhysReg> AFGR64ArgRegs = {Mips::D6, Mips::D7};
-  ArrayRef<MCPhysReg>::iterator NextGPR32 = GPR32ArgRegs.begin();
-  ArrayRef<MCPhysReg>::iterator NextFGR32 = FGR32ArgRegs.begin();
-  ArrayRef<MCPhysReg>::iterator NextAFGR64 = AFGR64ArgRegs.begin();
+  std::array<MCPhysReg, 4> GPR32ArgRegs = {Mips::A0, Mips::A1, Mips::A2,
+  std::array<MCPhysReg, 2> FGR32ArgRegs = {Mips::F12, Mips::F14};
+  std::array<MCPhysReg, 2> AFGR64ArgRegs = {Mips::D6, Mips::D7};
+  auto NextGPR32 = GPR32ArgRegs.begin();
+  auto NextFGR32 = FGR32ArgRegs.begin();
+  auto NextAFGR64 = AFGR64ArgRegs.begin();
 
   struct AllocatedReg {
     const TargetRegisterClass *RC;
     unsigned Reg;
     AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
         : RC(RC), Reg(Reg) {}
   };