[X86] Add WriteFMOVMSK/WriteVecMOVMSK/WriteMMXMOVMSK scheduler classes

[RKSimon]

Summary

Currently MOVMSK instructions use the WriteVecLogic class, which is a very poor choice given that MOVMSK involves a SSE->GPR transfer.

This introduces WriteFMOVMSK/WriteVecMOVMSK/WriteMMXMOVMSK scheduler classes instead.

SLM - Used Agner's values.

ZN - VPMOVMSKB/VPMOVMSKBY had some weird values that have been cleaned up based on advice from @GGanesh.

[GGanesh]

lib/Target/X86/X86ScheduleZnver1.td

222 ↗

(On Diff #139909)

The original version is wrong for the obvious reasons!
The Ymm version takes two u-ops and has two cycle latency.

[courbet]

lib/Target/X86/X86SchedBroadwell.td

300 ↗

(On Diff #139909)

I'm measuring a latency of 1 for MMX_PMOVMSKBrr, removing the override would break this.

[RKSimon]

Thanks @GGanesh

[RKSimon]

lib/Target/X86/X86SchedBroadwell.td

300 ↗

(On Diff #139909)

Should I put the override back for Haswell/SandyBridge?

[courbet]

lib/Target/X86/X86SchedBroadwell.td

300 ↗

(On Diff #139909)

Yes, please put it back for HW/BD. As for SNB, it does not have an override for MMX_PMOVMSKBrr right now, I'm going to add one in a separate commit.

To summarize my measurements:
(I don't have an SKX at hand, but I expect it to be similar to SKL)

	SNB	BDW/HSW	SKL
MMX_PMOVMSKBrr	1	1	3
(V)PMOVMSKBrr	2	3	3

[courbet]

lib/Target/X86/X86SchedBroadwell.td

300 ↗

(On Diff #139909)

I'm going to add one in a separate commit.

D44933

[RKSimon]

Add WriteMMXMOVMSK class - avoids an extra 2 scheduler classes by merging with IIC_MMX_MOVMSK

[courbet]

SNB/HW/BW/SKL/SKX LGTM.

[RKSimon]

Thanks, @craig.topper do you have any comments about SLM before I commit?

[craig.topper]

SLM looks good. Agner's latency/throughput data agrees with the Intel Optimization manual.

llvm/trunk/lib/Target/X86/X86InstrMMX.td

 
 // Mask creation
 let Predicates = [HasSSE1] in
 def MMX_PMOVMSKBrr : MMXI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
                           (ins VR64:$src),
                           "pmovmskb\t{$src, $dst|$dst, $src}",
                           [(set GR32orGR64:$dst,
                                 (int_x86_mmx_pmovmskb VR64:$src))],
-                          IIC_MMX_MOVMSK>, Sched<[WriteVecLogic]>;
+                          IIC_MMX_MOVMSK>, Sched<[WriteMMXMOVMSK]>;
 
 // Low word of XMM to MMX.
 def MMX_X86movdq2q : SDNode<"X86ISD::MOVDQ2Q", SDTypeProfile<1, 1,
                             [SDTCisVT<0, x86mmx>, SDTCisVT<1, v2i64>]>>;
 
 def : Pat<(x86mmx (MMX_X86movdq2q VR128:$src)),
           (x86mmx (MMX_MOVDQ2Qrr VR128:$src))>;
 

llvm/trunk/lib/Target/X86/X86InstrSSE.td

 //===----------------------------------------------------------------------===//
 
 /// sse12_extr_sign_mask - sse 1 & 2 unpack and interleave
 multiclass sse12_extr_sign_mask<RegisterClass RC, ValueType vt,
                                 string asm, Domain d> {
   def rr : PI<0x50, MRMSrcReg, (outs GR32orGR64:$dst), (ins RC:$src),
               !strconcat(asm, "\t{$src, $dst|$dst, $src}"),
               [(set GR32orGR64:$dst, (X86movmsk (vt RC:$src)))], IIC_SSE_MOVMSK, d>,
-              Sched<[WriteVecLogic]>;
+              Sched<[WriteFMOVMSK]>;
 }
 
 let Predicates = [HasAVX] in {
   defm VMOVMSKPS : sse12_extr_sign_mask<VR128, v4f32, "movmskps",
                                         SSEPackedSingle>, PS, VEX, VEX_WIG;
   defm VMOVMSKPD : sse12_extr_sign_mask<VR128, v2f64, "movmskpd",
                                         SSEPackedDouble>, PD, VEX, VEX_WIG;
   defm VMOVMSKPSY : sse12_extr_sign_mask<VR256, v8f32, "movmskps",

 defm PINSRW : sse2_pinsrw, PD;
 
 } // ExeDomain = SSEPackedInt
 
 //===---------------------------------------------------------------------===//
 // SSE2 - Packed Mask Creation
 //===---------------------------------------------------------------------===//
 
-let ExeDomain = SSEPackedInt, SchedRW = [WriteVecLogic] in {
+let ExeDomain = SSEPackedInt, SchedRW = [WriteVecMOVMSK] in {
 
 def VPMOVMSKBrr  : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
            (ins VR128:$src),
            "pmovmskb\t{$src, $dst|$dst, $src}",
            [(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))],
            IIC_SSE_MOVMSK>, VEX, VEX_WIG;
 
 let Predicates = [HasAVX2] in {
 def VPMOVMSKBYrr  : VPDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst),
            (ins VR256:$src),
            "pmovmskb\t{$src, $dst|$dst, $src}",
-           [(set GR32orGR64:$dst, (X86movmsk (v32i8 VR256:$src)))]>,
-           VEX, VEX_L, VEX_WIG;
+           [(set GR32orGR64:$dst, (X86movmsk (v32i8 VR256:$src)))],
+           IIC_SSE_MOVMSK>, VEX, VEX_L, VEX_WIG;
 }
 
 def PMOVMSKBrr : PDI<0xD7, MRMSrcReg, (outs GR32orGR64:$dst), (ins VR128:$src),
            "pmovmskb\t{$src, $dst|$dst, $src}",
            [(set GR32orGR64:$dst, (X86movmsk (v16i8 VR128:$src)))],
            IIC_SSE_MOVMSK>;
 
 } // ExeDomain = SSEPackedInt

llvm/trunk/lib/Target/X86/X86SchedBroadwell.td

def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
   let ResourceCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
   let Latency = 23;
   let NumMicroOps = 9;
   let ResourceCycles = [4,3,1,1];
 }
 
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [BWPort0]> { let Latency = 3; }
+def : WriteRes<WriteVecMOVMSK, [BWPort0]> { let Latency = 3; }
+def : WriteRes<WriteMMXMOVMSK, [BWPort0]> { let Latency = 1; }
+
 // AES instructions.
 def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
   let Latency = 7;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
   let Latency = 12;

 
 def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
   let Latency = 1;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
                                            "MMX_MOVD64grr",
-                                           "MMX_PMOVMSKBrr",
                                            "MMX_PSLLDri",
                                            "MMX_PSLLDrr",
                                            "MMX_PSLLQri",
                                            "MMX_PSLLQrr",
                                            "MMX_PSLLWri",
                                            "MMX_PSLLWrr",
                                            "MMX_PSRADri",
                                            "MMX_PSRADrr",

 def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
 def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
                                             "PUSH64i8",
                                             "STOSB",
                                             "STOSL",
                                             "STOSQ",
                                             "STOSW")>;
 
-def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
-  let Latency = 3;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[BWWriteResGroup26], (instregex "(V?)MOVMSKPD(Y?)rr",
-                                            "(V?)MOVMSKPS(Y?)rr",
-                                            "(V?)PMOVMSKB(Y?)rr")>;
-
 def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
 def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
 def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",

llvm/trunk/lib/Target/X86/X86SchedHaswell.td

def : WriteRes<WritePCmpEStrI, [HWPort0, HWPort5, HWPort0156]> {
   let ResourceCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [HWPort0, HWPort5, HWPort23, HWPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
   let ResourceCycles = [4,3,1,1];
 }
 
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [HWPort0]> { let Latency = 3; }
+def : WriteRes<WriteVecMOVMSK, [HWPort0]> { let Latency = 3; }
+def : WriteRes<WriteMMXMOVMSK, [HWPort0]> { let Latency = 1; }
+
 // AES Instructions.
 def : WriteRes<WriteAESDecEnc, [HWPort5]> {
   let Latency = 7;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [HWPort5, HWPort23]> {
   let Latency = 13;

 
 def HWWriteResGroup2 : SchedWriteRes<[HWPort0]> {
   let Latency = 1;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def: InstRW<[HWWriteResGroup2], (instregex "MMX_MOVD64from64rr",
                                            "MMX_MOVD64grr",
-                                           "MMX_PMOVMSKBrr",
                                            "MMX_PSLLDri",
                                            "MMX_PSLLDrr",
                                            "MMX_PSLLQri",
                                            "MMX_PSLLQrr",
                                            "MMX_PSLLWri",
                                            "MMX_PSLLWrr",
                                            "MMX_PSRADri",
                                            "MMX_PSRADrr",

 def HWWriteResGroup48 : SchedWriteRes<[HWPort4,HWPort6,HWPort23,HWPort237,HWPort0156]> {
   let Latency = 8;
   let NumMicroOps = 5;
   let ResourceCycles = [1,1,1,1,1];
 }
 def: InstRW<[HWWriteResGroup48], (instregex "CALL(16|32|64)m",
                                             "FARCALL64")>;
 
-def HWWriteResGroup49 : SchedWriteRes<[HWPort0]> {
-  let Latency = 3;
-  let NumMicroOps = 1;
-  let ResourceCycles = [1];
-}
-def: InstRW<[HWWriteResGroup49], (instregex "(V?)MOVMSKPD(Y?)rr",
-                                            "(V?)MOVMSKPS(Y?)rr",
-                                            "(V?)PMOVMSKB(Y?)rr")>;
-
 def HWWriteResGroup50 : SchedWriteRes<[HWPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def: InstRW<[HWWriteResGroup50], (instrs MUL8r, IMUL8r, IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
 def: InstRW<[HWWriteResGroup50], (instregex "ADD_FPrST0",
                                             "ADD_FST0r",

llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td

def : WriteRes<WritePCmpEStrI, [SBPort015]> {
   let Latency = 4;
   let ResourceCycles = [8];
 }
 def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
   let Latency = 4;
   let ResourceCycles = [7, 1];
 }
 
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [SBPort0]> { let Latency = 2; }
+def : WriteRes<WriteVecMOVMSK, [SBPort0]> { let Latency = 2; }
+def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; }
+
 // AES Instructions.
 def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
   let Latency = 7;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
   let Latency = 13;
def: InstRW<[SBWriteResGroup6], (instregex "ADD(8|16|32|64)ri",
                                            "XOR(8|16|32|64)rr",
                                            "XOR(8|16|32|64)i")>;
 
 def SBWriteResGroup7 : SchedWriteRes<[SBPort0]> {
   let Latency = 2;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
-def: InstRW<[SBWriteResGroup7], (instregex "(V?)PMOVMSKBrr",
-                                           "(V?)MOVMSKPD(Y?)rr",
-                                           "(V?)MOVMSKPS(Y?)rr",
-                                           "(V?)MOVPDI2DIrr",
+def: InstRW<[SBWriteResGroup7], (instregex "(V?)MOVPDI2DIrr",
                                            "(V?)MOVPQIto64rr")>;
 
 def SBWriteResGroup9 : SchedWriteRes<[SBPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [2];
 }
 def: InstRW<[SBWriteResGroup9], (instregex "BLENDVPDrr0",

llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td

def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
   let ResourceCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
   let ResourceCycles = [4,3,1,1];
 }
 
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; }
+def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; }
+def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; }
+
 // AES instructions.
 def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
   let Latency = 4;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
   let Latency = 10;

 
 def SKLWriteResGroup12 : SchedWriteRes<[SKLPort0]> {
   let Latency = 2;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def: InstRW<[SKLWriteResGroup12], (instregex "MMX_MOVD64from64rr",
                                              "MMX_MOVD64grr",
-                                             "MMX_PMOVMSKBrr",
                                              "(V?)COMISDrr",
                                              "(V?)COMISSrr",
-                                             "(V?)MOVMSKPD(Y?)rr",
-                                             "(V?)MOVMSKPS(Y?)rr",
                                              "(V?)MOVPDI2DIrr",
                                              "(V?)MOVPQIto64rr",
-                                             "(V?)PMOVMSKB(Y?)rr",
                                              "VTESTPD(Y?)rr",
                                              "VTESTPS(Y?)rr",
                                              "(V?)UCOMISDrr",
                                              "(V?)UCOMISSrr")>;
 
 def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
   let Latency = 2;
   let NumMicroOps = 2;

llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> {
   let ResourceCycles = [4,3,1];
 }
 def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> {
   let Latency = 24;
   let NumMicroOps = 9;
   let ResourceCycles = [4,3,1,1];
 }
 
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; }
+def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; }
+def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; }
+
 // AES instructions.
 def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption.
   let Latency = 4;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> {
   let Latency = 10;
def SKXWriteResGroup12 : SchedWriteRes<[SKXPort0]> {
   let Latency = 2;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def: InstRW<[SKXWriteResGroup12], (instregex "COMISDrr",
                                              "COMISSrr",
                                              "MMX_MOVD64from64rr",
                                              "MMX_MOVD64grr",
-                                             "MMX_PMOVMSKBrr",
-                                             "MOVMSKPDrr",
-                                             "MOVMSKPSrr",
                                              "MOVPDI2DIrr",
                                              "MOVPQIto64rr",
-                                             "PMOVMSKBrr",
                                              "UCOMISDrr",
                                              "UCOMISSrr",
                                              "VCOMISDZrr(b?)",
                                              "VCOMISDrr",
                                              "VCOMISSZrr(b?)",
                                              "VCOMISSrr",
-                                             "VMOVMSKPDYrr",
-                                             "VMOVMSKPDrr",
-                                             "VMOVMSKPSYrr",
-                                             "VMOVMSKPSrr",
                                              "VMOVPDI2DIZrr(b?)(k?)(z?)",
                                              "VMOVPDI2DIrr",
                                              "VMOVPQIto64Zrr(b?)(k?)(z?)",
                                              "VMOVPQIto64rr",
-                                             "VPMOVMSKBYrr",
-                                             "VPMOVMSKBrr",
                                              "VTESTPDYrr",
                                              "VTESTPDrr",
                                              "VTESTPSYrr",
                                              "VTESTPSrr",
                                              "VUCOMISDZrr(b?)",
                                              "VUCOMISDrr",
                                              "VUCOMISSZrr(b?)",
                                              "VUCOMISSrr")>;

llvm/trunk/lib/Target/X86/X86Schedule.td

 defm WriteBlend  : X86SchedWritePair; // Vector blends.
 defm WriteVarBlend  : X86SchedWritePair; // Vector variable blends.
 defm WriteMPSAD : X86SchedWritePair; // Vector MPSAD.
 
 // Vector bitwise operations.
 // These are often used on both floating point and integer vectors.
 defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
 
+// MOVMSK operations.
+def WriteFMOVMSK : SchedWrite;
+def WriteVecMOVMSK : SchedWrite;
+def WriteMMXMOVMSK : SchedWrite;
+
 // Conversion between integer and float.
 defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
 defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
 defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
 
 // CRC32 instruction.
 defm WriteCRC32 : X86SchedWritePair;
 

llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResFpuPair<WritePCmpIStrI, [JFPU1, JVALU1, JFPA, JALU0], 7, [1, 2, 1, 1], 3>;
 defm : JWriteResFpuPair<WritePCmpIStrM, [JFPU1, JVALU1, JFPA, JALU0], 8, [1, 2, 1, 1], 3>;
 defm : JWriteResFpuPair<WritePCmpEStrI, [JFPU1, JSAGU, JLAGU, JVALU, JVALU1, JFPA, JALU0], 14, [1, 2, 2, 6, 4, 1, 1], 9>;
 defm : JWriteResFpuPair<WritePCmpEStrM, [JFPU1, JSAGU, JLAGU, JVALU, JVALU1, JFPA, JALU0], 14, [1, 2, 2, 6, 4, 1, 1], 9>;
 
 ////////////////////////////////////////////////////////////////////////////////
+// MOVMSK Instructions.
+////////////////////////////////////////////////////////////////////////////////
+
+def  : WriteRes<WriteFMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
+def  : WriteRes<WriteVecMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
+def  : WriteRes<WriteMMXMOVMSK, [JFPU0, JFPA, JALU0]> { let Latency = 3; }
+
+////////////////////////////////////////////////////////////////////////////////
 // AES Instructions.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResFpuPair<WriteAESIMC,      [JFPU0, JVIMUL], 2>;
 defm : JWriteResFpuPair<WriteAESKeyGen,   [JFPU0, JVIMUL], 2>;
 defm : JWriteResFpuPair<WriteAESDecEnc,   [JFPU0, JVIMUL], 3>;
 
 ////////////////////////////////////////////////////////////////////////////////

 
 def JWriteVMaskMovYSt: SchedWriteRes<[JFPU01, JFPX, JSAGU]> {
   let Latency = 6;
   let ResourceCycles = [2, 4, 2];
   let NumMicroOps = 2;
 }
 def : InstRW<[JWriteVMaskMovYSt], (instrs VMASKMOVPDYmr, VMASKMOVPSYmr)>;
 
-def JWriteVMOVMSK: SchedWriteRes<[JFPU0, JFPA, JALU0]> {
-  let Latency = 3;
-}
-def : InstRW<[JWriteVMOVMSK], (instrs MOVMSKPDrr, VMOVMSKPDrr, VMOVMSKPDYrr,
-                                      MOVMSKPSrr, VMOVMSKPSrr, VMOVMSKPSYrr,
-                                      PMOVMSKBrr, VPMOVMSKBrr, MMX_PMOVMSKBrr)>;
-
 def JWriteVTESTY: SchedWriteRes<[JFPU01, JFPX, JFPA, JALU0]> {
   let Latency = 4;
   let ResourceCycles = [2, 2, 2, 1];
   let NumMicroOps = 3;
 }
 def : InstRW<[JWriteVTESTY], (instrs VPTESTYrr, VTESTPDYrr, VTESTPSYrr)>;
 
 def JWriteVTESTYLd: SchedWriteRes<[JLAGU, JFPU01, JFPX, JFPA, JALU0]> {

llvm/trunk/lib/Target/X86/X86ScheduleSLM.td

def : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> {
   let Latency = 21;
   let ResourceCycles = [21];
 }
 def : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
   let Latency = 21;
   let ResourceCycles = [21, 1];
 }
 
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
+def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
+def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; }
+
 // AES Instructions.
 def : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> {
   let Latency = 8;
   let ResourceCycles = [5];
 }
 def : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
   let Latency = 8;
   let ResourceCycles = [5, 1];

llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

 defm : ZnWriteResFpuPair<WriteVecIMul,    [ZnFPU0],  4>;
 defm : ZnWriteResFpuPair<WriteShuffle,    [ZnFPU],   1>;
 defm : ZnWriteResFpuPair<WriteBlend,      [ZnFPU01], 1>;
 defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU],   2>;
 
 // Vector Shift Operations
 defm : ZnWriteResFpuPair<WriteVarVecShift, [ZnFPU12], 1>;
 
+// MOVMSK Instructions.
+def : WriteRes<WriteFMOVMSK, [ZnFPU2]>;
+def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>;
+def : WriteRes<WriteMMXMOVMSK, [ZnFPU2]>;
+
 // AES Instructions.
 defm : ZnWriteResFpuPair<WriteAESDecEnc, [ZnFPU01], 4>;
 defm : ZnWriteResFpuPair<WriteAESIMC,    [ZnFPU01], 4>;
 defm : ZnWriteResFpuPair<WriteAESKeyGen, [ZnFPU01], 4>;
 
 def : WriteRes<WriteFence,  [ZnAGU]>;
 def : WriteRes<WriteNop, []>;
 

 def : InstRW<[ZnWriteFPU01Op2],(instregex "VPMASKMOVQrm")>;
 def : InstRW<[ZnWriteFPU01Op2Y],(instregex "VPMASKMOVQYrm")>;
 
 def : InstRW<[WriteMicrocoded],
                                (instregex "VPMASKMOVD(Y?)rm")>;
 // m, v,v.
 def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>;
 
-// PMOVMSKB.
-def ZnWritePMOVMSKB : SchedWriteRes<[ZnFPU2]> {
-  let NumMicroOps = 2;
-}
+// PMOVMSKBY.
 def ZnWritePMOVMSKBY : SchedWriteRes<[ZnFPU2]> {
+  let NumMicroOps = 2;
   let Latency = 2;
+  let ResourceCycles = [2];
 }
-def : InstRW<[ZnWritePMOVMSKB], (instregex "(V|MMX_)?PMOVMSKBrr")>;
 def : InstRW<[ZnWritePMOVMSKBY], (instregex "(V|MMX_)?PMOVMSKBYrr")>;
 
 // PEXTR B/W/D/Q.
 // r32,x,i.
 def ZnWritePEXTRr : SchedWriteRes<[ZnFPU12, ZnFPU2]> {
   let Latency = 2;
   let ResourceCycles = [1, 2];
 }

 
 // PSLL,PSRL DQ.
 def : InstRW<[ZnWritePShift], (instregex "(V?)PS(R|L)LDQri")>;
 def : InstRW<[ZnWritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>;
 
 //=== Floating Point XMM and YMM Instructions ===//
 //-- Move instructions --//
 
-// MOVMSKP S/D.
-// r32 <- x,y.
-def ZnWriteMOVMSKPr : SchedWriteRes<[ZnFPU2]> ;
-def : InstRW<[ZnWriteMOVMSKPr], (instregex "(V?)MOVMSKP(S|D)(Y?)rr")>;
-
 // VPERM2F128.
 def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rr")>;
 def : InstRW<[WriteMicrocoded], (instregex "VPERM2F128rm")>;
 
 // BLENDVP S/D.
 def ZnWriteFPU01Lat3 : SchedWriteRes<[ZnFPU013]> {
   let Latency = 3;
 }

llvm/trunk/test/CodeGen/X86/avx2-schedule.ll

; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %3 = call <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16> %1, <16 x i16> %2)
   ret <16 x i16> %3
 }
 declare <16 x i16> @llvm.x86.avx2.pminu.w(<16 x i16>, <16 x i16>) nounwind readnone
 
 define i32 @test_pmovmskb(<32 x i8> %a0) {
 ; GENERIC-LABEL: test_pmovmskb:
 ; GENERIC:       # %bb.0:
-; GENERIC-NEXT:    vpmovmskb %ymm0, %eax # sched: [1:1.00]
+; GENERIC-NEXT:    vpmovmskb %ymm0, %eax # sched: [2:1.00]
 ; GENERIC-NEXT:    vzeroupper # sched: [100:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_pmovmskb:
 ; HASWELL:       # %bb.0:
 ; HASWELL-NEXT:    vpmovmskb %ymm0, %eax # sched: [3:1.00]
 ; HASWELL-NEXT:    vzeroupper # sched: [4:1.00]
 ; HASWELL-NEXT:    retq # sched: [7:1.00]

 ; SKX-LABEL: test_pmovmskb:
 ; SKX:       # %bb.0:
 ; SKX-NEXT:    vpmovmskb %ymm0, %eax # sched: [2:1.00]
 ; SKX-NEXT:    vzeroupper # sched: [4:1.00]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; ZNVER1-LABEL: test_pmovmskb:
 ; ZNVER1:       # %bb.0:
-; ZNVER1-NEXT:    vpmovmskb %ymm0, %eax # sched: [2:1.00]
+; ZNVER1-NEXT:    vpmovmskb %ymm0, %eax # sched: [2:2.00]
 ; ZNVER1-NEXT:    vzeroupper # sched: [100:?]
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %1 = call i32 @llvm.x86.avx2.pmovmskb(<32 x i8> %a0)
   ret i32 %1
 }
 declare i32 @llvm.x86.avx2.pmovmskb(<32 x i8>) nounwind readnone
 
 define <8 x i32> @test_pmovsxbd(<16 x i8> %a0, <16 x i8> *%a1) {

llvm/trunk/test/CodeGen/X86/mmx-schedule.ll

 ;
 ; ATOM-LABEL: test_pmovmskb:
 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    pmovmskb %mm0, %eax # sched: [3:3.00]
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_pmovmskb:
 ; SLM:       # %bb.0:
-; SLM-NEXT:    pmovmskb %mm0, %eax # sched: [1:0.50]
+; SLM-NEXT:    pmovmskb %mm0, %eax # sched: [4:1.00]
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_pmovmskb:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    pmovmskb %mm0, %eax # sched: [1:1.00]
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_pmovmskb:

llvm/trunk/test/CodeGen/X86/sse-schedule.ll

 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    movmskps %xmm0, %eax # sched: [3:3.00]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_movmskps:
 ; SLM:       # %bb.0:
-; SLM-NEXT:    movmskps %xmm0, %eax # sched: [1:0.50]
+; SLM-NEXT:    movmskps %xmm0, %eax # sched: [4:1.00]
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-SSE-LABEL: test_movmskps:
 ; SANDY-SSE:       # %bb.0:
 ; SANDY-SSE-NEXT:    movmskps %xmm0, %eax # sched: [2:1.00]
 ; SANDY-SSE-NEXT:    retq # sched: [1:1.00]
 ;
 ; SANDY-LABEL: test_movmskps:

llvm/trunk/test/CodeGen/X86/sse2-schedule.ll

 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    movmskpd %xmm0, %eax # sched: [3:3.00]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_movmskpd:
 ; SLM:       # %bb.0:
-; SLM-NEXT:    movmskpd %xmm0, %eax # sched: [1:0.50]
+; SLM-NEXT:    movmskpd %xmm0, %eax # sched: [4:1.00]
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-SSE-LABEL: test_movmskpd:
 ; SANDY-SSE:       # %bb.0:
 ; SANDY-SSE-NEXT:    movmskpd %xmm0, %eax # sched: [2:1.00]
 ; SANDY-SSE-NEXT:    retq # sched: [1:1.00]
 ;
 ; SANDY-LABEL: test_movmskpd:

 ; ATOM:       # %bb.0:
 ; ATOM-NEXT:    pmovmskb %xmm0, %eax # sched: [3:3.00]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    nop # sched: [1:0.50]
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_pmovmskb:
 ; SLM:       # %bb.0:
-; SLM-NEXT:    pmovmskb %xmm0, %eax # sched: [1:0.50]
+; SLM-NEXT:    pmovmskb %xmm0, %eax # sched: [4:1.00]
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-SSE-LABEL: test_pmovmskb:
 ; SANDY-SSE:       # %bb.0:
 ; SANDY-SSE-NEXT:    pmovmskb %xmm0, %eax # sched: [2:1.00]
 ; SANDY-SSE-NEXT:    retq # sched: [1:1.00]
 ;
 ; SANDY-LABEL: test_pmovmskb: