[X86] Add WriteCRC32 scheduler class

[RKSimon]

Summary

Currently CRC32 instructions use the WriteFAdd class, this patch splits them off into their own.

At the moment WriteCRC32 is mostly just a duplicate of WriteFAdd but it can now be tweaked on a target by target basis.

SandyBridge is interesting as its custom memory latencies don't often match the +4 cy in SBWriteResPair - I can add a 'memory latency' optional argument to SBWriteResPair to make it easier to remedy these cases if people want?

[craig.topper]

Do any instructions on Sandybridge have a Custom load latency of 4? Looks like the most basic instruction like ADD32rr vs ADD32rm has a difference of 5 cycles.

[RKSimon]

In D44647#1042327, @craig.topper wrote:

Do any instructions on Sandybridge have a Custom load latency of 4? Looks like the most basic instruction like ADD32rr vs ADD32rm has a difference of 5 cycles.

You're right - +5 is probably the best option - I'll see what happens if I alter the default.

[RKSimon]

Rebased

[craig.topper]

LGTM

llvm/trunk/lib/Target/X86/X86InstrSSE.td

 // crc intrinsic instruction
 // This set of instructions are only rm, the only difference is the size
 // of r and m.
 class SS42I_crc32r<bits<8> opc, string asm, RegisterClass RCOut,
                    RegisterClass RCIn, SDPatternOperator Int> :
   SS42FI<opc, MRMSrcReg, (outs RCOut:$dst), (ins RCOut:$src1, RCIn:$src2),
          !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
          [(set RCOut:$dst, (Int RCOut:$src1, RCIn:$src2))], IIC_CRC32_REG>,
-         Sched<[WriteFAdd]>;
+         Sched<[WriteCRC32]>;
 
 class SS42I_crc32m<bits<8> opc, string asm, RegisterClass RCOut,
                    X86MemOperand x86memop, SDPatternOperator Int> :
   SS42FI<opc, MRMSrcMem, (outs RCOut:$dst), (ins RCOut:$src1, x86memop:$src2),
          !strconcat(asm, "\t{$src2, $src1|$src1, $src2}"),
          [(set RCOut:$dst, (Int RCOut:$src1, (load addr:$src2)))],
-         IIC_CRC32_MEM>, Sched<[WriteFAddLd, ReadAfterLd]>;
+         IIC_CRC32_MEM>, Sched<[WriteCRC32Ld, ReadAfterLd]>;
 
 let Constraints = "$src1 = $dst" in {
   def CRC32r32m8  : SS42I_crc32m<0xF0, "crc32{b}", GR32, i8mem,
                                  int_x86_sse42_crc32_32_8>;
   def CRC32r32r8  : SS42I_crc32r<0xF0, "crc32{b}", GR32, GR8,
                                  int_x86_sse42_crc32_32_8>;
   def CRC32r32m16 : SS42I_crc32m<0xF1, "crc32{w}", GR32, i16mem,
                                  int_x86_sse42_crc32_32_16>, OpSize16;

llvm/trunk/lib/Target/X86/X86SchedBroadwell.td

 // A folded store needs a cycle on port 4 for the store data, but it does not
 // need an extra port 2/3 cycle to recompute the address.
 def : WriteRes<WriteRMW, [BWPort4]>;
 
 // Arithmetic.
 defm : BWWriteResPair<WriteALU,   [BWPort0156], 1>; // Simple integer ALU op.
 defm : BWWriteResPair<WriteIMul,  [BWPort1],   3>; // Integer multiplication.
 defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
+defm : BWWriteResPair<WriteCRC32, [BWPort1],   3>;
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 
 def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
 
 // Bit counts.
 defm : BWWriteResPair<WriteBitScan, [BWPort1], 3>;
 defm : BWWriteResPair<WriteLZCNT,   [BWPort1], 3>;
 defm : BWWriteResPair<WriteTZCNT,   [BWPort1], 3>;

llvm/trunk/lib/Target/X86/X86SchedHaswell.td

 def : WriteRes<WriteMove,  [HWPort0156]>;
 def : WriteRes<WriteZero,  []>;
 
 defm : HWWriteResPair<WriteALU,   [HWPort0156], 1>;
 defm : HWWriteResPair<WriteIMul,  [HWPort1],   3>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 defm : HWWriteResPair<WriteShift, [HWPort06],  1>;
 defm : HWWriteResPair<WriteJump,  [HWPort06],   1>;
+defm : HWWriteResPair<WriteCRC32, [HWPort1],   3>;
 
 // This is for simple LEAs with one or two input operands.
 // The complex ones can only execute on port 1, and they require two cycles on
 // the port to read all inputs. We don't model that.
 def : WriteRes<WriteLEA, [HWPort15]>;
 
 // Bit counts.
 defm : HWWriteResPair<WriteBitScan, [HWPort1], 3>;

llvm/trunk/lib/Target/X86/X86SchedSandyBridge.td

 
 defm : SBWriteResPair<WriteALU,   [SBPort015], 1>;
 defm : SBWriteResPair<WriteIMul,  [SBPort1],   3>;
 defm : SBWriteResPair<WriteIDiv, [SBPort0, SBDivider], 25, [1, 10]>;
 def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
 
 defm : SBWriteResPair<WriteShift, [SBPort05],  1>;
 defm : SBWriteResPair<WriteJump,  [SBPort5],   1>;
+defm : SBWriteResPair<WriteCRC32, [SBPort1],   3, [1], 1, 5>;
 
 // This is for simple LEAs with one or two input operands.
 // The complex ones can only execute on port 1, and they require two cycles on
 // the port to read all inputs. We don't model that.
 def : WriteRes<WriteLEA, [SBPort15]>;
 
 // Bit counts.
 defm : SBWriteResPair<WriteBitScan, [SBPort1], 3, [1], 1, 5>;
def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
   let Latency = 3;
   let NumMicroOps = 1;
   let ResourceCycles = [1];
 }
 def: InstRW<[SBWriteResGroup21], (instrs MUL8r, IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
 def: InstRW<[SBWriteResGroup21], (instregex "ADD_FPrST0",
                                             "ADD_FST0r",
                                             "ADD_FrST0",
-                                            "CRC32r(16|32|64)r8",
-                                            "CRC32r(16|32|64)r64",
                                             "MMX_CVTPI2PSirr",
                                             "MMX_CVTPS2PIirr",
                                             "MMX_CVTTPS2PIirr",
                                             "POPCNT(16|32|64)rr",
                                             "PUSHFS64",
                                             "SUBR_FPrST0",
                                             "SUBR_FST0r",
                                             "SUBR_FrST0",

 def: InstRW<[SBWriteResGroup71], (instregex "VTESTPDYrm",
                                             "VTESTPSYrm")>;
 
 def SBWriteResGroup72 : SchedWriteRes<[SBPort1,SBPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
-def: InstRW<[SBWriteResGroup72], (instregex "CRC32r(16|32|64)m64",
-                                            "CRC32r(16|32|64)m8",
-                                            "FCOM32m",
+def: InstRW<[SBWriteResGroup72], (instregex "FCOM32m",
                                             "FCOM64m",
                                             "FCOMP32m",
                                             "FCOMP64m")>;
 def: InstRW<[SBWriteResGroup72], (instrs MUL8m)>;
 
 def SBWriteResGroup73 : SchedWriteRes<[SBPort5,SBPort23]> {
   let Latency = 8;
   let NumMicroOps = 2;

llvm/trunk/lib/Target/X86/X86SchedSkylakeClient.td

 // A folded store needs a cycle on port 4 for the store data, but it does not
 // need an extra port 2/3 cycle to recompute the address.
 def : WriteRes<WriteRMW, [SKLPort4]>;
 
 // Arithmetic.
 defm : SKLWriteResPair<WriteALU,   [SKLPort0156], 1>; // Simple integer ALU op.
 defm : SKLWriteResPair<WriteIMul,  [SKLPort1],   3>; // Integer multiplication.
 defm : SKLWriteResPair<WriteIDiv, [SKLPort0, SKLDivider], 25, [1,10], 1, 4>; // Integer division.
+defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
 
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
 
 // Bit counts.
 defm : SKLWriteResPair<WriteBitScan, [SKLPort1], 3>;
 defm : SKLWriteResPair<WriteLZCNT,   [SKLPort1], 3>;
 defm : SKLWriteResPair<WriteTZCNT,   [SKLPort1], 3>;

llvm/trunk/lib/Target/X86/X86SchedSkylakeServer.td

 // A folded store needs a cycle on port 4 for the store data, but it does not
 // need an extra port 2/3 cycle to recompute the address.
 def : WriteRes<WriteRMW, [SKXPort4]>;
 
 // Arithmetic.
 defm : SKXWriteResPair<WriteALU,   [SKXPort0156], 1>; // Simple integer ALU op.
 defm : SKXWriteResPair<WriteIMul,  [SKXPort1],   3>; // Integer multiplication.
 defm : SKXWriteResPair<WriteIDiv, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>; // Integer division.
+defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>;
 
 def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
 def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads.
 
 // Integer shifts and rotates.
 defm : SKXWriteResPair<WriteShift, [SKXPort06],  1>;
 
 // Bit counts.

llvm/trunk/lib/Target/X86/X86Schedule.td

 // These are often used on both floating point and integer vectors.
 defm WriteVecLogic : X86SchedWritePair; // Vector and/or/xor.
 
 // Conversion between integer and float.
 defm WriteCvtF2I : X86SchedWritePair; // Float -> Integer.
 defm WriteCvtI2F : X86SchedWritePair; // Integer -> Float.
 defm WriteCvtF2F : X86SchedWritePair; // Float -> Float size conversion.
 
+// CRC32 instruction.
+defm WriteCRC32 : X86SchedWritePair;
+
 // Strings instructions.
 // Packed Compare Implicit Length Strings, Return Mask
 defm WritePCmpIStrM : X86SchedWritePair;
 // Packed Compare Explicit Length Strings, Return Mask
 defm WritePCmpEStrM : X86SchedWritePair;
 // Packed Compare Implicit Length Strings, Return Index
 defm WritePCmpIStrI : X86SchedWritePair;
 // Packed Compare Explicit Length Strings, Return Index

llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

 
 ////////////////////////////////////////////////////////////////////////////////
 // Arithmetic.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResIntPair<WriteALU,   [JALU01], 1>;
 defm : JWriteResIntPair<WriteIMul,  [JALU1, JMul], 3, [1, 1], 2>; // i8/i16/i32 multiplication
 defm : JWriteResIntPair<WriteIDiv,  [JALU1, JDiv], 41, [1, 41], 2>; // Worst case (i64 division)
+defm : JWriteResIntPair<WriteCRC32, [JALU01], 3, [4], 3>;
 
 def  : WriteRes<WriteIMulH, [JALU1]> {
   let Latency = 6;
   let ResourceCycles = [4];
 }
 
 // This is for simple LEAs with one or two input operands.
 // FIXME: SAGU 3-operand LEA

 def JWriteIDiv32Ld : SchedWriteRes<[JLAGU, JALU1, JDiv]> {
   let Latency = 28;
   let ResourceCycles = [1, 1, 25];
   let NumMicroOps = 2;
 }
 def : InstRW<[JWriteIDiv32], (instrs DIV32r, IDIV32r)>;
 def : InstRW<[JWriteIDiv32Ld], (instrs DIV32m, IDIV32m)>;
 
-def JWriteCRC32 : SchedWriteRes<[JALU01]> {
-  let Latency = 3;
-  let ResourceCycles = [4];
-  let NumMicroOps = 3;
-}
-def : InstRW<[JWriteCRC32], (instrs CRC32r32r8, CRC32r32r16, CRC32r32r32,
-                                    CRC32r64r8, CRC32r64r64)>;
-
-def JWriteCRC32Ld : SchedWriteRes<[JLAGU, JALU01]> {
-  let Latency = 6;
-  let ResourceCycles = [1, 4];
-  let NumMicroOps = 3;
-}
-def : InstRW<[JWriteCRC32Ld], (instrs CRC32r32m8, CRC32r32m16, CRC32r32m32,
-                                      CRC32r64m8, CRC32r64m64)>;
-
 ////////////////////////////////////////////////////////////////////////////////
 // Integer shifts and rotates.
 ////////////////////////////////////////////////////////////////////////////////
 
 defm : JWriteResIntPair<WriteShift, [JALU01], 1>;
 
 def JWriteSHLDrri : SchedWriteRes<[JALU01]> {
   let Latency = 3;

llvm/trunk/lib/Target/X86/X86ScheduleSLM.td

 def : WriteRes<WriteZero,  []>;
 
 // Treat misc copies as a move.
 def : InstRW<[WriteMove], (instrs COPY)>;
 
 defm : SLMWriteResPair<WriteALU,   [SLM_IEC_RSV01], 1>;
 defm : SLMWriteResPair<WriteIMul,  [SLM_IEC_RSV1],  3>;
 defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0],  1>;
-defm : SLMWriteResPair<WriteJump,  [SLM_IEC_RSV1],   1>;
+defm : SLMWriteResPair<WriteJump,  [SLM_IEC_RSV1],  1>;
+defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1],  3>;
 
 // This is for simple LEAs with one or two input operands.
 // The complex ones can only execute on port 1, and they require two cycles on
 // the port to read all inputs. We don't model that.
 def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
 
 // Bit counts.
 defm : SLMWriteResPair<WriteBitScan, [SLM_IEC_RSV01], 10, [20], 10>;

llvm/trunk/lib/Target/X86/X86ScheduleZnver1.td

 def : WriteRes<WriteLoad,  [ZnAGU]> { let Latency = 8; }
 
 def : WriteRes<WriteZero,  []>;
 def : WriteRes<WriteLEA, [ZnALU]>;
 defm : ZnWriteResPair<WriteALU,   [ZnALU], 1>;
 defm : ZnWriteResPair<WriteIMul,   [ZnALU1, ZnMultiplier], 4>;
 defm : ZnWriteResPair<WriteShift, [ZnALU], 1>;
 defm : ZnWriteResPair<WriteJump,  [ZnALU], 1>;
+defm : ZnWriteResFpuPair<WriteCRC32, [ZnFPU0], 3>;
 
 // Bit counts.
 defm : ZnWriteResPair<WriteBitScan, [ZnALU], 3>;
 defm : ZnWriteResPair<WriteLZCNT,   [ZnALU], 2>;
 defm : ZnWriteResPair<WriteTZCNT,   [ZnALU], 2>;
 defm : ZnWriteResPair<WritePOPCNT,  [ZnALU], 1>;
 
 // Treat misc copies as a move.

llvm/trunk/test/CodeGen/X86/sse42-schedule.ll

; ZNVER1-NEXT:    retq # sched: [1:0.50]
   ret i32 %3
 }
 declare i32 @llvm.x86.sse42.crc32.32.8(i32, i8) nounwind
 
 define i32 @crc32_32_16(i32 %a0, i16 %a1, i16 *%a2) {
 ; GENERIC-LABEL: crc32_32_16:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    crc32w %si, %edi # sched: [3:1.00]
-; GENERIC-NEXT:    crc32w (%rdx), %edi # sched: [7:1.00]
+; GENERIC-NEXT:    crc32w (%rdx), %edi # sched: [8:1.00]
 ; GENERIC-NEXT:    movl %edi, %eax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; SLM-LABEL: crc32_32_16:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    crc32w %si, %edi # sched: [3:1.00]
 ; SLM-NEXT:    crc32w (%rdx), %edi # sched: [6:1.00]
 ; SLM-NEXT:    movl %edi, %eax # sched: [1:0.50]
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-SSE-LABEL: crc32_32_16:
 ; SANDY-SSE:       # %bb.0:
 ; SANDY-SSE-NEXT:    crc32w %si, %edi # sched: [3:1.00]
-; SANDY-SSE-NEXT:    crc32w (%rdx), %edi # sched: [7:1.00]
+; SANDY-SSE-NEXT:    crc32w (%rdx), %edi # sched: [8:1.00]
 ; SANDY-SSE-NEXT:    movl %edi, %eax # sched: [1:0.33]
 ; SANDY-SSE-NEXT:    retq # sched: [1:1.00]
 ;
 ; SANDY-LABEL: crc32_32_16:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    crc32w %si, %edi # sched: [3:1.00]
-; SANDY-NEXT:    crc32w (%rdx), %edi # sched: [7:1.00]
+; SANDY-NEXT:    crc32w (%rdx), %edi # sched: [8:1.00]
 ; SANDY-NEXT:    movl %edi, %eax # sched: [1:0.33]
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-SSE-LABEL: crc32_32_16:
 ; HASWELL-SSE:       # %bb.0:
 ; HASWELL-SSE-NEXT:    crc32w %si, %edi # sched: [3:1.00]
 ; HASWELL-SSE-NEXT:    crc32w (%rdx), %edi # sched: [8:1.00]
 ; HASWELL-SSE-NEXT:    movl %edi, %eax # sched: [1:0.25]
; ZNVER1-NEXT:    retq # sched: [1:0.50]
   ret i32 %3
 }
 declare i32 @llvm.x86.sse42.crc32.32.16(i32, i16) nounwind
 
 define i32 @crc32_32_32(i32 %a0, i32 %a1, i32 *%a2) {
 ; GENERIC-LABEL: crc32_32_32:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    crc32l %esi, %edi # sched: [3:1.00]
-; GENERIC-NEXT:    crc32l (%rdx), %edi # sched: [7:1.00]
+; GENERIC-NEXT:    crc32l (%rdx), %edi # sched: [8:1.00]
 ; GENERIC-NEXT:    movl %edi, %eax # sched: [1:0.33]
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; SLM-LABEL: crc32_32_32:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    crc32l %esi, %edi # sched: [3:1.00]
 ; SLM-NEXT:    crc32l (%rdx), %edi # sched: [6:1.00]
 ; SLM-NEXT:    movl %edi, %eax # sched: [1:0.50]
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-SSE-LABEL: crc32_32_32:
 ; SANDY-SSE:       # %bb.0:
 ; SANDY-SSE-NEXT:    crc32l %esi, %edi # sched: [3:1.00]
-; SANDY-SSE-NEXT:    crc32l (%rdx), %edi # sched: [7:1.00]
+; SANDY-SSE-NEXT:    crc32l (%rdx), %edi # sched: [8:1.00]
 ; SANDY-SSE-NEXT:    movl %edi, %eax # sched: [1:0.33]
 ; SANDY-SSE-NEXT:    retq # sched: [1:1.00]
 ;
 ; SANDY-LABEL: crc32_32_32:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    crc32l %esi, %edi # sched: [3:1.00]
-; SANDY-NEXT:    crc32l (%rdx), %edi # sched: [7:1.00]
+; SANDY-NEXT:    crc32l (%rdx), %edi # sched: [8:1.00]
 ; SANDY-NEXT:    movl %edi, %eax # sched: [1:0.33]
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-SSE-LABEL: crc32_32_32:
 ; HASWELL-SSE:       # %bb.0:
 ; HASWELL-SSE-NEXT:    crc32l %esi, %edi # sched: [3:1.00]
 ; HASWELL-SSE-NEXT:    crc32l (%rdx), %edi # sched: [8:1.00]
 ; HASWELL-SSE-NEXT:    movl %edi, %eax # sched: [1:0.25]