[x86] put nops into the WriteNop class and customize for Jaguar

[spatel]

Summary

1. Given that we already have a classification bucket with 'nop' in the name, I think that's where 'nop' belongs. Right now, it's only otherwise used for prefix bytes.
2. Make the latency of this class '0' because it has no dependencies.

I'm stopping there to make sure I'm on the right track. If so, then I can change other CPU sched models where either latency is not set to 0 for WriteNop (eg SNB) or it's explicitly overridden by instregex (eg HSW).

[RKSimon]

x87 fnop as well?

test/CodeGen/X86/schedule-x86_64.ll

8398 ↗

(On Diff #138852)

According to the 16h SOG tables, these should be [1:0.5] on the ALU pipes

[spatel]

Patch updated:

1. Use latency = 1 and specify units for Jaguar. As noted in the comment, this tells the scheduler (and presumably llvm-mca) how to model the resource requirements better even though a nop has no dependencies.
2. Move 'fnop' from the default WriteMicrocoded class to WriteNop. This may not be completely accurate for Jaguar, but it's still closer to the truth (and also for Silvermont based on Agner's tables).

[courbet]

In D44608#1041238, @spatel wrote:

2. Move 'fnop' from the default WriteMicrocoded class to WriteNop. This may not be completely accurate for Jaguar, but it's still closer to the truth (and also for Silvermont based on Agner's tables).

I agree that this is likely more accurate latencywise, and that WriteNop is a very reasonable default. Intel scheduling models override it anyway for each microarchitecture.

llvm/trunk/lib/Target/X86/X86InstrFPStack.td

 def FFREEP : FPI<0xDF, MRM0r, (outs), (ins RST:$reg),
                 "ffreep\t$reg", IIC_FFREE>;
 
 // Clear exceptions
 def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>;
 } // Defs = [FPSW]
 } // SchedRW
 
-// Operandless floating-point instructions for the disassembler.
-let SchedRW = [WriteMicrocoded] in {
-def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>;
+// Operand-less floating-point instructions for the disassembler.
+def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>, Sched<[WriteNop]>;
 
+let SchedRW = [WriteMicrocoded] in {
 let Defs = [FPSW] in {
 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
 def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>;
 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>;
 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>;
 def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>;
 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>;
 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>;

llvm/trunk/lib/Target/X86/X86InstrInfo.td

def trunc_su : PatFrag<(ops node:$src), (trunc node:$src), [{
   return N->hasOneUse();
 }]>;
 
 //===----------------------------------------------------------------------===//
 // Instruction list.
 //
 
 // Nop
-let hasSideEffects = 0, SchedRW = [WriteZero] in {
+let hasSideEffects = 0, SchedRW = [WriteNop] in {
   def NOOP : I<0x90, RawFrm, (outs), (ins), "nop", [], IIC_NOP>;
   def NOOPW : I<0x1f, MRMXm, (outs), (ins i16mem:$zero),
                 "nop{w}\t$zero", [], IIC_NOP>, TB, OpSize16;
   def NOOPL : I<0x1f, MRMXm, (outs), (ins i32mem:$zero),
                 "nop{l}\t$zero", [], IIC_NOP>, TB, OpSize32;
   def NOOPQ : RI<0x1f, MRMXm, (outs), (ins i64mem:$zero),
                 "nop{q}\t$zero", [], IIC_NOP>, TB,
                 Requires<[In64BitMode]>;

llvm/trunk/lib/Target/X86/X86ScheduleBtVer2.td

 
 ////////////////////////////////////////////////////////////////////////////////
 // Special case scheduling classes.
 ////////////////////////////////////////////////////////////////////////////////
 
 def : WriteRes<WriteSystem,     [JALU01]> { let Latency = 100; }
 def : WriteRes<WriteMicrocoded, [JALU01]> { let Latency = 100; }
 def : WriteRes<WriteFence,  [JSAGU]>;
-def : WriteRes<WriteNop, []>;
+// Nops don't have dependencies, so there's no actual latency, but we set this
+// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle.
+def : WriteRes<WriteNop, [JALU01]> { let Latency = 1; }
 
 ////////////////////////////////////////////////////////////////////////////////
 // Floating point. This covers both scalar and vector operations.
 // FIXME: should we bother splitting JFPU pipe + unit stages for fast instructions?
 // FIXME: Double precision latencies
 // FIXME: SS vs PS latencies
 ////////////////////////////////////////////////////////////////////////////////
 

llvm/trunk/test/CodeGen/X86/schedule-x86_64.ll

 ; SKX-NEXT:    nopq %rdx # sched: [1:0.25]
 ; SKX-NEXT:    nopq (%r9) # sched: [1:0.25]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_nop:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    nop # sched: [1:?]
-; BTVER2-NEXT:    nopw %di # sched: [1:?]
-; BTVER2-NEXT:    nopw (%rcx) # sched: [1:?]
-; BTVER2-NEXT:    nopl %esi # sched: [1:?]
-; BTVER2-NEXT:    nopl (%r8) # sched: [1:?]
-; BTVER2-NEXT:    nopq %rdx # sched: [1:?]
-; BTVER2-NEXT:    nopq (%r9) # sched: [1:?]
+; BTVER2-NEXT:    nop # sched: [1:0.50]
+; BTVER2-NEXT:    nopw %di # sched: [1:0.50]
+; BTVER2-NEXT:    nopw (%rcx) # sched: [1:0.50]
+; BTVER2-NEXT:    nopl %esi # sched: [1:0.50]
+; BTVER2-NEXT:    nopl (%r8) # sched: [1:0.50]
+; BTVER2-NEXT:    nopq %rdx # sched: [1:0.50]
+; BTVER2-NEXT:    nopq (%r9) # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_nop:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    nop # sched: [1:?]
 ; ZNVER1-NEXT:    nopw %di # sched: [1:?]

 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    pause # sched: [140:1.00]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_pause:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    pause # sched: [1:?]
+; BTVER2-NEXT:    pause # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_pause:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    pause # sched: [100:?]
 ; ZNVER1-NEXT:    #NO_APP

llvm/trunk/test/CodeGen/X86/sse-schedule.ll

; ZNVER1-NEXT:    retq # sched: [1:0.50]
   %3 = xor <4 x i32> %1, %2
   %4 = load <4 x float>, <4 x float> *%a2, align 16
   %5 = bitcast <4 x float> %4 to <4 x i32>
   %6 = xor <4 x i32> %3, %5
   %7 = bitcast <4 x i32> %6 to <4 x float>
   ret <4 x float> %7
 }
 
-; 'WriteZero' class instructions.
+; 'WriteZero' and 'WriteNop' class instructions.
 
 define <4 x float> @test_fnop() nounwind {
 ; GENERIC-LABEL: test_fnop:
 ; GENERIC:       # %bb.0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    nop # sched: [1:?]
 ; GENERIC-NEXT:    #NO_APP
 ; GENERIC-NEXT:    xorps %xmm0, %xmm0 # sched: [1:1.00]

 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.33]
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_fnop:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.50]
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    nop # sched: [1:?]
+; BTVER2-NEXT:    nop # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fnop:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    vxorps %xmm0, %xmm0, %xmm0 # sched: [1:0.25]
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    nop # sched: [1:?]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm sideeffect "nop", ""() nounwind
   ret <4 x float> zeroinitializer
 }
 
 !0 = !{i32 1}

llvm/trunk/test/CodeGen/X86/x87-schedule.ll

 ; ATOM-NEXT:    #APP
 ; ATOM-NEXT:    fnop # sched: [1:0.50]
 ; ATOM-NEXT:    #NO_APP
 ; ATOM-NEXT:    retl # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_fnop:
 ; SLM:       # %bb.0:
 ; SLM-NEXT:    #APP
-; SLM-NEXT:    fnop # sched: [100:1.00]
+; SLM-NEXT:    fnop # sched: [1:?]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retl # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_fnop:
 ; SANDY:       # %bb.0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    fnop # sched: [1:1.00]
 ; SANDY-NEXT:    #NO_APP

 ; SKX-NEXT:    #APP
 ; SKX-NEXT:    fnop # sched: [1:0.50]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retl # sched: [6:0.50]
 ;
 ; BTVER2-LABEL: test_fnop:
 ; BTVER2:       # %bb.0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    fnop # sched: [100:0.50]
+; BTVER2-NEXT:    fnop # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retl # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_fnop:
 ; ZNVER1:       # %bb.0:
 ; ZNVER1-NEXT:    #APP
 ; ZNVER1-NEXT:    fnop # sched: [1:1.00]
 ; ZNVER1-NEXT:    #NO_APP