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Fix for DAGCombiner infinite loop in AMDGPU OCLtst
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Authored by alex-t on Mar 13 2018, 4:37 AM.

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Summary

Some SelectionDAG methods use raw bits to create the ID for CSE map.
We need to exclude isDivergent bit from that raw representation to avoid creating new node each time we want to change it's properties.

For example this bug was caused by creating new node in DAGCombiner when it attempted to change node alignment.
It happened because we do not use divergence bit creating the hash for the node to put it in the CSE map. Same time for MemSDNode raw bits were used to create CSE map ID.
Thus we cannot identify the existing node in the map because it was added w/o counting the divergence bit but was looking for counting this bit.
So we either should add the divergence bit to ID any time we creating the node or exclude it from the raw bits representation.
The latter seems easier.

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rL LLVM

Event Timeline

alex-t created this revision.Mar 13 2018, 4:37 AM
rampitec accepted this revision.Mar 13 2018, 9:26 AM

I guess that is impossible to have two nodes which only differ by this bit. LGTM.

This revision is now accepted and ready to land.Mar 13 2018, 9:26 AM
This revision was automatically updated to reflect the committed changes.