[x86] Introduce the pconfig/encl[u|s|v] intrinsics

[GBuella]

Summary

Introduce pconfig and SGX related intrinsics.

[GBuella]

Rebased the patch.
Added pconfig to Icelake Server.

[craig.topper]

I see that gcc implements all of this with wrappers around inline assembly. Any reason we couldn't just do that?

lib/Headers/pconfigintrin.h

31

This doesn't match the name used by gcc. It also needs to start with underscores since all names without underscores belong to user code.

lib/Headers/sgxintrin.h

52

You need to undef __DEFAULT_FN_ATTRS

[craig.topper]

lib/Headers/pconfigintrin.h

28

I think all our other headers use double underscore here.

lib/Headers/sgxintrin.h

28

double underscore

[craig.topper]

I didn't see an answer to the inline assembly question.

lib/Headers/pconfigintrin.h

31

Gcc's constant is called __PCONFIG_KEY_PROGRAM from what I see in their repository

[GBuella]

Here is a variation on this, using inline asm:

pconfig: https://reviews.llvm.org/D46431

SGX: https://reviews.llvm.org/D46435

[vsapsai]

I see you've ended up implementing the intrinsics with inline assembly but are there any reasons not to do it with builtins like in this patch? The problem with inline assembly is that for some Apple platforms we require developers to emit bitcode. And inline assembly isn't really compatible with bitcode abstraction. Unfortunately, I have no experience with Intel intrinsics and I need your help in pursuing implementing them with builtins.

[craig.topper]

The main reason that we used inline assembly is due to the fixed register allocation for these instructions. We would have had to write out the register rules in the backend as a special case as seen in the getInstrWFourImplicitOps in https://reviews.llvm.org/D44386 Since the register allocator had no freedom there was no performance advantage to an intrinsic. So we just did inline assembly to avoid needing to special case these instructions.

[vsapsai]

Thanks for the insightful explanation, Craig. As far as I understand, implementing intrinsics with builtins is possible but it is more complex and wasn't providing enough value to prefer it over inline assembly. If that is correct, I'd like to revive the abandoned implementation. Does it sound reasonable? And do I need to do something special for testing? Because I don't have access to corresponding hardware and unable to test the intrinsics on the actual hardware.

[craig.topper]

Your understanding is correct. As far as testing I think the existing testing in the original patches is sufficient.

I'm not sure I understand how a target specific intrinsic that only works on x86 in the bitcode is substantially better than inline assembly. Do you plan to also change the cpuid intrinsics in cpuid.h that are also implemented in inline assembly?

[vsapsai]

Having in bitcode something like @llvm.x86.encls.64 is better than inline assembly because we understand the meaning of the bitcode while we don't parse assembly and have a very limited understanding of what it is doing.

The use case we need to support is basically

--- a/clang/test/Modules/compiler_builtins_x86.c
+++ b/clang/test/Modules/compiler_builtins_x86.c
@@ -1,6 +1,7 @@
 // RUN: rm -rf %t
 // RUN: %clang_cc1 -triple i686-unknown-unknown -fsyntax-only -fmodules -fimplicit-module-maps -fmodules-cache-path=%t %s -verify -ffreestanding
 // RUN: %clang_cc1 -triple i686-unknown-unknown -fsyntax-only -fmodules -fmodule-map-file=%resource_dir/module.modulemap -fmodules-cache-path=%t %s -verify -ffreestanding
+// RUN: %clang_cc1 -triple i686-unknown-unknown -fsyntax-only -fmodules -fimplicit-module-maps -fmodules-cache-path=%t %s -verify -ffreestanding -fno-gnu-inline-asm
 // expected-no-diagnostics
 
 #include<x86intrin.h>

And this case isn't affected by cpuid, so we don't plan to change that as well as Windows-specific assembly in immintrin.h.

While writing the response, it occurred to me that another solution might be changing -fno-gnu-inline-asm to cover only actually called code. If you don't call _pconfig_u32, it shouldn't matter that in the header it is implemented with inline assembly. But this is an early idea, I need to discuss with the team if it will work and if there are other constraints I'm missing.

[vsapsai]

Discussed with the team different approaches and suggesting https://reviews.llvm.org/D61621

include/clang/Basic/BuiltinsX86.def

 TARGET_BUILTIN(__builtin_ia32_tpause, "UcUiUiUi", "", "waitpkg")
 
 // CLZERO
 TARGET_BUILTIN(__builtin_ia32_clzero, "vv*", "", "clzero")
 
 // CLDEMOTE
 TARGET_BUILTIN(__builtin_ia32_cldemote, "vvC*", "", "cldemote")
 
+// PCONFIG
+TARGET_BUILTIN(__builtin_ia32_pconfig, "UiUiz*z*z*", "", "pconfig")
+
+// SGX
+TARGET_BUILTIN(__builtin_ia32_enclu, "UiUiz*z*z*", "", "sgx")
+TARGET_BUILTIN(__builtin_ia32_encls, "UiUiz*z*z*", "", "sgx")
+TARGET_BUILTIN(__builtin_ia32_enclv, "UiUiz*z*z*", "", "sgx")
+
 // MSVC
 TARGET_HEADER_BUILTIN(_BitScanForward, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_BitScanReverse, "UcUNi*UNi", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 
 TARGET_HEADER_BUILTIN(_ReadWriteBarrier, "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_ReadBarrier,      "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 TARGET_HEADER_BUILTIN(_WriteBarrier,     "v", "nh", "intrin.h", ALL_MS_LANGUAGES, "")
 

include/clang/Driver/Options.td

 def mmpx : Flag<["-"], "mmpx">, Group<m_x86_Features_Group>;
 def mno_mpx : Flag<["-"], "mno-mpx">, Group<m_x86_Features_Group>;
 def mmwaitx : Flag<["-"], "mmwaitx">, Group<m_x86_Features_Group>;
 def mno_mwaitx : Flag<["-"], "mno-mwaitx">, Group<m_x86_Features_Group>;
 def mpku : Flag<["-"], "mpku">, Group<m_x86_Features_Group>;
 def mno_pku : Flag<["-"], "mno-pku">, Group<m_x86_Features_Group>;
 def mpclmul : Flag<["-"], "mpclmul">, Group<m_x86_Features_Group>;
 def mno_pclmul : Flag<["-"], "mno-pclmul">, Group<m_x86_Features_Group>;
+def mpconfig : Flag<["-"], "mpconfig">, Group<m_x86_Features_Group>;
+def mno_pconfig : Flag<["-"], "mno-pconfig">, Group<m_x86_Features_Group>;
 def mpopcnt : Flag<["-"], "mpopcnt">, Group<m_x86_Features_Group>;
 def mno_popcnt : Flag<["-"], "mno-popcnt">, Group<m_x86_Features_Group>;
 def mprefetchwt1 : Flag<["-"], "mprefetchwt1">, Group<m_x86_Features_Group>;
 def mno_prefetchwt1 : Flag<["-"], "mno-prefetchwt1">, Group<m_x86_Features_Group>;
 def mprfchw : Flag<["-"], "mprfchw">, Group<m_x86_Features_Group>;
 def mno_prfchw : Flag<["-"], "mno-prfchw">, Group<m_x86_Features_Group>;
 def mrdpid : Flag<["-"], "mrdpid">, Group<m_x86_Features_Group>;
 def mno_rdpid : Flag<["-"], "mno-rdpid">, Group<m_x86_Features_Group>;

lib/Basic/Targets/X86.h

class LLVM_LIBRARY_VISIBILITY X86TargetInfo : public TargetInfo {
   bool HasFXSR = false;
   bool HasXSAVE = false;
   bool HasXSAVEOPT = false;
   bool HasXSAVEC = false;
   bool HasXSAVES = false;
   bool HasMWAITX = false;
   bool HasCLZERO = false;
   bool HasCLDEMOTE = false;
+  bool HasPCONFIG = false;
   bool HasPKU = false;
   bool HasCLFLUSHOPT = false;
   bool HasCLWB = false;
   bool HasMOVBE = false;
   bool HasPREFETCHWT1 = false;
   bool HasRDPID = false;
   bool HasRetpoline = false;
   bool HasRetpolineExternalThunk = false;

lib/Basic/Targets/X86.cpp

bool X86TargetInfo::initFeatureMap(
   case CK_PentiumMMX:
   case CK_Pentium2:
   case CK_K6:
   case CK_WinChipC6:
     setFeatureEnabledImpl(Features, "mmx", true);
     break;
 
   case CK_IcelakeServer:
+    setFeatureEnabledImpl(Features, "pconfig", true);
     setFeatureEnabledImpl(Features, "wbnoinvd", true);
     LLVM_FALLTHROUGH;
   case CK_IcelakeClient:
     setFeatureEnabledImpl(Features, "vaes", true);
     setFeatureEnabledImpl(Features, "gfni", true);
     setFeatureEnabledImpl(Features, "vpclmulqdq", true);
     setFeatureEnabledImpl(Features, "avx512bitalg", true);
     setFeatureEnabledImpl(Features, "avx512vnni", true);
for (const auto &Feature : Features) {
     } else if (Feature == "+retpoline") {
       HasRetpoline = true;
     } else if (Feature == "+retpoline-external-thunk") {
       HasRetpolineExternalThunk = true;
     } else if (Feature == "+sahf") {
       HasLAHFSAHF = true;
     } else if (Feature == "+waitpkg") {
       HasWAITPKG = true;
+    } else if (Feature == "+pconfig") {
+      HasPCONFIG = true;
     }
 
     X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature)
                            .Case("+avx512f", AVX512F)
                            .Case("+avx2", AVX2)
                            .Case("+avx", AVX)
                            .Case("+sse4.2", SSE42)
                            .Case("+sse4.1", SSE41)
void X86TargetInfo::getTargetDefines(const LangOptions &Opts,
   if (HasCLZERO)
     Builder.defineMacro("__CLZERO__");
   if (HasRDPID)
     Builder.defineMacro("__RDPID__");
   if (HasCLDEMOTE)
     Builder.defineMacro("__CLDEMOTE__");
   if (HasWAITPKG)
     Builder.defineMacro("__WAITPKG__");
+  if (HasPCONFIG)
+    Builder.defineMacro("__PCONFIG__");
 
   // Each case falls through to the previous one here.
   switch (SSELevel) {
   case AVX512F:
     Builder.defineMacro("__AVX512F__");
     LLVM_FALLTHROUGH;
   case AVX2:
     Builder.defineMacro("__AVX2__");
return llvm::StringSwitch<bool>(Name)
       .Case("gfni", true)
       .Case("lwp", true)
       .Case("lzcnt", true)
       .Case("mmx", true)
       .Case("movbe", true)
       .Case("mpx", true)
       .Case("mwaitx", true)
       .Case("pclmul", true)
+      .Case("pconfig", true)
       .Case("pku", true)
       .Case("popcnt", true)
       .Case("prefetchwt1", true)
       .Case("prfchw", true)
       .Case("rdpid", true)
       .Case("rdrnd", true)
       .Case("rdseed", true)
       .Case("rtm", true)
return llvm::StringSwitch<bool>(Feature)
       .Case("lzcnt", HasLZCNT)
       .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow)
       .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon)
       .Case("mmx", MMX3DNowLevel >= MMX)
       .Case("movbe", HasMOVBE)
       .Case("mpx", HasMPX)
       .Case("mwaitx", HasMWAITX)
       .Case("pclmul", HasPCLMUL)
+      .Case("pconfig", HasPCONFIG)
       .Case("pku", HasPKU)
       .Case("popcnt", HasPOPCNT)
       .Case("prefetchwt1", HasPREFETCHWT1)
       .Case("prfchw", HasPRFCHW)
       .Case("rdpid", HasRDPID)
       .Case("rdrnd", HasRDRND)
       .Case("rdseed", HasRDSEED)
       .Case("retpoline", HasRetpoline)

lib/CodeGen/CGBuiltin.cpp

case X86::BI__builtin_ia32_rdseed64_step:
       break;
     }
 
     Value *Call = Builder.CreateCall(CGM.getIntrinsic(ID));
     Builder.CreateDefaultAlignedStore(Builder.CreateExtractValue(Call, 0),
                                       Ops[0]);
     return Builder.CreateExtractValue(Call, 1);
   }
+  case X86::BI__builtin_ia32_enclu:
+  case X86::BI__builtin_ia32_encls:
+  case X86::BI__builtin_ia32_enclv:
+  case X86::BI__builtin_ia32_pconfig: {
+    Intrinsic::ID ID;
+
+    if (IntPtrTy->getBitWidth() == 64) {
+      switch (BuiltinID) {
+      default: llvm_unreachable("Unsupported intrinsic!");
+      case X86::BI__builtin_ia32_enclu:
+        ID = Intrinsic::x86_enclu_64;
+        break;
+      case X86::BI__builtin_ia32_encls:
+        ID = Intrinsic::x86_encls_64;
+        break;
+      case X86::BI__builtin_ia32_enclv:
+        ID = Intrinsic::x86_enclv_64;
+        break;
+      case X86::BI__builtin_ia32_pconfig:
+        ID = Intrinsic::x86_pconfig_64;
+        break;
+      }
+    } else {
+      switch (BuiltinID) {
+      default: llvm_unreachable("Unsupported intrinsic!");
+      case X86::BI__builtin_ia32_enclu:
+        ID = Intrinsic::x86_enclu_32;
+        break;
+      case X86::BI__builtin_ia32_encls:
+        ID = Intrinsic::x86_encls_32;
+        break;
+      case X86::BI__builtin_ia32_enclv:
+        ID = Intrinsic::x86_enclv_32;
+        break;
+      case X86::BI__builtin_ia32_pconfig:
+        ID = Intrinsic::x86_pconfig_32;
+        break;
+      }
+    }
+
+    Value *Call = Builder.CreateCall(CGM.getIntrinsic(ID),
+                   {Ops[0],
+                   Builder.CreateLoad(EmitPointerWithAlignment(E->getArg(1))),
+                   Builder.CreateLoad(EmitPointerWithAlignment(E->getArg(2))),
+                   Builder.CreateLoad(EmitPointerWithAlignment(E->getArg(3)))});
+    Builder.CreateDefaultAlignedStore(Builder.CreateExtractValue(Call, 1),
+                                      Ops[1]);
+    Builder.CreateDefaultAlignedStore(Builder.CreateExtractValue(Call, 2),
+                                      Ops[2]);
+    Builder.CreateDefaultAlignedStore(Builder.CreateExtractValue(Call, 3),
+                                      Ops[3]);
+    return Builder.CreateExtractValue(Call, 0);
+  }
 
   case X86::BI__builtin_ia32_cmpps128_mask:
   case X86::BI__builtin_ia32_cmpps256_mask:
   case X86::BI__builtin_ia32_cmpps512_mask:
   case X86::BI__builtin_ia32_cmppd128_mask:
   case X86::BI__builtin_ia32_cmppd256_mask:
   case X86::BI__builtin_ia32_cmppd512_mask: {
     unsigned NumElts = Ops[0]->getType()->getVectorNumElements();

lib/Headers/CMakeLists.txt

set(files
   mm_malloc.h
   module.modulemap
   msa.h
   mwaitxintrin.h
   nmmintrin.h
   opencl-c.h
   pkuintrin.h
   pmmintrin.h
+  pconfigintrin.h
   popcntintrin.h
   prfchwintrin.h
   rdseedintrin.h
   rtmintrin.h
+  sgxintrin.h
   s390intrin.h
   shaintrin.h
   smmintrin.h
   stdalign.h
   stdarg.h
   stdatomic.h
   stdbool.h
   stddef.h

lib/Headers/cpuid.h

 #define bit_AVX512BITALG     0x00001000
 #define bit_AVX512VPOPCNTDQ  0x00004000
 #define bit_RDPID            0x00400000
 #define bit_CLDEMOTE         0x02000000
 
 /* Features in %edx for leaf 7 sub-leaf 0 */
 #define bit_AVX5124VNNIW  0x00000004
 #define bit_AVX5124FMAPS  0x00000008
+#define bit_PCONFIG       0x00040000
 #define bit_IBT           0x00100000
 
 /* Features in %eax for leaf 13 sub-leaf 1 */
 #define bit_XSAVEOPT    0x00000001
 #define bit_XSAVEC      0x00000002
 #define bit_XSAVES      0x00000008
 
 /* Features in %ecx for leaf 0x80000001 */

lib/Headers/module.modulemap

explicit module intel {
     header "x86intrin.h"
     textual header "bmiintrin.h"
     textual header "bmi2intrin.h"
     textual header "lzcntintrin.h"
     textual header "xopintrin.h"
     textual header "fma4intrin.h"
     textual header "mwaitxintrin.h"
     textual header "clzerointrin.h"
+    textual header "pconfigintrin.h"
 
     explicit module mm_malloc {
       requires !freestanding
       header "mm_malloc.h"
       export * // note: for <stdlib.h> dependency
     }
 
     explicit module cpuid {

lib/Headers/pconfigintrin.h

+/*===---- pconfigintrin.h - X86 platform configuration ---------------------===
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __X86INTRIN_H
+#error "Never use <pconfigintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef _PCONFIGINTRIN_H
+#define _PCONFIGINTRIN_H
+
+#define MKTME_KEY_PROGRAM 0x00000001
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __nodebug__,  __target__("pconfig")))
+
+static __inline unsigned int __DEFAULT_FN_ATTRS
+_pconfig_u32(unsigned int __leaf, __SIZE_TYPE__ __D[])
+{
+  return __builtin_ia32_pconfig(__leaf, __D, __D + 1, __D + 2);
+}
+
+#undef __DEFAULT_FN_ATTRS
+
+#endif

lib/Headers/sgxintrin.h

+/*===---- sgxintrin.h - X86 SGX intrinsics configuration -------------------===
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ *
+ *===-----------------------------------------------------------------------===
+ */
+
+#ifndef __X86INTRIN_H
+#error "Never use <sgxintrin.h> directly; include <x86intrin.h> instead."
+#endif
+
+#ifndef _SGXINTRIN_H
+#define _SGXINTRIN_H
+
+/* Define the default attributes for the functions in this file. */
+#define __DEFAULT_FN_ATTRS \
+  __attribute__((__always_inline__, __nodebug__,  __target__("sgx")))
+
+static __inline unsigned int __DEFAULT_FN_ATTRS
+_enclu_u32(unsigned int __leaf, __SIZE_TYPE__ __D[])
+{
+  return __builtin_ia32_enclu(__leaf, __D, __D + 1, __D + 2);
+}
+
+static __inline unsigned int __DEFAULT_FN_ATTRS
+_encls_u32(unsigned int __leaf, __SIZE_TYPE__ __D[])
+{
+  return __builtin_ia32_encls(__leaf, __D, __D + 1, __D + 2);
+}
+
+static __inline unsigned int __DEFAULT_FN_ATTRS
+_enclv_u32(unsigned int __leaf, __SIZE_TYPE__ __D[])
+{
+  return __builtin_ia32_enclv(__leaf, __D, __D + 1, __D + 2);
+}
+
+#endif

lib/Headers/x86intrin.h

 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__CLDEMOTE__)
 #include <cldemoteintrin.h>
 #endif
 
 #if !defined(_MSC_VER) || __has_feature(modules) || defined(__WAITPKG__)
 #include <waitpkgintrin.h>
 #endif
 
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__PCONFIG__)
+#include <pconfigintrin.h>
+#endif
+
+#if !defined(_MSC_VER) || __has_feature(modules) || defined(__SGX__)
+#include <sgxintrin.h>
+#endif
+
 #endif /* __X86INTRIN_H */

test/CodeGen/builtins-x86.c

-// RUN: %clang_cc1 -DUSE_64 -triple x86_64-unknown-unknown -target-feature +fxsr -target-feature +avx -target-feature +xsaveopt -target-feature +xsaves -target-feature +xsavec -target-feature +mwaitx -target-feature +clzero -target-feature +ibt -target-feature +shstk -target-feature +wbnoinvd -target-feature +cldemote -emit-llvm -o %t %s
-// RUN: %clang_cc1 -DUSE_ALL -triple x86_64-unknown-unknown -target-feature +fxsr -target-feature +avx -target-feature +xsaveopt -target-feature +xsaves -target-feature +xsavec -target-feature +mwaitx -target-feature +ibt -target-feature +shstk -target-feature +clzero -target-feature +wbnoinvd -target-feature +cldemote -fsyntax-only -o %t %s
+// RUN: %clang_cc1 -DUSE_64 -triple x86_64-unknown-unknown -target-feature +fxsr -target-feature +avx -target-feature +xsaveopt -target-feature +xsaves -target-feature +xsavec -target-feature +mwaitx -target-feature +clzero -target-feature +ibt -target-feature +shstk -target-feature +wbnoinvd -target-feature +cldemote -target-feature +pconfig -emit-llvm -o %t %s
+// RUN: %clang_cc1 -DUSE_ALL -triple x86_64-unknown-unknown -target-feature +fxsr -target-feature +avx -target-feature +xsaveopt -target-feature +xsaves -target-feature +xsavec -target-feature +mwaitx -target-feature +ibt -target-feature +shstk -target-feature +clzero -target-feature +wbnoinvd -target-feature +cldemote -target-feature +pconfig -fsyntax-only -o %t %s
 
 #ifdef USE_ALL
 #define USE_3DNOW
 #define USE_64
 #define USE_SSE4
 #endif
 
 // 64-bit
#endif
   (void)__builtin_ia32_xsavec64(tmp_vp, tmp_ULLi);
   (void)__builtin_ia32_xsaves(tmp_vp, tmp_ULLi);
   (void)__builtin_ia32_xsaves64(tmp_vp, tmp_ULLi);
 
   (void) __builtin_ia32_monitorx(tmp_vp, tmp_Ui, tmp_Ui);
   (void) __builtin_ia32_mwaitx(tmp_Ui, tmp_Ui, tmp_Ui);
   (void) __builtin_ia32_clzero(tmp_vp);
   (void) __builtin_ia32_cldemote(tmp_vp);
+  (void) __builtin_ia32_pconfig(1, (__SIZE_TYPE__*)tmp_vp,
+                                   ((__SIZE_TYPE__*)tmp_vp) + 1,
+                                   ((__SIZE_TYPE__*)tmp_vp) + 2);
 
   tmp_V4f = __builtin_ia32_cvtpi2ps(tmp_V4f, tmp_V2i);
   tmp_V2i = __builtin_ia32_cvtps2pi(tmp_V4f);
   tmp_i = __builtin_ia32_cvtss2si(tmp_V4f);
   tmp_i = __builtin_ia32_cvttss2si(tmp_V4f);
 
   tmp_i = __builtin_ia32_rdtsc();
   tmp_i = __rdtsc();

test/CodeGen/pconfig.c

+// RUN: %clang_cc1 %s -ffreestanding -triple x86_64-apple-darwin -emit-llvm -target-feature +pconfig -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-64
+// RUN: %clang_cc1 %s -ffreestanding -triple i386 -emit-llvm -target-feature +pconfig -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-32
+
+#include <stddef.h>
+
+#include <x86intrin.h>
+
+unsigned int test_pconfig(unsigned int leaf, size_t arguments[]) {
+  //CHECK-LABEL: @test_pconfig
+  //CHECK-64: @llvm.x86.pconfig.64
+  //CHECK-32: @llvm.x86.pconfig.32
+  return _pconfig_u32(leaf, arguments);
+}
+

test/CodeGen/sgx.c

+// RUN: %clang_cc1 %s -ffreestanding -triple x86_64-unknown-unknown -emit-llvm -target-feature +sgx -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-64
+// RUN: %clang_cc1 %s -ffreestanding -triple i386-unknown-unknown -emit-llvm -target-feature +sgx -o - | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-32
+
+#include <stddef.h>
+
+#include <x86intrin.h>
+
+unsigned int test_encls(unsigned int leaf, size_t arguments[]) {
+  //CHECK-LABEL: @test_encls
+  //CHECK-64: @llvm.x86.encls.64
+  //CHECK-32: @llvm.x86.encls.32
+  return _encls_u32(leaf, arguments);
+}
+
+unsigned int test_enclu(unsigned int leaf, size_t arguments[]) {
+  //CHECK-LABEL: @test_enclu
+  //CHECK-64: @llvm.x86.enclu.64
+  //CHECK-32: @llvm.x86.enclu.32
+  return _enclu_u32(leaf, arguments);
+}
+
+unsigned int test_enclv(unsigned int leaf, size_t arguments[]) {
+  //CHECK-LABEL: @test_enclv
+  //CHECK-64: @llvm.x86.enclv.64
+  //CHECK-32: @llvm.x86.enclv.32
+  return _enclv_u32(leaf, arguments);
+}

test/Driver/x86-target-features.c

 // RUN: %clang -target i386-linux-gnu -mretpoline -mno-retpoline-external-thunk %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-RETPOLINE-EXTERNAL-THUNK %s
 // RETPOLINE-EXTERNAL-THUNK: "-target-feature" "+retpoline-external-thunk"
 // NO-RETPOLINE-EXTERNAL-THUNK: "-target-feature" "-retpoline-external-thunk"
 
 // RUN: %clang -target i386-linux-gnu -mwaitpkg %s -### -o %t.o 2>&1 | FileCheck -check-prefix=WAITPKG %s
 // RUN: %clang -target i386-linux-gnu -mno-waitpkg %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-WAITPKG %s
 // WAITPKG: "-target-feature" "+waitpkg"
 // NO-WAITPKG: "-target-feature" "-waitpkg"
+
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mpconfig %s -### -o %t.o 2>&1 | FileCheck -check-prefix=PCONFIG %s
+// RUN: %clang -target i386-unknown-linux-gnu -march=i386 -mno-pconfig %s -### -o %t.o 2>&1 | FileCheck -check-prefix=NO-PCONFIG %s
+// PCONFIG: "-target-feature" "+pconfig"
+// NO-PCONFIG: "-target-feature" "-pconfig"

test/Preprocessor/predefined-arch-macros.c

 // CHECK_ICX_M32: #define __CLWB__ 1
 // CHECK_ICX_M32: #define __F16C__ 1
 // CHECK_ICX_M32: #define __FMA__ 1
 // CHECK_ICX_M32: #define __GFNI__ 1
 // CHECK_ICX_M32: #define __LZCNT__ 1
 // CHECK_ICX_M32: #define __MMX__ 1
 // CHECK_ICX_M32: #define __MPX__ 1
 // CHECK_ICX_M32: #define __PCLMUL__ 1
+// CHECK_ICX_M32: #define __PCONFIG__ 1
 // CHECK_ICX_M32: #define __PKU__ 1
 // CHECK_ICX_M32: #define __POPCNT__ 1
 // CHECK_ICX_M32: #define __PRFCHW__ 1
 // CHECK_ICX_M32: #define __RDPID__ 1
 // CHECK_ICX_M32: #define __RDRND__ 1
 // CHECK_ICX_M32: #define __RDSEED__ 1
 // CHECK_ICX_M32: #define __RTM__ 1
 // CHECK_ICX_M32: #define __SGX__ 1

 // CHECK_ICX_M64: #define __CLWB__ 1
 // CHECK_ICX_M64: #define __F16C__ 1
 // CHECK_ICX_M64: #define __FMA__ 1
 // CHECK_ICX_M64: #define __GFNI__ 1
 // CHECK_ICX_M64: #define __LZCNT__ 1
 // CHECK_ICX_M64: #define __MMX__ 1
 // CHECK_ICX_M64: #define __MPX__ 1
 // CHECK_ICX_M64: #define __PCLMUL__ 1
+// CHECK_ICX_M64: #define __PCONFIG__ 1
 // CHECK_ICX_M64: #define __PKU__ 1
 // CHECK_ICX_M64: #define __POPCNT__ 1
 // CHECK_ICX_M64: #define __PRFCHW__ 1
 // CHECK_ICX_M64: #define __RDPID__ 1
 // CHECK_ICX_M64: #define __RDRND__ 1
 // CHECK_ICX_M64: #define __RDSEED__ 1
 // CHECK_ICX_M64: #define __RTM__ 1
 // CHECK_ICX_M64: #define __SGX__ 1