[x86] Introduce the pconfig/enclv instructions

[GBuella]

Summary

Two new instructions: pconfig and enclv. Four new LLVM
intrinsics for pconfig and for encl[u|s|v].

[craig.topper]

lib/Support/Host.cpp

1275

Did you mean -march=native?

lib/Target/X86/X86ISelLowering.cpp

21174

Variable names should be uppercase.

lib/Target/X86/X86ISelLowering.h

567 ↗

(On Diff #138010)

These aren't used by your patch since you selected the machine node directly.

lib/Target/X86/X86IntrinsicsInfo.h

337 ↗

(On Diff #138010)

You're not really using the X86ISD opcodes listed in the table here. You're probably better off not putting these in the table and putting the intrinsics in the earlier switch that's used when the table doesn't have an entry. The one that handles Intrinsic::x86_lwpins64

utils/TableGen/X86RecognizableInstr.cpp

681 ↗

(On Diff #138010)

We should just add all of C8-FF into this switch. They are all defined not sure why they aren't already here. I'll go ahead and do that ahead of this patch.

[GBuella]

utils/TableGen/X86RecognizableInstr.cpp

681 ↗

(On Diff #138010)

Thanks, I rebased it on top of your change.

[GBuella]

Rebased the patch.
Added pconfig to Icelake Server.

include/llvm/IR/IntrinsicsX86.td

 let TargetPrefix = "x86" in {
   def int_x86_umonitor : GCCBuiltin<"__builtin_ia32_umonitor">,
               Intrinsic<[], [llvm_ptr_ty], []>;
   def int_x86_umwait : GCCBuiltin<"__builtin_ia32_umwait">,
               Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
   def int_x86_tpause : GCCBuiltin<"__builtin_ia32_tpause">,
               Intrinsic<[llvm_i8_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
 }
+
+//===----------------------------------------------------------------------===//
+// Platform Configuration
+let TargetPrefix = "x86" in {
+  def int_x86_pconfig_32 :
+      Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+                [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
+  def int_x86_pconfig_64 :
+      Intrinsic<[llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
+                [llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], []>;
+}
+
+//===----------------------------------------------------------------------===//
+// SGX Intrinsics
+let TargetPrefix = "x86" in {
+  def int_x86_encls_32 :
+      Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+                [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
+  def int_x86_encls_64 :
+      Intrinsic<[llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
+                [llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], []>;
+  def int_x86_enclu_32 :
+      Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+                [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
+  def int_x86_enclu_64 :
+      Intrinsic<[llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
+                [llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], []>;
+  def int_x86_enclv_32 :
+      Intrinsic<[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
+                [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
+  def int_x86_enclv_64 :
+      Intrinsic<[llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty],
+                [llvm_i32_ty, llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], []>;
+}

lib/Support/Host.cpp

bool sys::getHostCPUFeatures(StringMap<bool> &Features) {
   Features["avx512vnni"]      = HasLeaf7 && ((ECX >> 11) & 1) && HasAVX512Save;
   Features["avx512bitalg"]    = HasLeaf7 && ((ECX >> 12) & 1) && HasAVX512Save;
   Features["avx512vpopcntdq"] = HasLeaf7 && ((ECX >> 14) & 1) && HasAVX512Save;
   Features["rdpid"]           = HasLeaf7 && ((ECX >> 22) & 1);
   Features["cldemote"]        = HasLeaf7 && ((ECX >> 25) & 1);
 
   Features["ibt"] = HasLeaf7 && ((EDX >> 20) & 1);
 
+  // There are two CPUID leafs which information associated with the pconfig
+  // instruction:
+  // EAX=0x7, ECX=0x0 indicates the availability of the instruction (via the 18th
+  // bit of EDX), while the EAX=0x1b leaf returns information on the
+  // availability of specific pconfig leafs.
+  // The target feature here only refers to the the first of these two.
+  // Users might need to check for the availability of specific pconfig
+  // leaves using cpuid, since that information is ignored while
+  // detecting features using the "-march=native" flag.
+  // For more info, see X86 ISA docs.
+  Features["pconfig"] = HasLeaf7 && ((EDX >> 18) & 1);
+
   bool HasLeafD = MaxLevel >= 0xd &&
                   !getX86CpuIDAndInfoEx(0xd, 0x1, &EAX, &EBX, &ECX, &EDX);
 
   // Only enable XSAVE if OS has enabled support for saving YMM state.
   Features["xsaveopt"] = HasLeafD && ((EAX >> 0) & 1) && HasAVXSave;
   Features["xsavec"]   = HasLeafD && ((EAX >> 1) & 1) && HasAVXSave;
   Features["xsaves"]   = HasLeafD && ((EAX >> 3) & 1) && HasAVXSave;
 

lib/Target/X86/X86.td

def FeatureSoftFloat
     : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
                        "Use software floating point features.">;
 def FeaturePOPCNTFalseDeps : SubtargetFeature<"false-deps-popcnt",
                                      "HasPOPCNTFalseDeps", "true",
                                      "POPCNT has a false dependency on dest register">;
 def FeatureLZCNTFalseDeps : SubtargetFeature<"false-deps-lzcnt-tzcnt",
                                      "HasLZCNTFalseDeps", "true",
                                      "LZCNT/TZCNT have a false dependency on dest register">;
+def FeaturePCONFIG : SubtargetFeature<"pconfig", "HasPCONFIG", "true",
+                                      "platform configuration instruction">;
 // On recent X86 (port bound) processors, its preferable to combine to a single shuffle
 // using a variable mask over multiple fixed shuffles.
 def FeatureFastVariableShuffle
     : SubtargetFeature<"fast-variable-shuffle",
                        "HasFastVariableShuffle",
                        "true", "Shuffles with variable masks are fast">;
 // On some X86 processors, there is no performance hazard to writing only the
 // lower parts of a YMM or ZMM register without clearing the upper part.
class IcelakeClientProc<string Name> : ProcModel<Name, SkylakeServerModel,
   ProcIntelICL,
   FeatureHasFastGather
 ]>;
 def : IcelakeClientProc<"icelake-client">;
 
 class IcelakeServerProc<string Name> : ProcModel<Name, SkylakeServerModel,
                                                  ICLFeatures.Value, [
   ProcIntelICX,
+  FeaturePCONFIG,
   FeatureWBNOINVD,
   FeatureHasFastGather
 ]>;
 def : IcelakeServerProc<"icelake-server">;
 
 // AMD CPUs.
 
 def : Proc<"k6",              [FeatureX87, FeatureSlowUAMem16, FeatureMMX]>;

lib/Target/X86/X86ISelLowering.cpp

static SDValue getPrefetchNode(unsigned Opc, SDValue Op, SelectionDAG &DAG,
   MVT MaskVT =
     MVT::getVectorVT(MVT::i1, Index.getSimpleValueType().getVectorNumElements());
   SDValue VMask = getMaskNode(Mask, MaskVT, Subtarget, DAG, dl);
   SDValue Ops[] = {VMask, Base, Scale, Index, Disp, Segment, Chain};
   SDNode *Res = DAG.getMachineNode(Opc, dl, MVT::Other, Ops);
   return SDValue(Res, 0);
 }
 
+static SDValue getInstrWFourImplicitOps(SDValue Op, SelectionDAG &DAG,
+                                        const X86Subtarget &Subtarget,
+                                        unsigned Opcode) {
+  SDLoc DL(Op);
+  SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
+  SDValue Chain = Op.getOperand(0);
+  unsigned ArgReg1 = Subtarget.is64Bit() ? X86::RBX : X86::EBX;
+  unsigned ArgReg2 = Subtarget.is64Bit() ? X86::RCX : X86::ECX;
+  unsigned ArgReg3 = Subtarget.is64Bit() ? X86::RDX : X86::EDX;
+  auto ArgVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
+
+  Chain = DAG.getCopyToReg(Chain, DL, X86::EAX, Op->getOperand(2));
+  Chain = DAG.getCopyToReg(Chain, DL, ArgReg1, Op->getOperand(3));
+  Chain = DAG.getCopyToReg(Chain, DL, ArgReg2, Op->getOperand(4));
+  Chain = DAG.getCopyToReg(Chain, DL, ArgReg3, Op->getOperand(5));
+
+  SDNode *Res = DAG.getMachineNode(Opcode, DL, Tys, Chain);
+
+  SDValue A = DAG.getCopyFromReg(SDValue(Res, 0), DL, X86::EAX, MVT::i32, SDValue(Res, 1));
+  SDValue B = DAG.getCopyFromReg(A.getValue(1), DL, ArgReg1, ArgVT, A.getValue(2));
+  SDValue C = DAG.getCopyFromReg(B.getValue(1), DL, ArgReg2, ArgVT, B.getValue(2));
+  SDValue D = DAG.getCopyFromReg(C.getValue(1), DL, ArgReg3, ArgVT, C.getValue(2));
+
+  return DAG.getMergeValues({A, B, C, D, SDValue(Res, 0)}, DL);
+}
+
 /// Handles the lowering of builtin intrinsic that return the value
 /// of the extended control register.
 static void getExtendedControlRegister(SDNode *N, const SDLoc &DL,
                                        SelectionDAG &DAG,
                                        const X86Subtarget &Subtarget,
                                        SmallVectorImpl<SDValue> &Results) {
   assert(N->getNumOperands() == 3 && "Unexpected number of operands!");
   SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
case Intrinsic::x86_tpause: {
       SDValue Operation =
           DAG.getNode(Opcode, dl, VTs, Chain, Op->getOperand(2),
                       Op->getOperand(3), Op->getOperand(4));
       SDValue SetCC = getSETCC(X86::COND_B, Operation.getValue(0), dl, DAG);
       SDValue Result = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i8, SetCC);
       return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result,
                          Operation.getValue(1));
     }
+    case Intrinsic::x86_pconfig_32:
+    case Intrinsic::x86_pconfig_64:
+      return getInstrWFourImplicitOps(Op, DAG, Subtarget, X86::PCONFIG);
+    case Intrinsic::x86_encls_32:
+    case Intrinsic::x86_encls_64:
+      return getInstrWFourImplicitOps(Op, DAG, Subtarget, X86::ENCLS);
+    case Intrinsic::x86_enclu_32:
+    case Intrinsic::x86_enclu_64:
+      return getInstrWFourImplicitOps(Op, DAG, Subtarget, X86::ENCLU);
+    case Intrinsic::x86_enclv_32:
+    case Intrinsic::x86_enclv_64:
+      return getInstrWFourImplicitOps(Op, DAG, Subtarget, X86::ENCLV);
     }
     return SDValue();
   }
 
   SDLoc dl(Op);
   switch(IntrData->Type) {
   default: llvm_unreachable("Unknown Intrinsic Type");
   case RDSEED:

lib/Target/X86/X86InstrInfo.td

 def HasBMI2      : Predicate<"Subtarget->hasBMI2()">;
 def NoBMI2       : Predicate<"!Subtarget->hasBMI2()">;
 def HasVBMI      : Predicate<"Subtarget->hasVBMI()">;
 def HasVBMI2     : Predicate<"Subtarget->hasVBMI2()">;
 def HasIFMA      : Predicate<"Subtarget->hasIFMA()">;
 def HasRTM       : Predicate<"Subtarget->hasRTM()">;
 def HasADX       : Predicate<"Subtarget->hasADX()">;
 def HasSHA       : Predicate<"Subtarget->hasSHA()">;
+def HasSGX       : Predicate<"Subtarget->hasSGX()">;
 def HasPRFCHW    : Predicate<"Subtarget->hasPRFCHW()">;
 def HasRDSEED    : Predicate<"Subtarget->hasRDSEED()">;
 def HasSSEPrefetch : Predicate<"Subtarget->hasSSEPrefetch()">;
 def NoSSEPrefetch : Predicate<"!Subtarget->hasSSEPrefetch()">;
 def HasPrefetchW : Predicate<"Subtarget->hasPRFCHW()">;
 def HasPREFETCHWT1 : Predicate<"Subtarget->hasPREFETCHWT1()">;
 def HasLAHFSAHF  : Predicate<"Subtarget->hasLAHFSAHF()">;
 def HasMWAITX    : Predicate<"Subtarget->hasMWAITX()">;
 def HasCLZERO    : Predicate<"Subtarget->hasCLZERO()">;
 def HasCLDEMOTE  : Predicate<"Subtarget->hasCLDEMOTE()">;
 def FPStackf32   : Predicate<"!Subtarget->hasSSE1()">;
 def FPStackf64   : Predicate<"!Subtarget->hasSSE2()">;
 def HasMPX       : Predicate<"Subtarget->hasMPX()">;
 def HasSHSTK     : Predicate<"Subtarget->hasSHSTK()">;
 def HasIBT       : Predicate<"Subtarget->hasIBT()">;
 def HasCLFLUSHOPT : Predicate<"Subtarget->hasCLFLUSHOPT()">;
 def HasCLWB      : Predicate<"Subtarget->hasCLWB()">;
 def HasWBNOINVD  : Predicate<"Subtarget->hasWBNOINVD()">;
 def HasRDPID     : Predicate<"Subtarget->hasRDPID()">;
 def HasWAITPKG   : Predicate<"Subtarget->hasWAITPKG()">;
 def HasCmpxchg16b: Predicate<"Subtarget->hasCmpxchg16b()">;
+def HasPCONFIG   : Predicate<"Subtarget->hasPCONFIG()">;
 def Not64BitMode : Predicate<"!Subtarget->is64Bit()">,
                              AssemblerPredicate<"!Mode64Bit", "Not 64-bit mode">;
 def In64BitMode  : Predicate<"Subtarget->is64Bit()">,
                              AssemblerPredicate<"Mode64Bit", "64-bit mode">;
 def IsLP64  : Predicate<"Subtarget->isTarget64BitLP64()">;
 def NotLP64 : Predicate<"!Subtarget->isTarget64BitLP64()">;
 def In16BitMode  : Predicate<"Subtarget->is16Bit()">,
                              AssemblerPredicate<"Mode16Bit", "16-bit mode">;

lib/Target/X86/X86InstrSGX.td

 // This file describes the instructions that make up the Intel SGX instruction
 // set.
 //
 //===----------------------------------------------------------------------===//
 
 //===----------------------------------------------------------------------===//
 // SGX instructions
 
-let SchedRW = [WriteSystem] in {
+let SchedRW = [WriteSystem], Predicates = [HasSGX] in {
 // ENCLS - Execute an Enclave System Function of Specified Leaf Number
 def ENCLS : I<0x01, MRM_CF, (outs), (ins),
              "encls", []>, TB;
 
 // ENCLU - Execute an Enclave User Function of Specified Leaf Number
 def ENCLU : I<0x01, MRM_D7, (outs), (ins),
              "enclu", []>, TB;
+
+// ENCLV - Execute an Enclave VMM Function of Specified Leaf Number
+def ENCLV : I<0x01, MRM_C0, (outs), (ins),
+             "enclv", []>, TB;
 } // SchedRW

lib/Target/X86/X86InstrSystem.td

 def PTWRITE64m : RI<0xAE, MRM4m, (outs), (ins i64mem:$dst),
                     "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
 
 def PTWRITEr : I<0xAE, MRM4r, (outs), (ins GR32:$dst),
                  "ptwrite{l}\t$dst", []>, XS;
 def PTWRITE64r : RI<0xAE, MRM4r, (outs), (ins GR64:$dst),
                     "ptwrite{q}\t$dst", []>, XS, Requires<[In64BitMode]>;
 } // SchedRW
+
+//===----------------------------------------------------------------------===//
+// Platform Configuration instruction
+
+// From ISA docs:
+//  "This instruction is used to execute functions for configuring platform
+//   features.
+//   EAX: Leaf function to be invoked.
+//   RBX/RCX/RDX: Leaf-specific purpose."
+//  "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
+//   AF, OF, and SF are cleared. In case of failure, the failure reason is
+//   indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
+// Thus all these mentioned registers are considered clobbered.
+
+let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX, RDX, EFLAGS] in
+    def PCONFIG : I<0x01, MRM_C5, (outs), (ins), "pconfig", []>, TB,
+                  Requires<[HasPCONFIG]>;

lib/Target/X86/X86Subtarget.h

protected:
   bool HasWBNOINVD;
 
   /// Processor support RDPID instruction
   bool HasRDPID;
 
   /// Processor supports WaitPKG instructions
   bool HasWAITPKG;
 
+  /// Processor supports PCONFIG instruction
+  bool HasPCONFIG;
+
   /// Use a retpoline thunk rather than indirect calls to block speculative
   /// execution.
   bool UseRetpoline;
 
   /// When using a retpoline thunk, call an externally provided thunk rather
   /// than emitting one inside the compiler.
   bool UseRetpolineExternalThunk;
 
public:
   bool hasMPX() const { return HasMPX; }
   bool hasSHSTK() const { return HasSHSTK; }
   bool hasIBT() const { return HasIBT; }
   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
   bool hasCLWB() const { return HasCLWB; }
   bool hasWBNOINVD() const { return HasWBNOINVD; }
   bool hasRDPID() const { return HasRDPID; }
   bool hasWAITPKG() const { return HasWAITPKG; }
+  bool hasPCONFIG() const { return HasPCONFIG; }
+  bool hasSGX() const { return HasSGX; }
   bool useRetpoline() const { return UseRetpoline; }
   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
 
   unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
   unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
 
   // Helper functions to determine when we should allow widening to 512-bit
   // during codegen.

lib/Target/X86/X86Subtarget.cpp

void X86Subtarget::initializeEnvironment() {
   HasLAHFSAHF = false;
   HasMWAITX = false;
   HasCLZERO = false;
   HasCLDEMOTE = false;
   HasMPX = false;
   HasSHSTK = false;
   HasIBT = false;
   HasSGX = false;
+  HasPCONFIG = false;
   HasCLFLUSHOPT = false;
   HasCLWB = false;
   HasWBNOINVD = false;
   HasRDPID = false;
   HasWAITPKG = false;
   UseRetpoline = false;
   UseRetpolineExternalThunk = false;
   IsPMULLDSlow = false;

test/CodeGen/X86/SGX32-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sgx | FileCheck %s
+
+; Function Attrs: nounwind
+define i32 @test_encls(i32 %leaf, i32* nocapture %d) local_unnamed_addr #0 {
+; CHECK-LABEL: test_encls:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    .cfi_offset %esi, -12
+; CHECK-NEXT:    .cfi_offset %ebx, -8
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl (%esi), %ebx
+; CHECK-NEXT:    movl 4(%esi), %ecx
+; CHECK-NEXT:    movl 8(%esi), %edx
+; CHECK-NEXT:    encls
+; CHECK-NEXT:    movl %ebx, (%esi)
+; CHECK-NEXT:    movl %ecx, 4(%esi)
+; CHECK-NEXT:    movl %edx, 8(%esi)
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
+entry:
+  %add.ptr.i = getelementptr inbounds i32, i32* %d, i32 1
+  %add.ptr1.i = getelementptr inbounds i32, i32* %d, i32 2
+  %0 = load i32, i32* %d, align 4
+  %1 = load i32, i32* %add.ptr.i, align 4
+  %2 = load i32, i32* %add.ptr1.i, align 4
+  %3 = tail call { i32, i32, i32, i32 } @llvm.x86.encls.32(i32 %leaf, i32 %0, i32 %1, i32 %2) #1
+  %4 = extractvalue { i32, i32, i32, i32 } %3, 1
+  store i32 %4, i32* %d, align 4
+  %5 = extractvalue { i32, i32, i32, i32 } %3, 2
+  store i32 %5, i32* %add.ptr.i, align 4
+  %6 = extractvalue { i32, i32, i32, i32 } %3, 3
+  store i32 %6, i32* %add.ptr1.i, align 4
+  %7 = extractvalue { i32, i32, i32, i32 } %3, 0
+  ret i32 %7
+}
+
+declare { i32, i32, i32, i32 } @llvm.x86.encls.32(i32, i32, i32, i32) #1
+
+; Function Attrs: nounwind
+define i32 @test_enclu(i32 %leaf, i32* nocapture %d) local_unnamed_addr #0 {
+; CHECK-LABEL: test_enclu:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    .cfi_offset %esi, -12
+; CHECK-NEXT:    .cfi_offset %ebx, -8
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl (%esi), %ebx
+; CHECK-NEXT:    movl 4(%esi), %ecx
+; CHECK-NEXT:    movl 8(%esi), %edx
+; CHECK-NEXT:    enclu
+; CHECK-NEXT:    movl %ebx, (%esi)
+; CHECK-NEXT:    movl %ecx, 4(%esi)
+; CHECK-NEXT:    movl %edx, 8(%esi)
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
+entry:
+  %add.ptr.i = getelementptr inbounds i32, i32* %d, i32 1
+  %add.ptr1.i = getelementptr inbounds i32, i32* %d, i32 2
+  %0 = load i32, i32* %d, align 4
+  %1 = load i32, i32* %add.ptr.i, align 4
+  %2 = load i32, i32* %add.ptr1.i, align 4
+  %3 = tail call { i32, i32, i32, i32 } @llvm.x86.enclu.32(i32 %leaf, i32 %0, i32 %1, i32 %2) #1
+  %4 = extractvalue { i32, i32, i32, i32 } %3, 1
+  store i32 %4, i32* %d, align 4
+  %5 = extractvalue { i32, i32, i32, i32 } %3, 2
+  store i32 %5, i32* %add.ptr.i, align 4
+  %6 = extractvalue { i32, i32, i32, i32 } %3, 3
+  store i32 %6, i32* %add.ptr1.i, align 4
+  %7 = extractvalue { i32, i32, i32, i32 } %3, 0
+  ret i32 %7
+}
+
+declare { i32, i32, i32, i32 } @llvm.x86.enclu.32(i32, i32, i32, i32) #1
+
+; Function Attrs: nounwind
+define i32 @test_enclv(i32 %leaf, i32* nocapture %d) local_unnamed_addr #0 {
+; CHECK-LABEL: test_enclv:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    .cfi_offset %esi, -12
+; CHECK-NEXT:    .cfi_offset %ebx, -8
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl (%esi), %ebx
+; CHECK-NEXT:    movl 4(%esi), %ecx
+; CHECK-NEXT:    movl 8(%esi), %edx
+; CHECK-NEXT:    enclv
+; CHECK-NEXT:    movl %ebx, (%esi)
+; CHECK-NEXT:    movl %ecx, 4(%esi)
+; CHECK-NEXT:    movl %edx, 8(%esi)
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
+entry:
+  %add.ptr.i = getelementptr inbounds i32, i32* %d, i32 1
+  %add.ptr1.i = getelementptr inbounds i32, i32* %d, i32 2
+  %0 = load i32, i32* %d, align 4
+  %1 = load i32, i32* %add.ptr.i, align 4
+  %2 = load i32, i32* %add.ptr1.i, align 4
+  %3 = tail call { i32, i32, i32, i32 } @llvm.x86.enclv.32(i32 %leaf, i32 %0, i32 %1, i32 %2) #1
+  %4 = extractvalue { i32, i32, i32, i32 } %3, 1
+  store i32 %4, i32* %d, align 4
+  %5 = extractvalue { i32, i32, i32, i32 } %3, 2
+  store i32 %5, i32* %add.ptr.i, align 4
+  %6 = extractvalue { i32, i32, i32, i32 } %3, 3
+  store i32 %6, i32* %add.ptr1.i, align 4
+  %7 = extractvalue { i32, i32, i32, i32 } %3, 0
+  ret i32 %7
+}
+
+declare { i32, i32, i32, i32 } @llvm.x86.enclv.32(i32, i32, i32, i32) #1

test/CodeGen/X86/SGX64-intrinsics.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sgx | FileCheck %s
+
+define i32 @test_encls(i32 %leaf, i64* nocapture %arguments) local_unnamed_addr #0 {
+; CHECK-LABEL: test_encls:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq (%rsi), %rbx
+; CHECK-NEXT:    movq 8(%rsi), %rcx
+; CHECK-NEXT:    movq 16(%rsi), %rdx
+; CHECK-NEXT:    encls
+; CHECK-NEXT:    movq %rbx, (%rsi)
+; CHECK-NEXT:    movq %rcx, 8(%rsi)
+; CHECK-NEXT:    movq %rdx, 16(%rsi)
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %add.ptr.i = getelementptr inbounds i64, i64* %arguments, i64 1
+  %add.ptr1.i = getelementptr inbounds i64, i64* %arguments, i64 2
+  %0 = load i64, i64* %arguments, align 8
+  %1 = load i64, i64* %add.ptr.i, align 8
+  %2 = load i64, i64* %add.ptr1.i, align 8
+  %3 = tail call { i32, i64, i64, i64 } @llvm.x86.encls.64(i32 %leaf, i64 %0, i64 %1, i64 %2) #1
+  %4 = extractvalue { i32, i64, i64, i64 } %3, 1
+  store i64 %4, i64* %arguments, align 8
+  %5 = extractvalue { i32, i64, i64, i64 } %3, 2
+  store i64 %5, i64* %add.ptr.i, align 8
+  %6 = extractvalue { i32, i64, i64, i64 } %3, 3
+  store i64 %6, i64* %add.ptr1.i, align 8
+  %7 = extractvalue { i32, i64, i64, i64 } %3, 0
+  ret i32 %7
+}
+
+; Function Attrs: nounwind
+define i32 @test_enclu(i32 %leaf, i64* nocapture %arguments) local_unnamed_addr #0 {
+; CHECK-LABEL: test_enclu:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq (%rsi), %rbx
+; CHECK-NEXT:    movq 8(%rsi), %rcx
+; CHECK-NEXT:    movq 16(%rsi), %rdx
+; CHECK-NEXT:    enclu
+; CHECK-NEXT:    movq %rbx, (%rsi)
+; CHECK-NEXT:    movq %rcx, 8(%rsi)
+; CHECK-NEXT:    movq %rdx, 16(%rsi)
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %add.ptr.i = getelementptr inbounds i64, i64* %arguments, i64 1
+  %add.ptr1.i = getelementptr inbounds i64, i64* %arguments, i64 2
+  %0 = load i64, i64* %arguments, align 8
+  %1 = load i64, i64* %add.ptr.i, align 8
+  %2 = load i64, i64* %add.ptr1.i, align 8
+  %3 = tail call { i32, i64, i64, i64 } @llvm.x86.enclu.64(i32 %leaf, i64 %0, i64 %1, i64 %2) #1
+  %4 = extractvalue { i32, i64, i64, i64 } %3, 1
+  store i64 %4, i64* %arguments, align 8
+  %5 = extractvalue { i32, i64, i64, i64 } %3, 2
+  store i64 %5, i64* %add.ptr.i, align 8
+  %6 = extractvalue { i32, i64, i64, i64 } %3, 3
+  store i64 %6, i64* %add.ptr1.i, align 8
+  %7 = extractvalue { i32, i64, i64, i64 } %3, 0
+  ret i32 %7
+}
+
+define i32 @test_enclv(i32 %leaf, i64* nocapture %arguments) local_unnamed_addr #0 {
+; CHECK-LABEL: test_enclv:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq (%rsi), %rbx
+; CHECK-NEXT:    movq 8(%rsi), %rcx
+; CHECK-NEXT:    movq 16(%rsi), %rdx
+; CHECK-NEXT:    enclv
+; CHECK-NEXT:    movq %rbx, (%rsi)
+; CHECK-NEXT:    movq %rcx, 8(%rsi)
+; CHECK-NEXT:    movq %rdx, 16(%rsi)
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %add.ptr.i = getelementptr inbounds i64, i64* %arguments, i64 1
+  %add.ptr1.i = getelementptr inbounds i64, i64* %arguments, i64 2
+  %0 = load i64, i64* %arguments, align 8
+  %1 = load i64, i64* %add.ptr.i, align 8
+  %2 = load i64, i64* %add.ptr1.i, align 8
+  %3 = tail call { i32, i64, i64, i64 } @llvm.x86.enclv.64(i32 %leaf, i64 %0, i64 %1, i64 %2) #1
+  %4 = extractvalue { i32, i64, i64, i64 } %3, 1
+  store i64 %4, i64* %arguments, align 8
+  %5 = extractvalue { i32, i64, i64, i64 } %3, 2
+  store i64 %5, i64* %add.ptr.i, align 8
+  %6 = extractvalue { i32, i64, i64, i64 } %3, 3
+  store i64 %6, i64* %add.ptr1.i, align 8
+  %7 = extractvalue { i32, i64, i64, i64 } %3, 0
+  ret i32 %7
+}
+
+declare { i32, i64, i64, i64 } @llvm.x86.encls.64(i32, i64, i64, i64) #1
+declare { i32, i64, i64, i64 } @llvm.x86.enclu.64(i32, i64, i64, i64) #1
+declare { i32, i64, i64, i64 } @llvm.x86.enclv.64(i32, i64, i64, i64) #1

test/CodeGen/X86/pconfig32-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+pconfig | FileCheck %s
+
+; Function Attrs: nounwind
+define i32 @test_pconfig(i32 %leaf, i32* nocapture %d) local_unnamed_addr #0 {
+; CHECK-LABEL: test_pconfig:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    pushl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 12
+; CHECK-NEXT:    .cfi_offset %esi, -12
+; CHECK-NEXT:    .cfi_offset %ebx, -8
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
+; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %esi
+; CHECK-NEXT:    movl (%esi), %ebx
+; CHECK-NEXT:    movl 4(%esi), %ecx
+; CHECK-NEXT:    movl 8(%esi), %edx
+; CHECK-NEXT:    # kill: def $eax killed $eax def $rax
+; CHECK-NEXT:    # kill: def $ebx killed $ebx def $rbx
+; CHECK-NEXT:    # kill: def $ecx killed $ecx def $rcx
+; CHECK-NEXT:    # kill: def $edx killed $edx def $rdx
+; CHECK-NEXT:    pconfig
+; CHECK-NEXT:    movl %ebx, (%esi)
+; CHECK-NEXT:    movl %ecx, 4(%esi)
+; CHECK-NEXT:    movl %edx, 8(%esi)
+; CHECK-NEXT:    popl %esi
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    popl %ebx
+; CHECK-NEXT:    .cfi_def_cfa_offset 4
+; CHECK-NEXT:    retl
+entry:
+  %add.ptr.i = getelementptr inbounds i32, i32* %d, i32 1
+  %add.ptr1.i = getelementptr inbounds i32, i32* %d, i32 2
+  %0 = load i32, i32* %d, align 4
+  %1 = load i32, i32* %add.ptr.i, align 4
+  %2 = load i32, i32* %add.ptr1.i, align 4
+  %3 = tail call { i32, i32, i32, i32 } @llvm.x86.pconfig.32(i32 %leaf, i32 %0, i32 %1, i32 %2) #1
+  %4 = extractvalue { i32, i32, i32, i32 } %3, 1
+  store i32 %4, i32* %d, align 4
+  %5 = extractvalue { i32, i32, i32, i32 } %3, 2
+  store i32 %5, i32* %add.ptr.i, align 4
+  %6 = extractvalue { i32, i32, i32, i32 } %3, 3
+  store i32 %6, i32* %add.ptr1.i, align 4
+  %7 = extractvalue { i32, i32, i32, i32 } %3, 0
+  ret i32 %7
+}
+
+; Function Attrs: nounwind
+declare { i32, i32, i32, i32 } @llvm.x86.pconfig.32(i32, i32, i32, i32) #1

test/CodeGen/X86/pconfig64-intrinsic.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+pconfig | FileCheck %s
+
+; Function Attrs: nounwind
+define i32 @test_pconfig(i32 %leaf, i64* nocapture %d) local_unnamed_addr #0 {
+; CHECK-LABEL: test_pconfig:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    pushq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 16
+; CHECK-NEXT:    .cfi_offset %rbx, -16
+; CHECK-NEXT:    movq (%rsi), %rbx
+; CHECK-NEXT:    movq 8(%rsi), %rcx
+; CHECK-NEXT:    movq 16(%rsi), %rdx
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    pconfig
+; CHECK-NEXT:    movq %rbx, (%rsi)
+; CHECK-NEXT:    movq %rcx, 8(%rsi)
+; CHECK-NEXT:    movq %rdx, 16(%rsi)
+; CHECK-NEXT:    popq %rbx
+; CHECK-NEXT:    .cfi_def_cfa_offset 8
+; CHECK-NEXT:    retq
+entry:
+  %add.ptr.i = getelementptr inbounds i64, i64* %d, i64 1
+  %add.ptr1.i = getelementptr inbounds i64, i64* %d, i64 2
+  %0 = load i64, i64* %d, align 8
+  %1 = load i64, i64* %add.ptr.i, align 8
+  %2 = load i64, i64* %add.ptr1.i, align 8
+  %3 = tail call { i32, i64, i64, i64 } @llvm.x86.pconfig.64(i32 %leaf, i64 %0, i64 %1, i64 %2) #1
+  %4 = extractvalue { i32, i64, i64, i64 } %3, 1
+  store i64 %4, i64* %d, align 8
+  %5 = extractvalue { i32, i64, i64, i64 } %3, 2
+  store i64 %5, i64* %add.ptr.i, align 8
+  %6 = extractvalue { i32, i64, i64, i64 } %3, 3
+  store i64 %6, i64* %add.ptr1.i, align 8
+  %7 = extractvalue { i32, i64, i64, i64 } %3, 0
+  ret i32 %7
+}
+
+; Function Attrs: nounwind
+declare { i32, i64, i64, i64 } @llvm.x86.pconfig.64(i32, i64, i64, i64) #1

test/MC/X86/sgx-encoding.s

 // RUN: llvm-mc -triple x86_64-unknown-unknown --show-encoding %s | FileCheck %s
 
 // CHECK: encls
 // CHECK: encoding: [0x0f,0x01,0xcf]
   encls
 
 // CHECK: enclu
 // CHECK: encoding: [0x0f,0x01,0xd7]
   enclu
+
+// CHECK: enclv
+// CHECK: encoding: [0x0f,0x01,0xc0]
+  enclv

test/MC/X86/x86-32-coverage.s

 
 // CHECK: umwait %eax
 // CHECK:  encoding: [0xf2,0x0f,0xae,0xf0]
   umwait %eax
 
 // CHECK: tpause %eax
 // CHECK:  encoding: [0x66,0x0f,0xae,0xf0]
   tpause %eax
+
+// CHECK: pconfig
+// CHECK:  encoding: [0x0f,0x01,0xc5]
+  pconfig

test/MC/X86/x86-64.s

 // CHECK: tpause %r15
 // CHECK:  encoding: [0x66,0x41,0x0f,0xae,0xf7]
 tpause %r15
 
 // CHECK: tpause %ebx
 // CHECK:  encoding: [0x66,0x0f,0xae,0xf3]
 tpause %ebx
 
+// CHECK: pconfig
+// CHECK:  encoding: [0x0f,0x01,0xc5]
+pconfig
+
 //  __asm __volatile(
 //    "pushf        \n\t"
 //    "popf       \n\t"
 //    "rep        \n\t"
 //    ".byte  0x0f, 0xa7, 0xd0"
 //  );
 // CHECK: pushfq
 // CHECK-NEXT: popfq