[Power9] Add missing instructions to the Power 9 scheduler

[stefanp]

Summary

In light of patch D43235 we realized that not all of the instructions available for use on Power 9 have resources defined for the scheduler.

This is the first in a series of patches that will define more instructions using InstRW so that we can move away from ItinRW and ultimately have a complete Power 9 scheduler.

[echristo]

TIL we accept regexes here.

I'm doubtful on a testcase, but... got a testcase? :)

[stefanp]

I also learned that we accept regexes here when I started doing this a couple of days ago. :)

Unfortunately, I don't have a test case that I was working with.
The issue with scheduling test cases is that they are like this today and then different tomorrow (when I add even more instructions to try to complete this model).
Still, I can try to cook one up for some of the instructions that have been added.

[echristo]

Nah, don't worry about it. Thanks :)

llvm/trunk/lib/Target/PowerPC/P9InstrResources.td

 //===----------------------------------------------------------------------===//
 
 // Two cycle ALU vector operation that uses an entire superslice.
 //  Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
 //  (EXECE, EXECO) and all three dispatches (DISP) to the given superslice.
 def : InstRW<[P9_ALUE_2C, P9_ALUO_2C, IP_EXECE_1C, IP_EXECO_1C,
               DISP_1C, DISP_1C, DISP_1C],
       (instrs
+    (instregex "VADDU(B|H|W|D)M$"),
     VADDCUW,
-    VADDUBM,
-    VADDUDM,
-    VADDUHM,
-    VADDUWM,
     VAND,
     VANDC,
     VCMPEQUB,
     VCMPEQUD,
     VCMPEQUH,
     VCMPEQUW,
     VCMPNEB,
     VCMPNEH,

 // Restricted Dispatch ALU operation for 3 cycles. The operation runs on a
 //  slingle slice. However, since it is Restricted it requires all 3 dispatches
 //  (DISP) for that superslice.
 def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     FCMPUS,
     FCMPUD,
     XSTSTDCDP,
-    XSTSTDCSP
+    XSTSTDCSP,
+    FTDIV,
+    FTSQRT,
+    (instregex "CMPRB(8)?$"),
+    (instregex "TD(I)?$"),
+    (instregex "TW(I)?$")
 )>;
 
 // Standard Dispatch ALU operation for 3 cycles. Only one slice used.
 def : InstRW<[P9_ALU_3C, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
-    XSMAXCDP,
-    XSMAXDP,
-    XSMAXJDP,
-    XSMINCDP,
-    XSMINDP,
-    XSMINJDP,
+    (instregex "XSMAX(C|J)?DP$"),
+    (instregex "XSMIN(C|J)?DP$"),
+    (instregex "XSCMP(EQ|EXP|GE|GT|O|U)DP$"),
     XSTDIVDP,
     XSTSQRTDP,
-    XSCMPEQDP,
-    XSCMPEXPDP,
-    XSCMPGEDP,
-    XSCMPGTDP,
-    XSCMPODP,
-    XSCMPUDP,
     XSXSIGDP,
-    XSCVSPDPN
+    XSCVSPDPN,
+    SETB,
+    BPERMD,
+    (instregex "CNT(L|T)Z(D|W)(8)?$"),
+    (instregex "POPCNT(D|W)$"),
+    (instregex "CMPB(8)?$")
 )>;
 
 // Standard Dispatch ALU operation for 2 cycles. Only one slice used.
 def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C],
       (instrs
     ADDIStocHA,
     ADDItocL,
     MCRF,
     MCRXRX,
-    SLD,
-    SRD,
-    SRAD,
-    SRADI,
-    RLDIC,
     XSNABSDP,
     XSXEXPDP,
     XSABSDP,
     XSNEGDP,
-    XSCPSGNDP
+    XSCPSGNDP,
+    (instregex "S(L|R)D$"),
+    (instregex "SRAD(I)?$"),
+    (instregex "EXTSWSLI$"),
+    SRADI_32,
+    RLDIC,
+    ADDIC,
+    ADDICo,
+    LA,
+    (instregex "CMP(WI|LWI|W|LW)(8)?$"),
+    (instregex "SUBF(I)?C(8)?$"),
+    (instregex "ANDI(S)?o(8)?$"),
+    (instregex "ADD(I)?C(8)?(o)?$"),
+    (instregex "ADD(E|ME|ZE)(8)?$"),
+    (instregex "SUBF(E|ME|ZE)?(8)?$"),
+    (instregex "NEG(8)?$"),
+    (instregex "POPCNTB$"),
+    (instregex "ADD(I|IS)?(8)?$"),
+    (instregex "LI(S)?(8)?$"),
+    (instregex "(X)?OR(I|IS)?(8)?$"),
+    NOP,
+    (instregex "NAND(8)?$"),
+    (instregex "AND(C)?(8)?$"),
+    (instregex "NOR(8)?$"),
+    (instregex "OR(C)?(8)?$"),
+    (instregex "EQV(8)?$"),
+    (instregex "EXTS(B|H)(8)?$"),
+    (instregex "ADD(4|8)(TLS)?(_)?$"),
+    (instregex "NEG(8)?$")
 )>;
 
 // Restricted Dispatch ALU operation for 2 cycles. The operation runs on a
 //  slingle slice. However, since it is Restricted it requires all 3 dispatches
 //  (DISP) for that superslice.
 def : InstRW<[P9_ALU_2C, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     RLDCL,
     RLDCR,
     RLDIMI,
     RLDICL,
     RLDICR,
     RLDICL_32_64,
+    RLDICL_32,
+    RLDICR_32,
+    (instregex "RLWIMI(8)?$"),
     XSIEXPDP,
     FMR,
-    FABSD,
-    FABSS,
-    FNABSD,
-    FNABSS,
-    FNEGD,
-    FNEGS,
-    FCPSGND,
-    FCPSGNS
+    (instregex "S(L|R)W(8)?$"),
+    (instregex "RLW(INM|NM)(8)?$"),
+    (instregex "F(N)?ABS(D|S)$"),
+    (instregex "FNEG(D|S)$"),
+    (instregex "FCPSGN(D|S)$"),
+    (instregex "SRAW(I)?$"),
+    (instregex "ISEL(8)?$")
 )>;
 
 // Three cycle ALU vector operation that uses an entire superslice.
 //  Uses both ALU units (the even ALUE and odd ALUO units), two pipelines
 //  (EXECE, EXECO) and all three dispatches (DISP) to the given superslice.
 def : InstRW<[P9_ALUE_3C, P9_ALUO_3C, IP_EXECE_1C, IP_EXECO_1C,
               DISP_1C, DISP_1C, DISP_1C],
       (instrs
def : InstRW<[P9_LS_5C, IP_AGEN_1C, DISP_1C, DISP_1C],
       (instrs
     LXSDX,
     LXVD2X,
     LXSIWZX,
     LXV,
     LXVX,
     LXSD,
     DFLOADf64,
-    XFLOADf64
+    XFLOADf64,
+    LIWZX
 )>;
 
 // 4 Cycle load uses a single slice.
 def : InstRW<[P9_LS_4C, IP_AGEN_1C, DISP_1C, DISP_1C],
       (instrs
     COPY
 )>;
 

 def : InstRW<[P9_LoadAndALUOp_7C, IP_AGEN_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     LXSSPX,
     LXSIWAX,
     LXSSP,
     DFLOADf32,
     XFLOADf32,
-    LIWAX,
-    LIWZX
+    LIWAX
 )>;
 
 // Cracked Load that requires the PM resource.
 // Since the Load and the PM cannot be done at the same time the latencies are
 //  added. Requires 8 cycles.
 // Since the PM requires the full superslice we need both EXECE, EXECO pipelines
 //  as well as 3 dispatches for the PM. The Load requires the remaining 2
 //  dispatches.
 def : InstRW<[P9_LoadAndPMOp_8C, IP_AGEN_1C, IP_EXECE_1C, IP_EXECO_1C,
               DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     LXVDSX,
     LXVWSX,
     LXVW4X
 )>;
 
 // Single slice Restricted store operation. The restricted operation requires
 //  all three dispatches for the superslice.
 def : InstRW<[P9_LS_1C, IP_EXEC_1C, IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
-    STFS,
-    STFD,
-    STFIWX,
-    STFSX,
-    STFDX,
-    STXSDX,
-    STXSSPX,
-    STXSIWX,
+    (instregex "STF(S|D|IWX|SX|DX)$"),
+    (instregex "STXS(DX|SPX|IWX)$"),
     DFSTOREf32,
     DFSTOREf64,
     XFSTOREf32,
     XFSTOREf64,
     STIWX
 )>;
 
 // Store operation that requires the whole superslice.
 def : InstRW<[P9_LS_1C, IP_EXECE_1C, IP_EXECO_1C, IP_AGEN_1C,
               DISP_1C, DISP_1C, DISP_1C],
       (instrs
     STXVD2X,
     STXVW4X
 )>;
 
+// Cracked instruction made up up two restriced stores.
+def : InstRW<[P9_LS_1C, P9_LS_1C, IP_EXEC_1C, IP_EXEC_1C, IP_AGEN_1C,
+              IP_AGEN_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
+      (instrs
+      STFDEPX
+)>;
+
+// 12 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
+// superslice. That includes both exec pipelines (EXECO, EXECE) and all three
+// dispatches.
+def : InstRW<[P9_DIV_12C, IP_EXECE_1C, IP_EXECO_1C, DISP_1C, DISP_1C, DISP_1C],
+      (instrs
+    (instregex "M(T|F)VRSAVE(v)?$")
+)>;
 
 // 16 Cycle DIV operation. Only one DIV unit per superslice so we use the whole
 //  superslice. That includes both exec pipelines (EXECO, EXECE) and all three
 //  dispatches.
 def : InstRW<[P9_DIV_16C_8, IP_EXECO_1C, IP_EXECE_1C,
               DISP_1C, DISP_1C, DISP_1C],
       (instrs
     DIVW,

 //  instructions running together on two pipelines and 6 dispatches.
 // ALU ops are 3 cycles each.
 def : InstRW<[P9_ALU_3C, P9_ALU_3C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     MCRFS
 )>;
 
+def : InstRW<[P9_ALUOpAndALUOp_4C, IP_EXEC_1C, IP_EXEC_1C,
+              DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
+      (instrs
+    RLWINMo
+)>;
+
 // FP Div instructions in IIC_FPDivD and IIC_FPDivS.
 
 // 33 Cycle DP Instruction Restricted. Takes one slice and 3 dispatches.
 def : InstRW<[P9_DP_33C_8, IP_EXEC_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
     FDIV
 )>;
 

 // Both the load and the ALU that depends on it are restricted and so they take
 //  a total of 6 dispatches. The final 2 dispatches come from the second ALU op.
 // The two EXEC pipelines are for the 2 ALUs while the AGEN is for the load.
 def : InstRW<[P9_LoadAndALUOp_6C, P9_ALU_2C,
               IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C, DISP_1C, DISP_1C,
               DISP_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
-    LFSU,
-    LFSUX
+    (instregex "LF(SU|SUX)$")
+)>;
+
+// Cracked instruction made up of a Store and an ALU. The ALU does not depend on
+// the store and so it can be run at the same time as the store. The store is
+// also restricted.
+def : InstRW<[P9_LS_1C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C, IP_EXEC_1C,
+              DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
+      (instrs
+    (instregex "STF(SU|SUX|DU|DUX)$")
 )>;
 
 // Cracked instruction made up of a Load and an ALU. The ALU does not depend on
 //  the load and so it can be run at the same time as the load. The load is also
 //  restricted. 3 dispatches are from the restricted load while the other two
 //  are from the ALU. The AGEN pipeline is from the load and the EXEC pipeline
 //  is required for the ALU.
 def : InstRW<[P9_LS_4C, P9_ALU_2C, IP_AGEN_1C, IP_EXEC_1C,
               DISP_1C, DISP_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
-    LFDU,
-    LFDUX
+    (instregex "LF(DU|DUX)$")
 )>;
 
 // Crypto Instructions
 
 // 6 Cycle CY operation. Only one CY unit per CPU so we use a whole
 //  superslice. That includes both exec pipelines (EXECO, EXECE) and all three
 //  dispatches.
 def : InstRW<[P9_CY_6C, IP_EXECO_1C, IP_EXECE_1C, DISP_1C, DISP_1C, DISP_1C],
       (instrs
   VPMSUMB,
   VPMSUMD,
   VPMSUMH,
   VPMSUMW,
   VCIPHER,
   VCIPHERLAST,
   VNCIPHER,
   VNCIPHERLAST,
   VSBOX
 )>;
+
+// Instructions without scheduling support.
+def : InstRW<[],
+    (instrs
+  (instregex "(H)?RFI(D)?$")
+)> { let Unsupported = 1; }