[ARM]Decoding MSR with unpredictable destination register causes an assert

[simpal01]

Summary

This patch handling:

1. Enable parsing of raw encodings of system registers .
2. Allows UNPREDICTABLE sysregs to be decoded to a raw number in the same way that disasslib does, rather than llvm crashing.
3. Disassemble msr/mrs with unpredictable sysregs as SoftFail.
4. Fix regression due to SoftFailing some encodings.

Patch by Chris Ryder

[olista01]

Hi Simi,

Could you re-upload this with more context (git diff -U999999)?

[simpal01]

Reuploaded the diff with more context

[javed.absar]

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

4247

Shouldn't this be 0xFF as that's what you checked one line up?

[simpal01]

@javed.absar Thanks Javed. I have made the changes according to your comments.

ChangeLog:

• Changed 0xFFF to 0xFF

lib/Target/ARM/AsmParser/ARMAsmParser.cpp

   MCAsmParser &Parser = getParser();
   SMLoc S = Parser.getTok().getLoc();
   const AsmToken &Tok = Parser.getTok();
+
+  if (Tok.is(AsmToken::Integer)) {
+    int64_t Val = Tok.getIntVal();
+    if (Val > 255 || Val < 0) {
+      return MatchOperand_NoMatch;
+    }
+    unsigned SYSmvalue = Val & 0xFFF;
+    Parser.Lex(); 
+    Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
+    return MatchOperand_Success;
+  }
+
   if (!Tok.is(AsmToken::Identifier))
     return MatchOperand_NoMatch;
   StringRef Mask = Tok.getString();

lib/Target/ARM/Disassembler/ARMDisassembler.cpp

     case 0x8a: // msplim_ns
     case 0x8b: // psplim_ns
     case 0x91: // basepri_ns
-    case 0x92: // basepri_max_ns
     case 0x93: // faultmask_ns
       if (!(FeatureBits[ARM::HasV8MMainlineOps]))
         return MCDisassembler::Fail;

         return MCDisassembler::Fail;
       break;
     default:
-      return MCDisassembler::Fail;
+      // Architecturally defined as unpredictable
+      S = MCDisassembler::SoftFail;
+      break;
     }
 
     if (Inst.getOpcode() == ARM::t2MSR_M) {

lib/Target/ARM/InstPrinter/ARMInstPrinter.cpp

       return;
     }
 
-    llvm_unreachable("Unexpected mask value!");
+    O << SYSm; 
+
     return;
   }
 

test/MC/ARM/thumbv8m.s

 // CHECK-MAINLINE: msr faultmask_ns, lr  @ encoding: [0x8e,0xf3,0x93,0x88]
 // UNDEF-BASELINE: error: invalid operand for instruction
 
+// Unpredictable SYSm's
+MRS r8, 146
+// CHECK: mrs r8, 146 @ encoding: [0xef,0xf3,0x92,0x88]
+MSR 146, r8
+// CHECK: msr 146, r8 @ encoding: [0x88,0xf3,0x92,0x80]
+
 // Invalid operand tests
 // UNDEF: error: too many operands for instruction
 // UNDEF:     sg #0

test/MC/Disassembler/ARM/invalid-thumb-MSR-MClass.txt

-# RUN: not llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
-# RUN: not llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
+# RUN: llvm-mc -disassemble %s -triple=thumbv7em 2>&1 | FileCheck %s
+# RUN: llvm-mc -disassemble %s -triple=thumbv7m 2>&1 | FileCheck --check-prefix=CHECK --check-prefix=CHECK-V7M %s
 
 #------------------------------------------------------------------------------
 # Undefined encodings for mrs

 #------------------------------------------------------------------------------
 
 # invalid SYSm
-# CHECK: warning: invalid instruction encoding
+# CHECK: warning: potentially undefined instruction encoding
 # CHECK-NEXT: [0xef 0xf3 0x80 0x80]
 [0xef 0xf3 0x80 0x80]
 

 [0x80 0xf3 0x00 0x84]
 
 # invalid SYSm
-# CHECK: warning: invalid instruction encoding
+# CHECK: warning: potentially undefined instruction encoding
 # CHECK-NEXT: [0x80 0xf3 0x80 0x88]
 [0x80 0xf3 0x80 0x88]