[CodeGen] Don't omit any redundant information in -debug output

[thegameg]

Summary

In r322867, we introduced IsStandalone when printing MIR in -debug output. The default behaviour for that was:

1. If any of MBB, MI, or MO are -debug-printed separately, don't omit any redundant information.
2. When -debug-printing a MF entirely, don't print any redundant information.
3. When printing MIR, don't print any redundant information.

I'd like to change 2) to: 2) When -debug-printing a MF entirely, don't omit any redundant information.

[MatzeB]

Printing different things depending on whether asserts are enabled feels strange. Can you explain the motivation here?

[thegameg]

In D43337#1009040, @MatzeB wrote:

Printing different things depending on whether asserts are enabled feels strange. Can you explain the motivation here?

I think we should be showing all the information we have (redundant reg classes, redundant successors, predecessors (always redundant)) in things like -print-after-all, or when calling MF.dump() from the debugger (basically, when we're actually debugging llvm). Also, this can be too verbose to have when calling MF.print() for testing or other purposes.
I'm basically trying to come up with an implicit -simplify-mir for MF.print().

I guess if we don't really care about having MF.print() being too verbose, we could always assume IsStandalone is true except for MIR printing.

[MatzeB]

In D43337#1009059, @thegameg wrote:

In D43337#1009040, @MatzeB wrote:

Printing different things depending on whether asserts are enabled feels strange. Can you explain the motivation here?

I think we should be showing all the information we have (redundant reg classes, redundant successors, predecessors (always redundant)) in things like -print-after-all, or when calling MF.dump() from the debugger (basically, when we're actually debugging llvm). Also, this can be too verbose to have when calling MF.print() for testing or other purposes.
I'm basically trying to come up with an implicit -simplify-mir for MF.print().

I guess if we don't really care about having MF.print() being too verbose, we could always assume IsStandalone is true except for MIR printing.

Apparently you care about print() being more verbose (I didn't print too much from a debugger/print-after-all lately, so maybe I am just unaware that reducing information is annoying there).
I'd say go for that independently of the asserts then (but keep it reduced for MIR printing).

[thegameg]

Forget the asserts part.

[MatzeB]

LGTM

lib/CodeGen/MachineBasicBlock.cpp

void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
   OS << ":\n";
 
   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
   const MachineRegisterInfo &MRI = MF->getRegInfo();
   const TargetInstrInfo &TII = *getParent()->getSubtarget().getInstrInfo();
   bool HasLineAttributes = false;
 
   // Print the preds of this block according to the CFG.
-  if (!pred_empty()) {
+  if (!pred_empty() && IsStandalone) {
     if (Indexes) OS << '\t';
     // Don't indent(2), align with previous line attributes.
     OS << "; predecessors: ";
     for (auto I = pred_begin(), E = pred_end(); I != E; ++I) {
       if (I != pred_begin())
         OS << ", ";
       OS << printMBBReference(**I);
     }
for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
       if (I != succ_begin())
         OS << ", ";
       OS << printMBBReference(**I);
       if (!Probs.empty())
         OS << '('
            << format("0x%08" PRIx32, getSuccProbability(I).getNumerator())
            << ')';
     }
-    if (!Probs.empty()) {
+    if (!Probs.empty() && IsStandalone) {
       // Print human readable probabilities as comments.
       OS << "; ";
       for (auto I = succ_begin(), E = succ_end(); I != E; ++I) {
         const BranchProbability &BP = *getProbabilityIterator(I);
         if (I != succ_begin())
           OS << ", ";
         OS << printMBBReference(**I) << '('
            << format("%.2f%%",
for (const MachineInstr &MI : instrs()) {
     }
 
     OS << '\n';
   }
 
   if (IsInBundle)
     OS.indent(2) << "}\n";
 
-  if (IrrLoopHeaderWeight) {
+  if (IrrLoopHeaderWeight && IsStandalone) {
     if (Indexes) OS << '\t';
     OS.indent(2) << "; Irreducible loop header weight: "
                  << IrrLoopHeaderWeight.getValue() << '\n';
   }
 }
 
 void MachineBasicBlock::printAsOperand(raw_ostream &OS,
                                        bool /*PrintType*/) const {

lib/CodeGen/MachineFunction.cpp

if (RegInfo && !RegInfo->livein_empty()) {
     OS << '\n';
   }
 
   ModuleSlotTracker MST(getFunction().getParent());
   MST.incorporateFunction(getFunction());
   for (const auto &BB : *this) {
     OS << '\n';
     // If we print the whole function, don't print any verbose information,
-    // since that information is already present.
-    BB.print(OS, MST, Indexes, /*IsStandalone=*/false);
+    // since that information is already present. However, when asserts are
+    // enabled, print it all.
+    BB.print(OS, MST, Indexes,
+#ifndef NDEBUG
+             /*IsStandalone=*/true);
+#else
+             /*IsStandalone=*/false);
+#endif // NDEBUG
   }
 
   OS << "\n# End machine code for function " << getName() << ".\n\n";
 }
 
 namespace llvm {
 
   template<>

test/CodeGen/AArch64/tailcall_misched_graph.ll

 ; CHECK:  fi#-4: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-3: {{.*}} fixed, at location [SP]
 ; CHECK:  fi#-2: {{.*}} fixed, at location [SP+8]
 ; CHECK:  fi#-1: {{.*}} fixed, at location [SP]
 
 ; CHECK:  [[VRA:%.*]]:gpr64 = LDRXui %fixed-stack.3
 ; CHECK:  [[VRB:%.*]]:gpr64 = LDRXui %fixed-stack.2
 ; CHECK:  STRXui %{{.*}}, %fixed-stack.0
-; CHECK:  STRXui [[VRB]], %fixed-stack.1
+; CHECK:  STRXui [[VRB]]{{[^,]*}}, %fixed-stack.1
 
 ; Make sure that there is an dependence edge between fi#-2 and fi#-4.
 ; Without this edge the scheduler would be free to move the store accross the load.
 
 ; CHECK: SU({{.*}}):   [[VRB]]:gpr64 = LDRXui %fixed-stack.2
 ; CHECK-NOT: SU
 ; CHECK:  Successors:
 ; CHECK:   SU([[DEPSTOREB:.*]]): Ord  Latency=0
 ; CHECK:   SU([[DEPSTOREA:.*]]): Ord  Latency=0
 
 ; CHECK: SU([[DEPSTOREA]]):   STRXui %{{.*}}, %fixed-stack.0
 ; CHECK: SU([[DEPSTOREB]]):   STRXui %{{.*}}, %fixed-stack.1

test/CodeGen/ARM/Windows/dbzchk.ll

 ; CHECK-CFG-DAG: %bb.0
 ; CHECK-CFG-DAG: t2Bcc %bb.2
 ; CHECK-CFG-DAG: t2B %bb.1
 
 ; CHECK-CFG-DAG: %bb.1
 ; CHECK-CFG-DAG: t2B %bb.3
 
 ; CHECK-CFG-DAG: %bb.2
-; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}, 0
+; CHECK-CFG-DAG: tCMPi8 %{{[0-9]}}{{[^,]*}}, 0
 ; CHECK-CFG-DAG: t2Bcc %bb.5
 
 ; CHECK-CFG-DAG: %bb.4
 
 ; CHECK-CFG-DAG: %bb.3
 ; CHECK-CFG-DAG: tBX_RET
 
 ; CHECK-CFG-DAG: %bb.5

test/CodeGen/Hexagon/post-inc-aa-metadata.ll

 ; RUN: llc -march=hexagon -debug-only=isel < %s 2>&1 | FileCheck %s
 ; REQUIRES: asserts
 
 ; Check that the generated post-increment load has TBAA information.
 ; CHECK-LABEL: Machine code for function fred:
-; CHECK: = V6_vL32b_pi %{{[0-9]+}}, 64; mem:LD64[{{.*}}](tbaa=
+; CHECK: = V6_vL32b_pi %{{[0-9]+}}{{[^,]*}}, 64; mem:LD64[{{.*}}](tbaa=
 
 target triple = "hexagon"
 
 ; Function Attrs: norecurse nounwind
 define void @fred(<16 x i32>* nocapture %p, <16 x i32>* nocapture readonly %q, i32 %n) local_unnamed_addr #0 {
 entry:
   %tobool2 = icmp eq i32 %n, 0
   br i1 %tobool2, label %while.end, label %while.body

test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

foo:
   ret i32 1
 
 bar:
   ret i32 0
 }
 
 ; CHECK-LABEL: fn3
 define signext i32 @fn3(i32 %a) {
-; CHECK: ANDIo killed {{[%0-9]+}}, 10, implicit-def $cr0
+; CHECK: ANDIo killed {{[%0-9]+}}{{[^,]*}}, 10, implicit-def $cr0
 ; CHECK: [[CREG:[^, ]+]]:crrc = COPY $cr0
 ; CHECK: BCC 76, killed [[CREG]]
   %1 = and i32 %a, 10
   %2 = icmp ne i32 %1, 0
   br i1 %2, label %foo, label %bar
 
 foo:
   ret i32 1