[LLD] [COFF] Add support for ARM64 secrel relocations for add/load instructions

[mstorsjo]

Ping @ruiu

[ruiu]

COFF/Chunks.cpp

226–230

You should factor out this part of code.

233

Why do you need to check for Shift?

[mstorsjo]

COFF/Chunks.cpp

226–230

Ok, will do

233

When using these relocations, you'd normally use them in a pair with SECREL_HIGH12A plus SECREL_LOW12A/L. It's very much expected and ok that the actual section relative offset is larger than 12 bits, and only the truncated lower 12 bits go with the LOW12A/L relocations. For the HIGH12A relocation, there's no corresponding larger relocation that could be used to handle the rest, so if the code uses that relocation, and there's overflow when writing the high part of it, we have an issue.

Another way of writing the same would be to always check if the section relative offset is over 24 bits, regardless of which of these relocations are used.

[mstorsjo]

Factorized the initial part of calculating the section relative offset.

[ruiu]

LGTM

Hmm, factoring that common part out doesn't seem good as I anticipated. Free free to revert it and submit. I'll try to make some cleanup on that code if possible.

COFF/Chunks.cpp

 }
 
 static void add16(uint8_t *P, int16_t V) { write16le(P, read16le(P) + V); }
 static void add32(uint8_t *P, int32_t V) { write32le(P, read32le(P) + V); }
 static void add64(uint8_t *P, int64_t V) { write64le(P, read64le(P) + V); }
 static void or16(uint8_t *P, uint16_t V) { write16le(P, read16le(P) | V); }
 static void or32(uint8_t *P, uint32_t V) { write32le(P, read32le(P) | V); }
 
-static void applySecRel(const SectionChunk *Sec, uint8_t *Off,
-                        OutputSection *OS, uint64_t S) {
+static bool getSecRel(const SectionChunk *Sec, OutputSection *OS, uint64_t S,
+                      uint64_t &SecRel) {
   if (!OS) {
     if (Sec->isCodeView())
-      return;
+      return false;
     fatal("SECREL relocation cannot be applied to absolute symbols");
   }
-  uint64_t SecRel = S - OS->getRVA();
+  SecRel = S - OS->getRVA();
+  return true;
+}
+
+static void applySecRel(const SectionChunk *Sec, uint8_t *Off,
+                        OutputSection *OS, uint64_t S) {
+  uint64_t SecRel;
+  if (!getSecRel(Sec, OS, S, SecRel))
+    return;
   if (SecRel > UINT32_MAX) {
     error("overflow in SECREL relocation in section: " + Sec->getSectionName());
     return;
   }
   add32(Off, SecRel);
 }
 
 static void applySecIdx(uint8_t *Off, OutputSection *OS) {
static void applyArm64Ldr(uint8_t *Off, uint64_t Imm) {
   // 0x00800000 indicates 128 bit
   if ((Orig & 0x4800000) == 0x4800000)
     Size += 4;
   if ((Imm & ((1 << Size) - 1)) != 0)
     fatal("misaligned ldr/str offset");
   applyArm64Imm(Off, Imm >> Size, Size);
 }
 
+static void applySecRelAdd(const SectionChunk *Sec, uint8_t *Off,
+                           OutputSection *OS, uint64_t S, int Shift) {
+  uint64_t SecRel;
+  if (!getSecRel(Sec, OS, S, SecRel))
+    return;
+  SecRel >>= Shift;
+  if (Shift > 0 && SecRel > 0xfff) {
+    error("overflow in SECREL_HIGH12A relocation in section: " +
+          Sec->getSectionName());
+    return;
+  }
+  applyArm64Imm(Off, SecRel & 0xfff, 0);
+}
+
+static void applySecRelLdr(const SectionChunk *Sec, uint8_t *Off,
+                           OutputSection *OS, uint64_t S) {
+  uint64_t SecRel;
+  if (!getSecRel(Sec, OS, S, SecRel))
+    return;
+  applyArm64Ldr(Off, SecRel & 0xfff);
+}
+
 void SectionChunk::applyRelARM64(uint8_t *Off, uint16_t Type, OutputSection *OS,
                                  uint64_t S, uint64_t P) const {
   switch (Type) {
   case IMAGE_REL_ARM64_PAGEBASE_REL21: applyArm64Addr(Off, S, P); break;
   case IMAGE_REL_ARM64_PAGEOFFSET_12A: applyArm64Imm(Off, S & 0xfff, 0); break;
   case IMAGE_REL_ARM64_PAGEOFFSET_12L: applyArm64Ldr(Off, S & 0xfff); break;
   case IMAGE_REL_ARM64_BRANCH26:       or32(Off, ((S - P) & 0x0FFFFFFC) >> 2); break;
   case IMAGE_REL_ARM64_ADDR32:         add32(Off, S + Config->ImageBase); break;
   case IMAGE_REL_ARM64_ADDR32NB:       add32(Off, S); break;
   case IMAGE_REL_ARM64_ADDR64:         add64(Off, S + Config->ImageBase); break;
   case IMAGE_REL_ARM64_SECREL:         applySecRel(this, Off, OS, S); break;
+  case IMAGE_REL_ARM64_SECREL_LOW12A:  applySecRelAdd(this, Off, OS, S, 0); break;
+  case IMAGE_REL_ARM64_SECREL_HIGH12A: applySecRelAdd(this, Off, OS, S, 12); break;
+  case IMAGE_REL_ARM64_SECREL_LOW12L:  applySecRelLdr(this, Off, OS, S); break;
   default:
     fatal("unsupported relocation type 0x" + Twine::utohexstr(Type));
   }
 }
 
 void SectionChunk::writeTo(uint8_t *Buf) const {
   if (!hasData())
     return;

test/COFF/arm64-relocs-imports.test

 # BEFORE:       60:       00 fc 4f f9     ldr     x0, [x0, #8184]
 # BEFORE:       64:       e0 03 1f 2a     mov      w0, wzr
 # BEFORE:       68:       fe 07 41 f8     ldr     x30, [sp], #16
 # BEFORE:       6c:       c0 03 5f d6     ret
 # BEFORE:       70:       08 00 00 00     <unknown>
 # BEFORE:       74:       00 00 00 00     <unknown>
 # BEFORE:       78:       01 00 00 00     <unknown>
 # BEFORE:       7c:       01 00 00 00     <unknown>
+# BEFORE:       80:       00 00 00 91     add     x0, x0, #0
+# BEFORE:       84:       00 00 40 91     add     x0, x0, #0, lsl #12
+# BEFORE:       88:       00 00 40 f9     ldr     x0, [x0]
 
 # AFTER: Disassembly of section .text:
 # AFTER:  140002000:      fe 0f 1f f8     str     x30, [sp, #-16]!
 # AFTER:  140002004:      e0 ff ff f0     adrp    x0, #-4096
 # AFTER:  140002008:      00 18 00 91     add     x0, x0, #6
-# AFTER:  14000200c:      1d 00 00 94     bl      #116
+# AFTER:  14000200c:      20 00 00 94     bl      #128
 # AFTER:  140002010:      00 21 40 39     ldrb    w0, [x8, #8]
 # AFTER:  140002014:      00 11 40 79     ldrh    w0, [x8, #8]
 # AFTER:  140002018:      00 09 40 b9     ldr     w0, [x8, #8]
 # AFTER:  14000201c:      00 05 40 f9     ldr     x0, [x8, #8]
 # AFTER:  140002020:      00 21 00 39     strb    w0, [x8, #8]
 # AFTER:  140002024:      00 11 00 79     strh    w0, [x8, #8]
 # AFTER:  140002028:      00 09 00 b9     str     w0, [x8, #8]
 # AFTER:  14000202c:      00 05 00 f9     str     x0, [x8, #8]

 # AFTER:  140002060:      00 fc 47 f9     ldr     x0, [x0, #4088]
 # AFTER:  140002064:      e0 03 1f 2a     mov      w0, wzr
 # AFTER:  140002068:      fe 07 41 f8     ldr     x30, [sp], #16
 # AFTER:  14000206c:      c0 03 5f d6     ret
 # AFTER:  140002070:      10 10 00 40     <unknown>
 # AFTER:  140002074:      01 00 00 00     <unknown>
 # AFTER:  140002078:      09 10 00 00     <unknown>
 # AFTER:  14000207c:      09 00 00 00     <unknown>
-# AFTER:  140002080:      10 00 00 b0     adrp    x16, #4096
-# AFTER:  140002084:      10 1e 40 f9     ldr     x16, [x16, #56]
-# AFTER:  140002088:      00 02 1f d6     br      x16
+# AFTER:  140002080:      00 20 0e 91     add     x0, x0, #904
+# AFTER:  140002084:      00 04 40 91     add     x0, x0, #1, lsl #12
+# AFTER:  140002088:      00 c4 41 f9     ldr     x0, [x0, #904]
+# AFTER:  14000208c:      10 00 00 b0     adrp    x16, #4096
+# AFTER:  140002090:      10 1e 40 f9     ldr     x16, [x16, #56]
+# AFTER:  140002094:      00 02 1f d6     br      x16
 
 --- !COFF
 header:
   Machine:         IMAGE_FILE_MACHINE_ARM64
   Characteristics: [  ]
 sections:
   - Name:            .text
     Characteristics: [ IMAGE_SCN_CNT_CODE, IMAGE_SCN_MEM_EXECUTE, IMAGE_SCN_MEM_READ ]
     Alignment:       4
-    SectionData:     FE0F1FF80000009000080091000000940001403900014079000140B9000140F90001003900010079000100B9000100F90001403D0001407D000140BD000140FD0001C03D0001003D0001007D000100BD000100FD0001803D000540F9201A01B000FC4FF9E0031F2AFE0741F8C0035FD608000000000000000100000001000000
+    SectionData:     FE0F1FF80000009000080091000000940001403900014079000140B9000140F90001003900010079000100B9000100F90001403D0001407D000140BD000140FD0001C03D0001003D0001007D000100BD000100FD0001803D000540F9201A01B000FC4FF9E0031F2AFE0741F8C0035FD6080000000000000001000000010000000000009100004091000040f9
     Relocations:
       - VirtualAddress:  4
         SymbolName:      .Lstr
         Type:            IMAGE_REL_ARM64_PAGEBASE_REL21
       - VirtualAddress:  8
         SymbolName:      .Lstr
         Type:            IMAGE_REL_ARM64_PAGEOFFSET_12A
       - VirtualAddress:  12
Relocations:
         SymbolName:      .Lglobal
         Type:            IMAGE_REL_ARM64_ADDR64
       - VirtualAddress:  120
         SymbolName:      .Lglobal
         Type:            IMAGE_REL_ARM64_ADDR32NB
       - VirtualAddress:  124
         SymbolName:      .Lglobal
         Type:            IMAGE_REL_ARM64_SECREL
+      - VirtualAddress:  128
+        SymbolName:      .Lglobal5000
+        Type:            IMAGE_REL_ARM64_SECREL_LOW12A
+      - VirtualAddress:  132
+        SymbolName:      .Lglobal5000
+        Type:            IMAGE_REL_ARM64_SECREL_HIGH12A
+      - VirtualAddress:  136
+        SymbolName:      .Lglobal5000
+        Type:            IMAGE_REL_ARM64_SECREL_LOW12L
   - Name:            .data
     Characteristics: [ IMAGE_SCN_CNT_INITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ]
     Alignment:       4
     SectionData:     ''
   - Name:            .bss
     Characteristics: [ IMAGE_SCN_CNT_UNINITIALIZED_DATA, IMAGE_SCN_MEM_READ, IMAGE_SCN_MEM_WRITE ]
     Alignment:       4
     SectionData:     ''
- Name:            .Lglobal0
     ComplexType:     IMAGE_SYM_DTYPE_NULL
     StorageClass:    IMAGE_SYM_CLASS_STATIC
   - Name:            function
     Value:           0
     SectionNumber:   0
     SimpleType:      IMAGE_SYM_TYPE_NULL
     ComplexType:     IMAGE_SYM_DTYPE_NULL
     StorageClass:    IMAGE_SYM_CLASS_EXTERNAL
+  - Name:            .Lglobal5000
+    Value:           5000
+    SectionNumber:   4
+    SimpleType:      IMAGE_SYM_TYPE_NULL
+    ComplexType:     IMAGE_SYM_DTYPE_NULL
+    StorageClass:    IMAGE_SYM_CLASS_STATIC
 ...