Variable register class using HwMode

[abeserminji]

Summary

This patch introduces RegClassByHwMode which allows choosing the certain register class in run-time, depending on activated features.

For example:

def HwModeA  : HwMode<"+fp64", "RegClass">;
def VarRegClass : RegisterClassByHwMode<[DefaultMode, HwModeA], [DefaultRegClass, FP64RegClass]>,  RegisterClass<"Target", [f64], 64, (add D0)>;

When +fp64 feature is present, HwModeA is active and VarRegClass behaves like FP64RegClass. Otherwise it becomes DefaultRegClass.

Concern that I have here is that VarRegClass has to inherit RegisterClass in order to use it for instruction definitions. RegisterClass as defined in this case is not used later, because it's substituted with DefaultRegClass/FP64RegClass in tables like MCRegisterClasses[], RegisterClasses[] etc. I'd be glad to hear some comments on that/suggestions on how to fix it.

Depends on D43238. This is second in a series of three patches.

[kparzysz]

What is the exact difference between DefaultRegClass and FP64RegClass? TableGen precalculates certain properties of register classes that must be preserved, (such as class ordering).

[abeserminji]

In my particular example for Mips I have a situation like this:

def AFGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u", 0, 15)>;
def FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>;
def VarFGR64 : RegisterClassByHwMode<[DefaultMode, HwMips64], [AFGR64, FGR64]>, RegisterClass<"Mips", [f64], 64, (add D0)>;

Where AFGR64 and FGR64 would represent DefaultRegClass and FP64RegClass.
Until now I didn't experience any problems with wrong offsets being calculated, but maybe I'm missing something here?

[kparzysz]

Changing class members may affect topological ordering (see TopoOrderRC). This is something that TableGen precomputes and that cannot be changed at runtime without repeating all this computation.

[abeserminji]

I guess there is no need to keep this alive any longer.

include/llvm/CodeGen/TargetRegisterInfo.h

public:
   //
 protected:
   const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
     return RCInfos[getNumRegClasses() * hwMode.get() + RC.getID()];
   }
 
 public:
   /// Register class iterators
-  regclass_iterator regclass_begin() const { return RegClassBegin; }
-  regclass_iterator regclass_end() const { return RegClassEnd; }
+  regclass_iterator regclass_begin() const {
+    return RegClassBegin + (RegClassEnd - RegClassBegin) * hwMode.get("RegClass");
+  }
+  regclass_iterator regclass_end() const {
+    return RegClassEnd + (RegClassEnd - RegClassBegin) * hwMode.get("RegClass");
+  }
   iterator_range<regclass_iterator> regclasses() const {
     return make_range(regclass_begin(), regclass_end());
   }
 
   unsigned getNumRegClasses() const {
     return (unsigned)(regclass_end()-regclass_begin());
   }
 
   /// Returns the register class associated with the enumeration value.
   /// See class MCOperandInfo.
   const TargetRegisterClass *getRegClass(unsigned i) const {
     assert(i < getNumRegClasses() && "Register Class ID out of range");
-    return RegClassBegin[i];
+    return RegClassBegin[getNumRegClasses() * hwMode.get("RegClass") + i];
   }
 
   /// Returns the name of the register class.
   const char *getRegClassName(const TargetRegisterClass *Class) const {
     return MCRegisterInfo::getRegClassName(Class->MC);
   }
 
   /// Find the largest common subclass of A and B.

include/llvm/MC/MCRegisterInfo.h

public:
   /// \brief Map a target register to an equivalent SEH register
   /// number.  Returns LLVM register number if there is no equivalent value.
   int getSEHRegNum(unsigned RegNum) const;
 
   /// \brief Map a target register to an equivalent CodeView register
   /// number.
   int getCodeViewRegNum(unsigned RegNum) const;
 
-  regclass_iterator regclass_begin() const { return Classes; }
-  regclass_iterator regclass_end() const { return Classes+NumClasses; }
+  regclass_iterator regclass_begin() const {
+    return NumClasses * hwMode.get("RegClass") + Classes;
+  }
+  regclass_iterator regclass_end() const {
+    return NumClasses * hwMode.get("RegClass") + Classes + NumClasses;
+  }
   iterator_range<regclass_iterator> regclasses() const {
     return make_range(regclass_begin(), regclass_end());
   }
 
   unsigned getNumRegClasses() const {
     return (unsigned)(regclass_end()-regclass_begin());
   }
 
   /// \brief Returns the register class associated with the enumeration
   /// value.  See class MCOperandInfo.
   const MCRegisterClass& getRegClass(unsigned i) const {
     assert(i < getNumRegClasses() && "Register Class ID out of range");
-    return Classes[i];
+    return Classes[NumClasses * hwMode.get("RegClass") + i];
   }
 
   const char *getRegClassName(const MCRegisterClass *Class) const {
     return RegClassStrings + Class->NameIdx;
   }
 
    /// \brief Returns the encoding for RegNo
   uint16_t getEncodingValue(unsigned RegNo) const {

include/llvm/Target/Target.td

class RegisterClass<string namespace, list<ValueType> regTypes, int alignment,
   // A diagnostic message to emit when an invalid value is provided for this
   // register class when it is being used an an assembly operand. If this is
   // non-empty, an anonymous diagnostic type enum value will be generated, and
   // the assembly matcher will provide a function to map from diagnostic types
   // to message strings.
   string DiagnosticString = "";
 }
 
+// This class provides a choice to switch RegisterClass in runtime depending
+// on active HwMode. Useful for instructions which exist on 32/64bit platform
+// where they differ by RegisterClass. Reduces the ammount of code in TableGen.
+class RegisterClassByHwMode<list<HwMode> Ms = [], list<RegisterClass> Ts = []>
+  : HwModeSelect<Ms> {
+  list<RegisterClass> Objects = Ts;
+}
+
 // The memberList in a RegisterClass is a dag of set operations. TableGen
 // evaluates these set operations and expand them into register lists. These
 // are the most common operation, see test/TableGen/SetTheory.td for more
 // examples of what is possible:
 //
 // (add R0, R1, R2) - Set Union. Each argument can be an individual register, a
 // register class, or a sub-expression. This is also the way to simply list
 // registers.

utils/TableGen/InfoByHwMode.h

 // and RegSizeInfoByHwMode (parameterized register/spill size and alignment
 // data).
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
 #define LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H
 
 #include "CodeGenHwModes.h"
+#include "CodeGenRegisters.h"
+#include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/MachineValueType.h"
+#include "llvm/TableGen/Record.h"
 
 #include <map>
 #include <set>
 #include <string>
 #include <vector>
 
 namespace llvm {
 
 struct CodeGenHwModes;
+struct CodeGenRegBank;
+struct CodeGenRegisterClass;
 class Record;
 class raw_ostream;
 
 template <typename InfoT> struct InfoByHwMode;
 
 std::string getModeName(unsigned Mode);
 
 enum : unsigned {
struct RegSizeInfoByHwMode : public InfoByHwMode<RegSizeInfo> {
   }
 
   bool isSubClassOf(const RegSizeInfoByHwMode &I) const;
   bool hasStricterSpillThan(const RegSizeInfoByHwMode &I) const;
 
   void writeToStream(raw_ostream &OS) const;
 };
 
+struct RegClassByHwMode : public InfoByHwMode<const CodeGenRegisterClass*> {
+  RegClassByHwMode(Record *R, const CodeGenHwModes &CGH,
+                   const CodeGenRegBank &RegBank);
+};
+
 raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T);
 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T);
 raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T);
 
 } // namespace llvm
 
 #endif // LLVM_UTILS_TABLEGEN_INFOBYHWMODE_H

utils/TableGen/InfoByHwMode.cpp

for (unsigned i = 0, e = Pairs.size(); i != e; ++i) {
     const PairType *P = Pairs[i];
     OS << '(' << getModeName(P->first) << ':' << P->second << ')';
     if (i != e-1)
       OS << ',';
   }
   OS << '}';
 }
 
+RegClassByHwMode::RegClassByHwMode(Record *R, const CodeGenHwModes &CGH,
+                                   const CodeGenRegBank &RegBank) {
+  const HwModeSelect &MS = CGH.getHwModeSelect(R);
+  const auto &RegisterClasses = RegBank.getRegClasses();
+
+  for (const HwModeSelect::PairType &P : MS.Items) {
+    for (const auto &RC : RegisterClasses) {
+      if (RC.getName() == P.second->getName()) {
+        auto I = Map.insert({P.first, &RC});
+        assert(I.second && "Duplicate entry?");
+        (void)I;
+      }
+    }
+  }
+}
+
 namespace llvm {
   raw_ostream &operator<<(raw_ostream &OS, const ValueTypeByHwMode &T) {
     T.writeToStream(OS);
     return OS;
   }
 
   raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfo &T) {
     T.writeToStream(OS);
     return OS;
   }
 
   raw_ostream &operator<<(raw_ostream &OS, const RegSizeInfoByHwMode &T) {
     T.writeToStream(OS);
     return OS;
   }
 }

utils/TableGen/RegisterInfoEmitter.cpp

#endif
   RegClassStrings.layout();
   OS << "extern const char " << TargetName << "RegClassStrings[] = {\n";
   RegClassStrings.emit(OS, printChar);
   OS << "};\n\n";
 
   OS << "extern const MCRegisterClass " << TargetName
      << "MCRegisterClasses[] = {\n";
 
-  for (const auto &RC : RegisterClasses) {
+  const CodeGenHwModes &CGH = Target.getHwModes();
+  unsigned NumModes = CGH.getNumModeIds("RegClass");
+
+  for (unsigned M = 0; M < NumModes; ++M) {
+      OS << "  // Mode = " << M << " (";
+      if (M == 0)
+        OS << "Default";
+      else
+        OS << CGH.getMode(M, "RegClass").Name;
+      OS << ")\n";
+
+      for (const auto &iRC : RegisterClasses) {
+        const auto *tmpRC = &iRC;
+        if (iRC.getDef() && iRC.getDef()->isSubClassOf("RegisterClassByHwMode")) {
+          RegClassByHwMode regClassByHwMode(iRC.getDef(), CGH, RegBank);
+          tmpRC = regClassByHwMode.get(M);
+        }
+        const auto &RC = *tmpRC;
+
         assert(isInt<8>(RC.CopyCost) && "Copy cost too large.");
         uint32_t RegSize = 0;
         if (RC.RSI.isSimple())
           RegSize = RC.RSI.getSimple().RegSize;
         OS << "  { " << RC.getName() << ", " << RC.getName() << "Bits, "
            << RegClassStrings.get(RC.getName()) << ", "
            << RC.getOrder().size() << ", sizeof(" << RC.getName() << "Bits), "
            << RC.getQualifiedName() + "RegClassID" << ", "
            << RegSize/8 << ", "
            << RC.CopyCost << ", "
            << ( RC.Allocatable ? "true" : "false" ) << " },\n";
       }
+  }
 
   OS << "};\n\n";
 
   EmitRegMappingTables(OS, Regs, false);
 
   // Emit Reg encoding table
   OS << "extern const uint16_t " << TargetName;
   OS << "RegEncodingTable[] = {\n";
for (const auto &RC : RegisterClasses) {
         OS << "nullptr\n";
       else
         OS << RC.getName() << "GetRawAllocationOrder\n";
       OS << "  };\n\n";
     }
 
     OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n";
   }
-
+  NumModes = CGH.getNumModeIds("RegClass");
   OS << "\nnamespace {\n";
   OS << "  const TargetRegisterClass* const RegisterClasses[] = {\n";
-  for (const auto &RC : RegisterClasses)
+  for (unsigned M = 0; M < NumModes; ++M) {
+    OS << "  // Mode = " << M << " (";
+    if (M == 0)
+      OS << "Default";
+    else
+      OS << CGH.getMode(M, "RegClass").Name;
+    OS << ")\n";
+
+    for (const auto &iRC : RegisterClasses) {
+      const auto *tmpRC = &iRC;
+      if (iRC.getDef() && iRC.getDef()->isSubClassOf("RegisterClassByHwMode")) {
+        RegClassByHwMode regClassByHwMode(iRC.getDef(), CGH, RegBank);
+        tmpRC = regClassByHwMode.get(M);
+      }
+      const auto &RC = *tmpRC;
+
       OS << "    &" << RC.getQualifiedName() << "RegClass,\n";
+    }
+  }
   OS << "  };\n";
   OS << "} // end anonymous namespace\n";
 
   // Emit extra information about registers.
   const std::string &TargetName = Target.getName();
   OS << "\nstatic const TargetRegisterInfoDesc "
      << TargetName << "RegInfoDesc[] = { // Extra Descriptors\n";
   OS << "  { 0, false },\n";
if (!SubRegIndices.empty()) {
     emitComposeSubRegIndexLaneMask(OS, RegBank, ClassName);
   }
 
   // Emit getSubClassWithSubReg.
   if (!SubRegIndices.empty()) {
     OS << "const TargetRegisterClass *" << ClassName
        << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)"
        << " const {\n";
+    const CodeGenHwModes &CGH = Target.getHwModes();
+    unsigned NumModes = CGH.getNumModeIds("RegClass");
     // Use the smallest type that can hold a regclass ID with room for a
     // sentinel.
-    if (RegisterClasses.size() < UINT8_MAX)
+    if (RegisterClasses.size() * NumModes < UINT8_MAX)
       OS << "  static const uint8_t Table[";
-    else if (RegisterClasses.size() < UINT16_MAX)
+    else if (RegisterClasses.size() * NumModes < UINT16_MAX)
       OS << "  static const uint16_t Table[";
     else
       PrintFatalError("Too many register classes.");
-    OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n";
-    for (const auto &RC : RegisterClasses) {
+    OS << RegisterClasses.size() * NumModes << "][" << SubRegIndicesSize << "] = {\n";
+    for (unsigned M = 0; M < NumModes; ++M) {
+      OS << "  // Mode = " << M << " (";
+      if (M == 0)
+        OS << "Default";
+      else
+        OS << CGH.getMode(M, "RegClass").Name;
+      OS << ")\n";
+
+      for (const auto &iRC : RegisterClasses) {
+        const auto *tmpRC = &iRC;
+        if (iRC.getDef() && iRC.getDef()->isSubClassOf("RegisterClassByHwMode")) {
+          RegClassByHwMode regClassByHwMode(iRC.getDef(), CGH, RegBank);
+          tmpRC = regClassByHwMode.get(M);
+        }
+        const auto &RC = *tmpRC;
+
         OS << "    {\t// " << RC.getName() << "\n";
         for (auto &Idx : SubRegIndices) {
           if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx))
             OS << "      " << SRC->EnumValue + 1 << ",\t// " << Idx.getName()
                << " -> " << SRC->getName() << "\n";
           else
             OS << "      0,\t// " << Idx.getName() << "\n";
         }
         OS << "    },\n";
       }
+    }
     OS << "  };\n  assert(RC && \"Missing regclass\");\n"
        << "  if (!Idx) return RC;\n  --Idx;\n"
        << "  assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n"
-       << "  unsigned TV = Table[RC->getID()][Idx];\n"
+       << "  unsigned TV = Table[" << RegisterClasses.size()
+       << " * hwMode.get(\"VarReg\") + RC->getID()][Idx];\n"
        << "  return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n";
   }
 
   EmitRegUnitPressure(OS, RegBank, ClassName);
 
   // Emit the constructor of the class...
   OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n";
   OS << "extern const MCPhysReg " << TargetName << "RegDiffLists[];\n";