Add types to HwMode

[abeserminji]

Summary

This patch adds 'Type' field to HwMode class so that HwMode can be used for parameterization of different information independently.

Edit: It also changes the way how HwMode is determined and moves getHwMode(...) function to MCSubtargetInfo so it can be accessed from MC and Disassembler.

Motivation for this change is implementation of 'RegisterClassByHwMode' which should not be mutually exclusive with other implementations of *ByHwMode. This is first in a series of three patches.

[abeserminji]

No need for this, now when D43283 is closed.

include/llvm/CodeGen/TargetRegisterInfo.h

 // target machines register file.  This information is used for a variety of
 // purposed, especially register allocation.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_TARGETREGISTERINFO_H
 #define LLVM_CODEGEN_TARGETREGISTERINFO_H
 
+#include "llvm/HwMode.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineValueType.h"
 #include "llvm/IR/CallingConv.h"
 #include "llvm/MC/LaneBitmask.h"
private:
   const TargetRegisterInfoDesc *InfoDesc;     // Extra desc array for codegen
   const char *const *SubRegIndexNames;        // Names of subreg indexes.
   // Pointer to array of lane masks, one per sub-reg index.
   const LaneBitmask *SubRegIndexLaneMasks;
 
   regclass_iterator RegClassBegin, RegClassEnd;   // List of regclasses
   LaneBitmask CoveringLanes;
   const RegClassInfo *const RCInfos;
-  unsigned HwMode;
 
 protected:
   TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
                      regclass_iterator RegClassBegin,
                      regclass_iterator RegClassEnd,
                      const char *const *SRINames,
                      const LaneBitmask *SRILaneMasks,
                      LaneBitmask CoveringLanes,
                      const RegClassInfo *const RSI,
-                     unsigned Mode = 0);
+                     HwMode Mode = HwMode());
   virtual ~TargetRegisterInfo();
 
 public:
   // Register numbers can represent physical registers, virtual registers, and
   // sometimes stack slots. The unsigned values are divided into these ranges:
   //
   //   0           Not a register, can be used as a sentinel.
   //   [1;2^30)    Physical registers assigned by TableGen.
getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
                          const TargetRegisterClass *RCB, unsigned SubB,
                          unsigned &PreA, unsigned &PreB) const;
 
   //===--------------------------------------------------------------------===//
   // Register Class Information
   //
 protected:
   const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
-    return RCInfos[getNumRegClasses() * HwMode + RC.getID()];
+    return RCInfos[getNumRegClasses() * hwMode.get() + RC.getID()];
   }
 
 public:
   /// Register class iterators
   regclass_iterator regclass_begin() const { return RegClassBegin; }
   regclass_iterator regclass_end() const { return RegClassEnd; }
   iterator_range<regclass_iterator> regclasses() const {
     return make_range(regclass_begin(), regclass_end());

include/llvm/CodeGen/TargetSubtargetInfo.h

 //===- llvm/CodeGen/TargetSubtargetInfo.h - Target Information --*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the subtarget options of a Target machine.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_TARGETSUBTARGETINFO_H
 #define LLVM_CODEGEN_TARGETSUBTARGETINFO_H
 
+#include "llvm/HwMode.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/CodeGen/PBQPRAConstraint.h"
 #include "llvm/CodeGen/ScheduleDAGMutation.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
 #include "llvm/MC/MCSubtargetInfo.h"
 #include "llvm/Support/CodeGen.h"
public:
   // FIXME: This lets targets specialize the selector by subtarget (which lets
   // us do things like a dedicated avx512 selector).  However, we might want
   // to also specialize selectors by MachineFunction, which would let us be
   // aware of optsize/optnone and such.
   virtual const InstructionSelector *getInstructionSelector() const {
     return nullptr;
   }
 
-  virtual unsigned getHwMode() const { return 0; }
-
   /// Target can subclass this hook to select a different DAG scheduler.
   virtual RegisterScheduler::FunctionPassCtor
       getDAGScheduler(CodeGenOpt::Level) const {
     return nullptr;
   }
 
   virtual const LegalizerInfo *getLegalizerInfo() const { return nullptr; }
 

include/llvm/HwMode.h

+//===--------- HwMode.h - Hardware modes class ------------------*- C++ -*-===//
+//
+//                      The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This header file contais a definition of HwMode which is used for
+// parameterized register class information
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef LLVM_HWMODE_H_
+#define LLVM_HWMODE_H_
+
+#include <map>
+#include <string>
+#include <vector>
+
+namespace llvm {
+
+  typedef std::map<std::string, std::vector<std::string> > HwModeList;
+
+  struct HwMode  {
+    std::map<std::string, unsigned> hwModesByType;
+    unsigned get(std::string Type = "default") const {
+      auto it = hwModesByType.find(Type);
+      if (it == hwModesByType.end())
+        return 0;
+      return it->second;
+    }
+  };
+
+} // namespace llvm
+
+#endif /* LLVM_HWMODE_H_ */
+

include/llvm/MC/MCRegisterInfo.h

 // target machines register file.  This information is used for a variety of
 // purposed, especially register allocation.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCREGISTERINFO_H
 #define LLVM_MC_MCREGISTERINFO_H
 
+#include "llvm/HwMode.h"
 #include "llvm/ADT/DenseMap.h"
 #include "llvm/ADT/iterator_range.h"
 #include "llvm/MC/LaneBitmask.h"
 #include <cassert>
 #include <cstdint>
 #include <utility>
 
 namespace llvm {
public:
   // internal list pointers.
   friend class MCSubRegIterator;
   friend class MCSubRegIndexIterator;
   friend class MCSuperRegIterator;
   friend class MCRegUnitIterator;
   friend class MCRegUnitMaskIterator;
   friend class MCRegUnitRootIterator;
 
+  HwMode hwMode;
+
+public:
+  void setHwMode(HwMode M) {
+    hwMode = M;
+  }
   /// \brief Initialize MCRegisterInfo, called by TableGen
   /// auto-generated routines. *DO NOT USE*.
   void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
                           unsigned PC,
                           const MCRegisterClass *C, unsigned NC,
                           const MCPhysReg (*RURoots)[2],
                           unsigned NRU,
                           const MCPhysReg *DL,

include/llvm/MC/MCSubtargetInfo.h

 //===- llvm/MC/MCSubtargetInfo.h - Subtarget Information --------*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the subtarget options of a Target machine.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_MC_MCSUBTARGETINFO_H
 #define LLVM_MC_MCSUBTARGETINFO_H
 
+#include "llvm/HwMode.h"
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/Triple.h"
 #include "llvm/MC/MCInstrItineraries.h"
 #include "llvm/MC/MCSchedule.h"
 #include "llvm/MC/SubtargetFeature.h"
 #include <algorithm>
 #include <cassert>
public:
   void setFeatureBits(const FeatureBitset &FeatureBits_) {
     FeatureBits = FeatureBits_;
   }
 
   bool hasFeature(unsigned Feature) const {
     return FeatureBits[Feature];
   }
 
+  HwMode hwMode;
+
+public:
+  void InitHwModes(HwModeList modes) {
+    for (const auto &T : modes) {
+      for (unsigned i = 0; i < T.second.size(); i++) {
+        if (checkFeatures(T.second[i])) {
+          hwMode.hwModesByType[T.first] = i + 1;
+          break;
+        }
+      }
+      if (hwMode.hwModesByType.find(T.first) == hwMode.hwModesByType.end()) {
+        hwMode.hwModesByType[T.first] = 0;
+      }
+    }
+  }
+
 protected:
   /// Initialize the scheduling model and feature bits.
   ///
   /// FIXME: Find a way to stick this in the constructor, since it should only
   /// be called during initialization.
   void InitMCProcessorInfo(StringRef CPU, StringRef FS);
-
 public:
   /// Set the features to the default for the given CPU with an appended feature
   /// string.
   void setDefaultFeatures(StringRef CPU, StringRef FS);
 
   /// ToggleFeature - Toggle a feature and returns the re-computed feature
   /// bits. This version does not change the implied bits.
   FeatureBitset ToggleFeature(uint64_t FB);
public:
   /// Returns string representation of scheduler comment
   virtual std::string getSchedInfoStr(const MachineInstr &MI) const {
     return {};
   }
 
   virtual std::string getSchedInfoStr(MCInst const &MCI) const {
     return {};
   }
+
+  unsigned getHwMode(StringRef type) const {
+    return hwMode.get(type);
+  }
+
+  HwMode getHwMode() const {
+    return hwMode;
+  }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_MC_MCSUBTARGETINFO_H

include/llvm/Target/Target.td

 include "llvm/IR/Intrinsics.td"
 
 //===----------------------------------------------------------------------===//
 // Register file description - These classes are used to fill in the target
 // description classes.
 
 class RegisterClass; // Forward def
 
-class HwMode<string FS> {
+class HwMode<string FS, string T = "default"> {
   // A string representing subtarget features that turn on this HW mode.
   // For example, "+feat1,-feat2" will indicate that the mode is active
   // when "feat1" is enabled and "feat2" is disabled at the same time.
   // Any other features are not checked.
   // When multiple modes are used, they should be mutually exclusive,
   // otherwise the results are unpredictable.
   string Features = FS;
+  string Type = T;
 }
 
 // A special mode recognized by tablegen. This mode is considered active
 // when no other mode is active. For targets that do not use specific hw
 // modes, this is the only mode.
 def DefaultMode : HwMode<"">;
 
 // A class used to associate objects with HW modes. It is only intended to

lib/CodeGen/TargetRegisterInfo.cpp

 using namespace llvm;
 
 TargetRegisterInfo::TargetRegisterInfo(const TargetRegisterInfoDesc *ID,
                              regclass_iterator RCB, regclass_iterator RCE,
                              const char *const *SRINames,
                              const LaneBitmask *SRILaneMasks,
                              LaneBitmask SRICoveringLanes,
                              const RegClassInfo *const RCIs,
-                             unsigned Mode)
+                             HwMode Mode)
   : InfoDesc(ID), SubRegIndexNames(SRINames),
     SubRegIndexLaneMasks(SRILaneMasks),
     RegClassBegin(RCB), RegClassEnd(RCE),
     CoveringLanes(SRICoveringLanes),
-    RCInfos(RCIs), HwMode(Mode) {
+    RCInfos(RCIs) {
+      setHwMode(Mode);
 }
 
 TargetRegisterInfo::~TargetRegisterInfo() = default;
 
 void TargetRegisterInfo::markSuperRegs(BitVector &RegisterSet, unsigned Reg)
     const {
   for (MCSuperRegIterator AI(Reg, this, true); AI.isValid(); ++AI)
     RegisterSet.set(*AI);

lib/Target/Hexagon/HexagonRegisterInfo.h

 
 namespace Hexagon {
   // Generic (pseudo) subreg indices for use with getHexagonSubRegIndex.
   enum { ps_sub_lo = 0, ps_sub_hi = 1 };
 }
 
 class HexagonRegisterInfo : public HexagonGenRegisterInfo {
 public:
-  HexagonRegisterInfo(unsigned HwMode);
+  HexagonRegisterInfo(HwMode hwMode);
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF)
         const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
         CallingConv::ID) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;

lib/Target/Hexagon/HexagonRegisterInfo.cpp

 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
 
 #define GET_REGINFO_TARGET_DESC
 #include "HexagonGenRegisterInfo.inc"
 
 using namespace llvm;
 
-HexagonRegisterInfo::HexagonRegisterInfo(unsigned HwMode)
+HexagonRegisterInfo::HexagonRegisterInfo(HwMode hwMode)
     : HexagonGenRegisterInfo(Hexagon::R31, 0/*DwarfFlavor*/, 0/*EHFlavor*/,
-                             0/*PC*/, HwMode) {}
+                             0/*PC*/, hwMode) {}
 
 
 bool HexagonRegisterInfo::isEHReturnCalleeSaveReg(unsigned R) const {
   return R == Hexagon::R0 || R == Hexagon::R1 || R == Hexagon::R2 ||
          R == Hexagon::R3 || R == Hexagon::D0 || R == Hexagon::D1;
 }
 
 const MCPhysReg *

tools/llvm-mc/llvm-mc.cpp

int main(int argc, char **argv) {
   std::unique_ptr<buffer_ostream> BOS;
   raw_pwrite_stream *OS = &Out->os();
   std::unique_ptr<MCStreamer> Str;
 
   std::unique_ptr<MCInstrInfo> MCII(TheTarget->createMCInstrInfo());
   std::unique_ptr<MCSubtargetInfo> STI(
       TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
 
+  MRI->setHwMode(STI->getHwMode());
+
   MCInstPrinter *IP = nullptr;
   if (FileType == OFT_AssemblyFile) {
     IP = TheTarget->createMCInstPrinter(Triple(TripleName), OutputAsmVariant,
                                         *MAI, *MCII, *MRI);
 
     if (!IP) {
       errs()
           << "error: unable to create instruction printer for target triple '"

utils/TableGen/CodeGenHwModes.h

namespace llvm {
   class Record;
   class RecordKeeper;
 
   struct CodeGenHwModes;
 
   struct HwMode {
     HwMode(Record *R);
     StringRef Name;
+    std::string Type;
     std::string Features;
     void dump() const;
   };
 
   struct HwModeSelect {
     HwModeSelect(Record *R, CodeGenHwModes &CGH);
     typedef std::pair<unsigned, Record*> PairType;
     std::vector<PairType> Items;
     void dump() const;
   };
 
   struct CodeGenHwModes {
     enum : unsigned { DefaultMode = 0 };
     static StringRef DefaultModeName;
 
     CodeGenHwModes(RecordKeeper &R);
-    unsigned getHwModeId(StringRef Name) const;
-    const HwMode &getMode(unsigned Id) const {
+    unsigned getHwModeId(StringRef Name, StringRef Type = "default") const;
+    const HwMode &getMode(unsigned Id, StringRef Type = "default") const {
       assert(Id != 0 && "Mode id of 0 is reserved for the default mode");
-      return Modes[Id-1];
+      auto M = Modes.find(Type);
+      assert(M != Modes.end() && "Type not recognized");
+      return M->second[Id-1];
     }
     const HwModeSelect &getHwModeSelect(Record *R) const;
-    unsigned getNumModeIds() const { return Modes.size()+1; }
+    unsigned getNumModeIds(StringRef Type = "default") const {
+      auto M = Modes.find(Type);
+      if (M != Modes.end()) {
+        return M->second.size()+1;
+      }
+      return 1; // There is always at least a default mode
+    }
+
+    std::vector<std::string> getTypes() const {
+      std::vector<std::string> types;
+      for (auto M : Modes) {
+        types.push_back(M.first);
+      }
+      return types;
+    }
+
     void dump() const;
 
   private:
     RecordKeeper &Records;
-    StringMap<unsigned> ModeIds;  // HwMode (string) -> HwModeId
-    std::vector<HwMode> Modes;
+    // HwMode(type)(string) -> HwModeId
+    std::map<std::string, StringMap<unsigned> > ModeIds;
+    std::map<std::string, std::vector<HwMode> > Modes;
     std::map<Record*,HwModeSelect> ModeSelects;
   };
 }
 
 #endif // LLVM_UTILS_TABLEGEN_CODEGENHWMODES_H

utils/TableGen/CodeGenHwModes.cpp

 #include "llvm/TableGen/Record.h"
 
 using namespace llvm;
 
 StringRef CodeGenHwModes::DefaultModeName = "DefaultMode";
 
 HwMode::HwMode(Record *R) {
   Name = R->getName();
+  Type = R->getValueAsString("Type");
   Features = R->getValueAsString("Features");
 }
 
 LLVM_DUMP_METHOD
 void HwMode::dump() const {
-  dbgs() << Name << ": " << Features << '\n';
+  dbgs() << Name << "/" << Type << ": " << Features << '\n';
 }
 
 HwModeSelect::HwModeSelect(Record *R, CodeGenHwModes &CGH) {
   std::vector<Record*> Modes = R->getValueAsListOfDefs("Modes");
   std::vector<Record*> Objects = R->getValueAsListOfDefs("Objects");
   if (Modes.size() != Objects.size()) {
     PrintError(R->getLoc(), "in record " + R->getName() +
         " derived from HwModeSelect: the lists Modes and Objects should "
         "have the same size");
     report_fatal_error("error in target description.");
   }
   for (unsigned i = 0, e = Modes.size(); i != e; ++i) {
-    unsigned ModeId = CGH.getHwModeId(Modes[i]->getName());
+    unsigned ModeId = CGH.getHwModeId(Modes[i]->getName(),
+                                      Modes[i]->getValueAsString("Type"));
     Items.push_back(std::make_pair(ModeId, Objects[i]));
   }
 }
 
 LLVM_DUMP_METHOD
 void HwModeSelect::dump() const {
   dbgs() << '{';
   for (const PairType &P : Items)
     dbgs() << " (" << P.first << ',' << P.second->getName() << ')';
   dbgs() << " }\n";
 }
 
 CodeGenHwModes::CodeGenHwModes(RecordKeeper &RK) : Records(RK) {
   std::vector<Record*> MRs = Records.getAllDerivedDefinitions("HwMode");
   // The default mode needs a definition in the .td sources for TableGen
   // to accept references to it. We need to ignore the definition here.
   for (auto I = MRs.begin(), E = MRs.end(); I != E; ++I) {
     if ((*I)->getName() != DefaultModeName)
       continue;
     MRs.erase(I);
     break;
   }
 
   for (Record *R : MRs) {
-    Modes.emplace_back(R);
-    unsigned NewId = Modes.size();
-    ModeIds.insert(std::make_pair(Modes[NewId-1].Name, NewId));
+    std::string Type = R->getValueAsString("Type");
+    Modes[Type].emplace_back(R);
+    unsigned NewId = Modes[Type].size();
+    ModeIds[Type].insert(std::make_pair(Modes[Type][NewId-1].Name, NewId));
   }
 
   std::vector<Record*> MSs = Records.getAllDerivedDefinitions("HwModeSelect");
   for (Record *R : MSs) {
     auto P = ModeSelects.emplace(std::make_pair(R, HwModeSelect(R, *this)));
     assert(P.second);
     (void)P;
   }
 }
 
-unsigned CodeGenHwModes::getHwModeId(StringRef Name) const {
+unsigned CodeGenHwModes::getHwModeId(StringRef Name, StringRef Type) const {
   if (Name == DefaultModeName)
     return DefaultMode;
-  auto F = ModeIds.find(Name);
-  assert(F != ModeIds.end() && "Unknown mode name");
+  auto M = ModeIds.find(Type);
+  assert(M != ModeIds.end() && "Type not recognized");
+  auto F = M->second.find(Name);
+  assert(F != M->second.end() && "Unknown mode name");
   return F->second;
 }
 
 const HwModeSelect &CodeGenHwModes::getHwModeSelect(Record *R) const {
   auto F = ModeSelects.find(R);
   assert(F != ModeSelects.end() && "Record is not a \"mode select\"");
   return F->second;
 }
 
 LLVM_DUMP_METHOD
 void CodeGenHwModes::dump() const {
   dbgs() << "Modes: {\n";
-  for (const HwMode &M : Modes) {
+  for (const auto T : Modes) {
+    for (const HwMode &M : T.second) {
       dbgs() << "  ";
       M.dump();
     }
+  }
   dbgs() << "}\n";
 
   dbgs() << "ModeIds: {\n";
-  for (const auto &P : ModeIds)
-    dbgs() << "  " << P.first() << " -> " << P.second << '\n';
+  for (const auto T : ModeIds)
+    for (const auto &P1 : T.second)
+      dbgs() << "  " << P1.first() << "/" << T.first
+             << " -> " << P1.second << '\n';
   dbgs() << "}\n";
 
   dbgs() << "ModeSelects: {\n";
   for (const auto &P : ModeSelects) {
     dbgs() << "  " << P.first->getName() << " -> ";
     P.second.dump();
   }
   dbgs() << "}\n";
 }

utils/TableGen/RegisterInfoEmitter.cpp

RegisterInfoEmitter::runTargetHeader(raw_ostream &OS, CodeGenTarget &Target,
 
   OS << "namespace llvm {\n\n";
 
   OS << "class " << TargetName << "FrameLowering;\n\n";
 
   OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
      << "  explicit " << ClassName
      << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n"
-     << "      unsigned PC = 0, unsigned HwMode = 0);\n";
+     << "      unsigned PC = 0, HwMode hwMode = HwMode());\n";
   if (!RegBank.getSubRegIndices().empty()) {
     OS << "  unsigned composeSubRegIndicesImpl"
        << "(unsigned, unsigned) const override;\n"
        << "  LaneBitmask composeSubRegIndexLaneMaskImpl"
        << "(unsigned, LaneBitmask) const override;\n"
        << "  LaneBitmask reverseComposeSubRegIndexLaneMaskImpl"
        << "(unsigned, LaneBitmask) const override;\n"
        << "  const TargetRegisterClass *getSubClassWithSubReg"
RegisterInfoEmitter::runTargetDesc(raw_ostream &OS, CodeGenTarget &Target,
   OS << "extern const MCRegisterInfo::SubRegCoveredBits "
      << TargetName << "SubRegIdxRanges[];\n";
   OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n";
 
   EmitRegMappingTables(OS, Regs, true);
 
   OS << ClassName << "::\n" << ClassName
      << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n"
-        "      unsigned PC, unsigned HwMode)\n"
+        "      unsigned PC, HwMode hwMode)\n"
      << "  : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
      << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n"
      << "             SubRegIndexNameTable, SubRegIndexLaneMaskTable,\n"
      << "             ";
   printMask(OS, RegBank.CoveringLanes);
-  OS << ", RegClassInfos, HwMode) {\n"
+  OS << ", RegClassInfos, hwMode) {\n"
      << "  InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1
      << ", RA, PC,\n                     " << TargetName
      << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
      << "                     " << TargetName << "RegUnitRoots,\n"
      << "                     " << RegBank.getNumNativeRegUnits() << ",\n"
      << "                     " << TargetName << "RegDiffLists,\n"
      << "                     " << TargetName << "LaneMaskLists,\n"
      << "                     " << TargetName << "RegStrings,\n"

utils/TableGen/SubtargetEmitter.cpp

void ExpandProcResources(RecVec &PRVec, std::vector<int64_t> &Cycles,
                            const CodeGenProcModel &ProcModel);
   void GenSchedClassTables(const CodeGenProcModel &ProcModel,
                            SchedClassTables &SchedTables);
   void EmitSchedClassTables(SchedClassTables &SchedTables, raw_ostream &OS);
   void EmitProcessorModels(raw_ostream &OS);
   void EmitProcessorLookup(raw_ostream &OS);
   void EmitSchedModelHelpers(const std::string &ClassName, raw_ostream &OS);
   void EmitSchedModel(raw_ostream &OS);
-  void EmitHwModeCheck(const std::string &ClassName, raw_ostream &OS);
+  void EmitHwModesList(const CodeGenHwModes &CGH, raw_ostream &OS);
   void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures,
                              unsigned NumProcs);
 
 public:
   SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT)
     : TGT(TGT), Records(R), SchedModels(TGT.getSchedModels()),
       Target(TGT.getName()) {}
 
for (unsigned VC : VariantClasses) {
       OS << "    break;\n";
     }
     OS << "  };\n";
   }
   OS << "  report_fatal_error(\"Expected a variant SchedClass\");\n"
      << "} // " << ClassName << "::resolveSchedClass\n";
 }
 
-void SubtargetEmitter::EmitHwModeCheck(const std::string &ClassName,
-                                       raw_ostream &OS) {
-  const CodeGenHwModes &CGH = TGT.getHwModes();
-  assert(CGH.getNumModeIds() > 0);
-  if (CGH.getNumModeIds() == 1)
-    return;
-
-  OS << "unsigned " << ClassName << "::getHwMode() const {\n";
-  for (unsigned M = 1, NumModes = CGH.getNumModeIds(); M != NumModes; ++M) {
-    const HwMode &HM = CGH.getMode(M);
-    OS << "  if (checkFeatures(\"" << HM.Features
-       << "\")) return " << M << ";\n";
+void SubtargetEmitter::EmitHwModesList(const CodeGenHwModes &CGH, raw_ostream &OS) {
+  OS << "\nHwModeList HwModes;";
+  for (auto T : CGH.getTypes()) {
+    if (CGH.getNumModeIds(T) > 1) {
+      OS << "\nHwModes[\"" << T << "\"] = {";
+      for (unsigned M = 1, NumModes = CGH.getNumModeIds(T); M != NumModes; ++M) {
+        const HwMode &HM = CGH.getMode(M, T);
+        OS << "\"" << HM.Features << "\",";
+      }
+      OS << "};";
+    }
   }
-  OS << "  return 0;\n}\n";
 }
 
 //
 // ParseFeaturesFunction - Produces a subtarget specific function for parsing
 // the subtarget features string.
 //
 void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS,
                                              unsigned NumFeatures,

 #if 0
   OS << "} // end anonymous namespace\n\n";
 #endif
 
   // MCInstrInfo initialization routine.
   OS << "\nstatic inline MCSubtargetInfo *create" << Target
      << "MCSubtargetInfoImpl("
      << "const Triple &TT, StringRef CPU, StringRef FS) {\n";
-  OS << "  return new MCSubtargetInfo(TT, CPU, FS, ";
+  OS << "  MCSubtargetInfo *MCSI = new MCSubtargetInfo(TT, CPU, FS, ";
   if (NumFeatures)
     OS << Target << "FeatureKV, ";
   else
     OS << "None, ";
   if (NumProcs)
     OS << Target << "SubTypeKV, ";
   else
     OS << "None, ";
   OS << '\n'; OS.indent(22);
   OS << Target << "ProcSchedKV, "
      << Target << "WriteProcResTable, "
      << Target << "WriteLatencyTable, "
      << Target << "ReadAdvanceTable, ";
   OS << '\n'; OS.indent(22);
   if (SchedModels.hasItineraries()) {
     OS << Target << "Stages, "
        << Target << "OperandCycles, "
        << Target << "ForwardingPaths";
   } else
     OS << "nullptr, nullptr, nullptr";
-  OS << ");\n}\n\n";
+  OS << ");\n\n";
+  const CodeGenHwModes &CGH = TGT.getHwModes();
+  EmitHwModesList(CGH, OS);
+  OS << "  MCSI->InitHwModes(HwModes);\n\n";
+  OS << "  return MCSI;\n";
+  OS << "}\n\n";
 
   OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n";
 
   OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n";
   OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n\n";
 
OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n"
      << "  explicit " << ClassName << "(const Triple &TT, StringRef CPU, "
      << "StringRef FS);\n"
      << "public:\n"
      << "  unsigned resolveSchedClass(unsigned SchedClass, "
      << " const MachineInstr *DefMI,"
      << " const TargetSchedModel *SchedModel) const override;\n"
      << "  DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
      << " const;\n";
-  if (TGT.getHwModes().getNumModeIds() > 1)
-    OS << "  unsigned getHwMode() const override;\n";
   OS << "};\n"
      << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n";
 
   OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n";
   OS << "#undef GET_SUBTARGETINFO_CTOR\n\n";
 
OS << Target << "ProcSchedKV, "
      << Target << "ReadAdvanceTable, ";
   OS << '\n'; OS.indent(24);
   if (SchedModels.hasItineraries()) {
     OS << Target << "Stages, "
        << Target << "OperandCycles, "
        << Target << "ForwardingPaths";
   } else
     OS << "nullptr, nullptr, nullptr";
-  OS << ") {}\n\n";
+  OS << ") {";
+  EmitHwModesList(CGH, OS);
+  OS << "   InitHwModes(HwModes);\n";
+  OS << "}\n\n";
 
   EmitSchedModelHelpers(ClassName, OS);
-  EmitHwModeCheck(ClassName, OS);
 
   OS << "} // end namespace llvm\n\n";
 
   OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n";
 }
 
 namespace llvm {
 
 void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) {
   CodeGenTarget CGTarget(RK);
   SubtargetEmitter(RK, CGTarget).run(OS);
 }
 
 } // end namespace llvm