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Differential D43170

[AMDGPU] Change constant addr space to 4
ClosedPublic

Authored by yaxunl on Feb 11 2018, 1:08 PM.

Details

Reviewers
t-tye
arsenm
b-sumner
Commits
rG0124b5484cdd: [AMDGPU] Change constant addr space to 4
rL325030: [AMDGPU] Change constant addr space to 4

Diff Detail

Event Timeline

yaxunl created this revision.Feb 11 2018, 1:08 PM
Herald added subscribers: tpr, dstuttard, nhaehnle and 3 others. · View Herald TranscriptFeb 11 2018, 1:08 PM
t-tye accepted this revision.Feb 12 2018, 8:54 AM

LGTM. Cleanup comments can be done as a separate patch at a later time.

lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp
54–62

Since there is now only a single address space mapping can this simply be deleted?

63

Can then rename this to simply ASAliasRules

80–88

Ditto.

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
945–951

Now there is only a single address mapping presumably this can be eliminated?

This revision is now accepted and ready to land.Feb 12 2018, 8:54 AM
yaxunl added a comment.Feb 13 2018, 8:42 AM

Will clean up the old addr space mapping with separate patch.

Closed by commit rL325030: [AMDGPU] Change constant addr space to 4 (authored by yaxunl). · Explain WhyFeb 13 2018, 10:02 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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Diff 133801

docs/AMDGPUUsage.rst

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The memory space names used in the table, aside from the region memory space, is The memory space names used in the table, aside from the region memory space, is
from the OpenCL standard. from the OpenCL standard.
LLVM Address Space number is used throughout LLVM (for example, in LLVM IR). LLVM Address Space number is used throughout LLVM (for example, in LLVM IR).
.. table:: Address Space Mapping .. table:: Address Space Mapping
:name: amdgpu-address-space-mapping-table :name: amdgpu-address-space-mapping-table
================== ================= ================= ================== =================
LLVM Address Space Memory Space LLVM Address Space Memory Space
------------------ ----------------------------------- ================== =================
\ Current Default Future Default 0 Generic (Flat)
================== ================= ================= 1 Global
0 Generic (Flat) Generic (Flat) 2 Region (GDS)
1 Global Global 3 Local (group/LDS)
2 Constant Region (GDS) 4 Constant
3 Local (group/LDS) Local (group/LDS) 5 Private (Scratch)
4 Region (GDS) Constant ================== =================
5 Private (Scratch) Private (Scratch)
================== ================= =================
Current Default
This is the current default address space mapping used for all languages.
This will shortly be deprecated.
Future Default
This will shortly be the only address space mapping for all languages using
AMDGPU backend.
.. _amdgpu-memory-scopes: .. _amdgpu-memory-scopes:
Memory Scopes Memory Scopes
------------- -------------
This section provides LLVM memory synchronization scopes supported by the AMDGPU This section provides LLVM memory synchronization scopes supported by the AMDGPU
backend memory model when the target triple OS is ``amdhsa`` (see backend memory model when the target triple OS is ``amdhsa`` (see
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include/llvm/IR/IntrinsicsAMDGPU.td

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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz; defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz;
defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
<"__builtin_amdgcn_workgroup_id">; <"__builtin_amdgcn_workgroup_id">;
def int_amdgcn_dispatch_ptr : def int_amdgcn_dispatch_ptr :
GCCBuiltin<"__builtin_amdgcn_dispatch_ptr">, GCCBuiltin<"__builtin_amdgcn_dispatch_ptr">,
Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
[IntrNoMem, IntrSpeculatable]>; [IntrNoMem, IntrSpeculatable]>;
def int_amdgcn_queue_ptr : def int_amdgcn_queue_ptr :
GCCBuiltin<"__builtin_amdgcn_queue_ptr">, GCCBuiltin<"__builtin_amdgcn_queue_ptr">,
Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
[IntrNoMem, IntrSpeculatable]>; [IntrNoMem, IntrSpeculatable]>;
def int_amdgcn_kernarg_segment_ptr : def int_amdgcn_kernarg_segment_ptr :
GCCBuiltin<"__builtin_amdgcn_kernarg_segment_ptr">, GCCBuiltin<"__builtin_amdgcn_kernarg_segment_ptr">,
Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
[IntrNoMem, IntrSpeculatable]>; [IntrNoMem, IntrSpeculatable]>;
def int_amdgcn_implicitarg_ptr : def int_amdgcn_implicitarg_ptr :
GCCBuiltin<"__builtin_amdgcn_implicitarg_ptr">, GCCBuiltin<"__builtin_amdgcn_implicitarg_ptr">,
Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
[IntrNoMem, IntrSpeculatable]>; [IntrNoMem, IntrSpeculatable]>;
def int_amdgcn_groupstaticsize : def int_amdgcn_groupstaticsize :
GCCBuiltin<"__builtin_amdgcn_groupstaticsize">, GCCBuiltin<"__builtin_amdgcn_groupstaticsize">,
Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>; Intrinsic<[llvm_i32_ty], [], [IntrNoMem, IntrSpeculatable]>;
def int_amdgcn_dispatch_id : def int_amdgcn_dispatch_id :
GCCBuiltin<"__builtin_amdgcn_dispatch_id">, GCCBuiltin<"__builtin_amdgcn_dispatch_id">,
Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable]>; Intrinsic<[llvm_i64_ty], [], [IntrNoMem, IntrSpeculatable]>;
def int_amdgcn_implicit_buffer_ptr : def int_amdgcn_implicit_buffer_ptr :
GCCBuiltin<"__builtin_amdgcn_implicit_buffer_ptr">, GCCBuiltin<"__builtin_amdgcn_implicit_buffer_ptr">,
Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 4>], [],
[IntrNoMem, IntrSpeculatable]>; [IntrNoMem, IntrSpeculatable]>;
// Set EXEC to the 64-bit value given. // Set EXEC to the 64-bit value given.
// This is always moved to the beginning of the basic block. // This is always moved to the beginning of the basic block.
def int_amdgcn_init_exec : Intrinsic<[], def int_amdgcn_init_exec : Intrinsic<[],
[llvm_i64_ty], // 64-bit literal constant [llvm_i64_ty], // 64-bit literal constant
[IntrConvergent]>; [IntrConvergent]>;
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lib/Target/AMDGPU/AMDGPU.h

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unsigned FLAT_ADDRESS; ///< Address space for flat memory. unsigned FLAT_ADDRESS; ///< Address space for flat memory.
unsigned REGION_ADDRESS; ///< Address space for region memory. unsigned REGION_ADDRESS; ///< Address space for region memory.
enum : unsigned { enum : unsigned {
// The maximum value for flat, generic, local, private, constant and region. // The maximum value for flat, generic, local, private, constant and region.
MAX_COMMON_ADDRESS = 5, MAX_COMMON_ADDRESS = 5,
GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0). GLOBAL_ADDRESS = 1, ///< Address space for global memory (RAT0, VTX0).
CONSTANT_ADDRESS = 2, ///< Address space for constant memory (VTX2) CONSTANT_ADDRESS = 4, ///< Address space for constant memory (VTX2)
LOCAL_ADDRESS = 3, ///< Address space for local memory. LOCAL_ADDRESS = 3, ///< Address space for local memory.
/// Address space for direct addressible parameter memory (CONST0) /// Address space for direct addressible parameter memory (CONST0)
PARAM_D_ADDRESS = 6, PARAM_D_ADDRESS = 6,
/// Address space for indirect addressible parameter memory (VTX1) /// Address space for indirect addressible parameter memory (VTX1)
PARAM_I_ADDRESS = 7, PARAM_I_ADDRESS = 7,
// Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on
// this order to be able to dynamically index a constant buffer, for // this order to be able to dynamically index a constant buffer, for
Show All 35 Lines

lib/Target/AMDGPU/AMDGPUAliasAnalysis.cpp

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Linesvoid AMDGPUAAWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesAll(); AU.setPreservesAll();
} }
// Must match the table in getAliasResult. // Must match the table in getAliasResult.
AMDGPUAAResult::ASAliasRulesTy::ASAliasRulesTy(AMDGPUAS AS_, Triple::ArchType Arch_) AMDGPUAAResult::ASAliasRulesTy::ASAliasRulesTy(AMDGPUAS AS_, Triple::ArchType Arch_)
: Arch(Arch_), AS(AS_) { : Arch(Arch_), AS(AS_) {
// These arrarys are indexed by address space value // These arrarys are indexed by address space value
// enum elements 0 ... to 5 // enum elements 0 ... to 5
static const AliasResult ASAliasRulesPrivIsZero[6][6] = { static const AliasResult ASAliasRulesPrivIsZero[6][6] = {
/* Private Global Constant Group Flat Region*/ /* Private Global Constant Group Flat Region*/
/* Private */ {MayAlias, NoAlias , NoAlias , NoAlias , MayAlias, NoAlias}, /* Private */ {MayAlias, NoAlias , NoAlias , NoAlias , MayAlias, NoAlias},
/* Global */ {NoAlias , MayAlias, NoAlias , NoAlias , MayAlias, NoAlias}, /* Global */ {NoAlias , MayAlias, NoAlias , NoAlias , MayAlias, NoAlias},
/* Constant */ {NoAlias , NoAlias , MayAlias, NoAlias , MayAlias, NoAlias}, /* Constant */ {NoAlias , NoAlias , MayAlias, NoAlias , MayAlias, NoAlias},
/* Group */ {NoAlias , NoAlias , NoAlias , MayAlias, MayAlias, NoAlias}, /* Group */ {NoAlias , NoAlias , NoAlias , MayAlias, MayAlias, NoAlias},
/* Flat */ {MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias}, /* Flat */ {MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias},
/* Region */ {NoAlias , NoAlias , NoAlias , NoAlias , MayAlias, MayAlias} /* Region */ {NoAlias , NoAlias , NoAlias , NoAlias , MayAlias, MayAlias}
}; };
t-tyeUnsubmitted
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Since there is now only a single address space mapping can this simply be deleted?

t-tye: Since there is now only a single address space mapping can this simply be deleted?
static const AliasResult ASAliasRulesGenIsZero[6][6] = { static const AliasResult ASAliasRulesGenIsZero[6][6] = {
t-tyeUnsubmitted
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Can then rename this to simply ASAliasRules

t-tye: Can then rename this to simply ASAliasRules
/* Flat Global Constant Group Region Private */ /* Flat Global Region Group Constant Private */
/* Flat */ {MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias}, /* Flat */ {MayAlias, MayAlias, MayAlias, MayAlias, MayAlias, MayAlias},
/* Global */ {MayAlias, MayAlias, NoAlias , NoAlias , NoAlias , NoAlias}, /* Global */ {MayAlias, MayAlias, NoAlias , NoAlias , NoAlias , NoAlias},
/* Constant */ {MayAlias, NoAlias , MayAlias, NoAlias , NoAlias, NoAlias}, /* Constant */ {MayAlias, NoAlias , MayAlias, NoAlias , NoAlias, NoAlias},
/* Group */ {MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , NoAlias}, /* Group */ {MayAlias, NoAlias , NoAlias , MayAlias, NoAlias , NoAlias},
/* Region */ {MayAlias, NoAlias , NoAlias , NoAlias, MayAlias, NoAlias}, /* Region */ {MayAlias, NoAlias , NoAlias , NoAlias, MayAlias, NoAlias},
/* Private */ {MayAlias, NoAlias , NoAlias , NoAlias , NoAlias , MayAlias} /* Private */ {MayAlias, NoAlias , NoAlias , NoAlias , NoAlias , MayAlias}
}; };
assert(AS.MAX_COMMON_ADDRESS <= 5); assert(AS.MAX_COMMON_ADDRESS <= 5);
if (AS.FLAT_ADDRESS == 0) { if (AS.FLAT_ADDRESS == 0) {
assert(AS.GLOBAL_ADDRESS == 1 && assert(AS.GLOBAL_ADDRESS == 1 &&
AS.REGION_ADDRESS == 4 && AS.REGION_ADDRESS == 2 &&
AS.LOCAL_ADDRESS == 3 && AS.LOCAL_ADDRESS == 3 &&
AS.CONSTANT_ADDRESS == 2 && AS.CONSTANT_ADDRESS == 4 &&
AS.PRIVATE_ADDRESS == 5); AS.PRIVATE_ADDRESS == 5);
ASAliasRules = &ASAliasRulesGenIsZero; ASAliasRules = &ASAliasRulesGenIsZero;
} else { } else {
assert(AS.PRIVATE_ADDRESS == 0 && assert(AS.PRIVATE_ADDRESS == 0 &&
AS.GLOBAL_ADDRESS == 1 && AS.GLOBAL_ADDRESS == 1 &&
AS.CONSTANT_ADDRESS == 2 && AS.CONSTANT_ADDRESS == 2 &&
AS.LOCAL_ADDRESS == 3 && AS.LOCAL_ADDRESS == 3 &&
AS.FLAT_ADDRESS == 4 && AS.FLAT_ADDRESS == 4 &&
AS.REGION_ADDRESS == 5); AS.REGION_ADDRESS == 5);
ASAliasRules = &ASAliasRulesPrivIsZero; ASAliasRules = &ASAliasRulesPrivIsZero;
} }
t-tyeUnsubmitted
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Ditto.

t-tye: Ditto.
} }
AliasResult AMDGPUAAResult::ASAliasRulesTy::getAliasResult(unsigned AS1, AliasResult AMDGPUAAResult::ASAliasRulesTy::getAliasResult(unsigned AS1,
unsigned AS2) const { unsigned AS2) const {
if (AS1 > AS.MAX_COMMON_ADDRESS || AS2 > AS.MAX_COMMON_ADDRESS) { if (AS1 > AS.MAX_COMMON_ADDRESS || AS2 > AS.MAX_COMMON_ADDRESS) {
if (Arch == Triple::amdgcn) if (Arch == Triple::amdgcn)
report_fatal_error("Pointer address space out of range"); report_fatal_error("Pointer address space out of range");
return AS1 == AS2 ? MayAlias : NoAlias; return AS1 == AS2 ? MayAlias : NoAlias;
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lib/Target/AMDGPU/AMDGPUCallLowering.cpp

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if (Info->hasQueuePtr()) { if (Info->hasQueuePtr()) {
unsigned QueuePtrReg = Info->addQueuePtr(*TRI); unsigned QueuePtrReg = Info->addQueuePtr(*TRI);
// FIXME: Need to add reg as live-in // FIXME: Need to add reg as live-in
CCInfo.AllocateReg(QueuePtrReg); CCInfo.AllocateReg(QueuePtrReg);
} }
if (Info->hasKernargSegmentPtr()) { if (Info->hasKernargSegmentPtr()) {
unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI); unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
const LLT P2 = LLT::pointer(2, 64); const LLT P2 = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
unsigned VReg = MRI.createGenericVirtualRegister(P2); unsigned VReg = MRI.createGenericVirtualRegister(P2);
MRI.addLiveIn(InputPtrReg, VReg); MRI.addLiveIn(InputPtrReg, VReg);
MIRBuilder.getMBB().addLiveIn(InputPtrReg); MIRBuilder.getMBB().addLiveIn(InputPtrReg);
MIRBuilder.buildCopy(VReg, InputPtrReg); MIRBuilder.buildCopy(VReg, InputPtrReg);
CCInfo.AllocateReg(InputPtrReg); CCInfo.AllocateReg(InputPtrReg);
} }
if (Info->hasDispatchID()) { if (Info->hasDispatchID()) {
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lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp

//===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==// //===- AMDGPULegalizerInfo.cpp -----------------------------------*- C++ -*-==//
// //
// The LLVM Compiler Infrastructure // The LLVM Compiler Infrastructure
// //
// This file is distributed under the University of Illinois Open Source // This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details. // License. See LICENSE.TXT for details.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
/// \file /// \file
/// This file implements the targeting of the Machinelegalizer class for /// This file implements the targeting of the Machinelegalizer class for
/// AMDGPU. /// AMDGPU.
/// \todo This should be generated by TableGen. /// \todo This should be generated by TableGen.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "AMDGPU.h"
#include "AMDGPULegalizerInfo.h" #include "AMDGPULegalizerInfo.h"
#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h" #include "llvm/IR/DerivedTypes.h"
#include "llvm/IR/Type.h" #include "llvm/IR/Type.h"
#include "llvm/Support/Debug.h" #include "llvm/Support/Debug.h"
using namespace llvm; using namespace llvm;
using namespace LegalizeActions; using namespace LegalizeActions;
AMDGPULegalizerInfo::AMDGPULegalizerInfo() { AMDGPULegalizerInfo::AMDGPULegalizerInfo() {
using namespace TargetOpcode; using namespace TargetOpcode;
const LLT S1= LLT::scalar(1); const LLT S1= LLT::scalar(1);
const LLT V2S16 = LLT::vector(2, 16); const LLT V2S16 = LLT::vector(2, 16);
const LLT S32 = LLT::scalar(32); const LLT S32 = LLT::scalar(32);
const LLT S64 = LLT::scalar(64); const LLT S64 = LLT::scalar(64);
const LLT P1 = LLT::pointer(1, 64); const LLT P1 = LLT::pointer(AMDGPUAS::GLOBAL_ADDRESS, 64);
const LLT P2 = LLT::pointer(2, 64); const LLT P2 = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
setAction({G_ADD, S32}, Legal); setAction({G_ADD, S32}, Legal);
setAction({G_AND, S32}, Legal); setAction({G_AND, S32}, Legal);
setAction({G_BITCAST, V2S16}, Legal); setAction({G_BITCAST, V2S16}, Legal);
setAction({G_BITCAST, 1, S32}, Legal); setAction({G_BITCAST, 1, S32}, Legal);
setAction({G_BITCAST, S32}, Legal); setAction({G_BITCAST, S32}, Legal);
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lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

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if (TT.getArch() == Triple::r600) { if (TT.getArch() == Triple::r600) {
// 32-bit pointers. // 32-bit pointers.
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
} }
// 32-bit private, local, and region pointers. 64-bit global, constant and // 32-bit private, local, and region pointers. 64-bit global, constant and
// flat. // flat.
return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" return "e-p:64:64-p1:64:64-p2:32:32-p3:32:32-p4:64:64-p5:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
} }
LLVM_READNONE LLVM_READNONE
static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) { static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
if (!GPU.empty()) if (!GPU.empty())
return GPU; return GPU;
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lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

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} // end namespace AMDGPU } // end namespace AMDGPU
} // end namespace llvm } // end namespace llvm
namespace llvm { namespace llvm {
namespace AMDGPU { namespace AMDGPU {
AMDGPUAS getAMDGPUAS(Triple T) { AMDGPUAS getAMDGPUAS(Triple T) {
AMDGPUAS AS; AMDGPUAS AS;
AS.FLAT_ADDRESS = 0; AS.FLAT_ADDRESS = 0;
AS.PRIVATE_ADDRESS = 5; AS.PRIVATE_ADDRESS = 5;
AS.REGION_ADDRESS = 4; AS.REGION_ADDRESS = 2;
return AS; return AS;
} }
t-tyeUnsubmitted
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Now there is only a single address mapping presumably this can be eliminated?

t-tye: Now there is only a single address mapping presumably this can be eliminated?
AMDGPUAS getAMDGPUAS(const TargetMachine &M) { AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
return getAMDGPUAS(M.getTargetTriple()); return getAMDGPUAS(M.getTargetTriple());
} }
AMDGPUAS getAMDGPUAS(const Module &M) { AMDGPUAS getAMDGPUAS(const Module &M) {
return getAMDGPUAS(Triple(M.getTargetTriple())); return getAMDGPUAS(Triple(M.getTargetTriple()));
} }
} // namespace AMDGPU } // namespace AMDGPU
} // namespace llvm } // namespace llvm
Context not available.

test/CodeGen/AMDGPU/GlobalISel/inst-select-load-smrd.mir

# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,SI,SICI,SIVI # RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,SI,SICI,SIVI
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,CI,SICI # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,CI,SICI
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,VI,SIVI # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s -check-prefixes=GCN,VI,SIVI
# REQUIRES: global-isel # REQUIRES: global-isel
--- | --- |
define amdgpu_kernel void @smrd_imm(i32 addrspace(2)* %const0) { ret void } define amdgpu_kernel void @smrd_imm(i32 addrspace(4)* %const0) { ret void }
... ...
--- ---
name: smrd_imm name: smrd_imm
legalized: true legalized: true
regBankSelected: true regBankSelected: true
# GCN: body: # GCN: body:
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# SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1 # SIVI: [[ADD_PTR:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[ADD_PTR_LO]], %subreg.sub0, [[ADD_PTR_HI]], %subreg.sub1
# SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0 # SIVI: S_LOAD_DWORD_IMM [[ADD_PTR]], 0, 0
# CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0 # CI: S_LOAD_DWORD_IMM_ci [[PTR]], 1073741824, 0
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%0:sgpr(p2) = COPY $sgpr0_sgpr1 %0:sgpr(p4) = COPY $sgpr0_sgpr1
%1:sgpr(s64) = G_CONSTANT i64 4 %1:sgpr(s64) = G_CONSTANT i64 4
%2:sgpr(p2) = G_GEP %0, %1 %2:sgpr(p4) = G_GEP %0, %1
%3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0) %3:sgpr(s32) = G_LOAD %2 :: (load 4 from %ir.const0)
$sgpr0 = COPY %3 $sgpr0 = COPY %3
%4:sgpr(s64) = G_CONSTANT i64 1020 %4:sgpr(s64) = G_CONSTANT i64 1020
%5:sgpr(p2) = G_GEP %0, %4 %5:sgpr(p4) = G_GEP %0, %4
%6:sgpr(s32) = G_LOAD %5 :: (load 4 from %ir.const0) %6:sgpr(s32) = G_LOAD %5 :: (load 4 from %ir.const0)
$sgpr0 = COPY %6 $sgpr0 = COPY %6
%7:sgpr(s64) = G_CONSTANT i64 1024 %7:sgpr(s64) = G_CONSTANT i64 1024
%8:sgpr(p2) = G_GEP %0, %7 %8:sgpr(p4) = G_GEP %0, %7
%9:sgpr(s32) = G_LOAD %8 :: (load 4 from %ir.const0) %9:sgpr(s32) = G_LOAD %8 :: (load 4 from %ir.const0)
$sgpr0 = COPY %9 $sgpr0 = COPY %9
%10:sgpr(s64) = G_CONSTANT i64 1048572 %10:sgpr(s64) = G_CONSTANT i64 1048572
%11:sgpr(p2) = G_GEP %0, %10 %11:sgpr(p4) = G_GEP %0, %10
%12:sgpr(s32) = G_LOAD %11 :: (load 4 from %ir.const0) %12:sgpr(s32) = G_LOAD %11 :: (load 4 from %ir.const0)
$sgpr0 = COPY %12 $sgpr0 = COPY %12
%13:sgpr(s64) = G_CONSTANT i64 1048576 %13:sgpr(s64) = G_CONSTANT i64 1048576
%14:sgpr(p2) = G_GEP %0, %13 %14:sgpr(p4) = G_GEP %0, %13
%15:sgpr(s32) = G_LOAD %14 :: (load 4 from %ir.const0) %15:sgpr(s32) = G_LOAD %14 :: (load 4 from %ir.const0)
$sgpr0 = COPY %15 $sgpr0 = COPY %15
%16:sgpr(s64) = G_CONSTANT i64 17179869180 %16:sgpr(s64) = G_CONSTANT i64 17179869180
%17:sgpr(p2) = G_GEP %0, %16 %17:sgpr(p4) = G_GEP %0, %16
%18:sgpr(s32) = G_LOAD %17 :: (load 4 from %ir.const0) %18:sgpr(s32) = G_LOAD %17 :: (load 4 from %ir.const0)
$sgpr0 = COPY %18 $sgpr0 = COPY %18
%19:sgpr(s64) = G_CONSTANT i64 17179869184 %19:sgpr(s64) = G_CONSTANT i64 17179869184
%20:sgpr(p2) = G_GEP %0, %19 %20:sgpr(p4) = G_GEP %0, %19
%21:sgpr(s32) = G_LOAD %20 :: (load 4 from %ir.const0) %21:sgpr(s32) = G_LOAD %20 :: (load 4 from %ir.const0)
$sgpr0 = COPY %21 $sgpr0 = COPY %21
%22:sgpr(s64) = G_CONSTANT i64 4294967292 %22:sgpr(s64) = G_CONSTANT i64 4294967292
%23:sgpr(p2) = G_GEP %0, %22 %23:sgpr(p4) = G_GEP %0, %22
%24:sgpr(s32) = G_LOAD %23 :: (load 4 from %ir.const0) %24:sgpr(s32) = G_LOAD %23 :: (load 4 from %ir.const0)
$sgpr0 = COPY %24 $sgpr0 = COPY %24
%25:sgpr(s64) = G_CONSTANT i64 4294967296 %25:sgpr(s64) = G_CONSTANT i64 4294967296
%26:sgpr(p2) = G_GEP %0, %25 %26:sgpr(p4) = G_GEP %0, %25
%27:sgpr(s32) = G_LOAD %26 :: (load 4 from %ir.const0) %27:sgpr(s32) = G_LOAD %26 :: (load 4 from %ir.const0)
$sgpr0 = COPY %27 $sgpr0 = COPY %27
... ...
--- ---

test/CodeGen/AMDGPU/GlobalISel/irtranslator-amdgpu_vs.ll

Show All 12 Lines
; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY $vgpr0
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]] ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[V0]]
define amdgpu_vs void @test_f32(float %arg0) { define amdgpu_vs void @test_f32(float %arg0) {
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
ret void ret void
} }
; CHECK-LABEL: name: test_ptr2_byval ; CHECK-LABEL: name: test_ptr2_byval
; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY $sgpr0_sgpr1 ; CHECK: [[S01:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; CHECK: G_LOAD [[S01]] ; CHECK: G_LOAD [[S01]]
define amdgpu_vs void @test_ptr2_byval(i32 addrspace(2)* byval %arg0) { define amdgpu_vs void @test_ptr2_byval(i32 addrspace(4)* byval %arg0) {
%tmp0 = load volatile i32, i32 addrspace(2)* %arg0 %tmp0 = load volatile i32, i32 addrspace(4)* %arg0
ret void ret void
} }
; CHECK-LABEL: name: test_ptr2_inreg ; CHECK-LABEL: name: test_ptr2_inreg
; CHECK: [[S01:%[0-9]+]]:_(p2) = COPY $sgpr0_sgpr1 ; CHECK: [[S01:%[0-9]+]]:_(p4) = COPY $sgpr0_sgpr1
; CHECK: G_LOAD [[S01]] ; CHECK: G_LOAD [[S01]]
define amdgpu_vs void @test_ptr2_inreg(i32 addrspace(2)* inreg %arg0) { define amdgpu_vs void @test_ptr2_inreg(i32 addrspace(4)* inreg %arg0) {
%tmp0 = load volatile i32, i32 addrspace(2)* %arg0 %tmp0 = load volatile i32, i32 addrspace(4)* %arg0
ret void ret void
} }
; CHECK-LABEL: name: test_sgpr_alignment0 ; CHECK-LABEL: name: test_sgpr_alignment0
; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0 ; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[S23:%[0-9]+]]:_(p2) = COPY $sgpr2_sgpr3 ; CHECK: [[S23:%[0-9]+]]:_(p4) = COPY $sgpr2_sgpr3
; CHECK: G_LOAD [[S23]] ; CHECK: G_LOAD [[S23]]
; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]] ; CHECK: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.exp), %{{[0-9]+}}(s32), %{{[0-9]+}}(s32), [[S0]]
define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, i32 addrspace(2)* inreg %arg1) { define amdgpu_vs void @test_sgpr_alignment0(float inreg %arg0, i32 addrspace(4)* inreg %arg1) {
%tmp0 = load volatile i32, i32 addrspace(2)* %arg1 %tmp0 = load volatile i32, i32 addrspace(4)* %arg1
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %arg0, float undef, float undef, float undef, i1 false, i1 false) #0
ret void ret void
} }
; CHECK-LABEL: name: test_order ; CHECK-LABEL: name: test_order
; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0 ; CHECK: [[S0:%[0-9]+]]:_(s32) = COPY $sgpr0
; CHECK: [[S1:%[0-9]+]]:_(s32) = COPY $sgpr1 ; CHECK: [[S1:%[0-9]+]]:_(s32) = COPY $sgpr1
; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY $vgpr0 ; CHECK: [[V0:%[0-9]+]]:_(s32) = COPY $vgpr0
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test/CodeGen/AMDGPU/GlobalISel/regbankselect.mir

# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=regbankselect -global-isel %s -verify-machineinstrs -o - | FileCheck %s
# REQUIRES: global-isel # REQUIRES: global-isel
--- | --- |
define amdgpu_kernel void @load_constant(i32 addrspace(2)* %ptr0) { ret void } define amdgpu_kernel void @load_constant(i32 addrspace(4)* %ptr0) { ret void }
define amdgpu_kernel void @load_global_uniform(i32 addrspace(1)* %ptr1) { define amdgpu_kernel void @load_global_uniform(i32 addrspace(1)* %ptr1) {
%tmp0 = load i32, i32 addrspace(1)* %ptr1 %tmp0 = load i32, i32 addrspace(1)* %ptr1
ret void ret void
} }
define amdgpu_kernel void @load_global_non_uniform(i32 addrspace(1)* %ptr2) { define amdgpu_kernel void @load_global_non_uniform(i32 addrspace(1)* %ptr2) {
%tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #0
%tmp1 = getelementptr i32, i32 addrspace(1)* %ptr2, i32 %tmp0 %tmp1 = getelementptr i32, i32 addrspace(1)* %ptr2, i32 %tmp0
%tmp2 = load i32, i32 addrspace(1)* %tmp1 %tmp2 = load i32, i32 addrspace(1)* %tmp1
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# CHECK-LABEL: name: load_constant # CHECK-LABEL: name: load_constant
# CHECK: registers: # CHECK: registers:
# CHECK: - { id: 0, class: sgpr, preferred-register: '' } # CHECK: - { id: 0, class: sgpr, preferred-register: '' }
# CHECK: - { id: 1, class: sgpr, preferred-register: '' } # CHECK: - { id: 1, class: sgpr, preferred-register: '' }
body: | body: |
bb.0: bb.0:
liveins: $sgpr0_sgpr1 liveins: $sgpr0_sgpr1
%0:_(p2) = COPY $sgpr0_sgpr1 %0:_(p4) = COPY $sgpr0_sgpr1
%1:_(s32) = G_LOAD %0 :: (load 4 from %ir.ptr0) %1:_(s32) = G_LOAD %0 :: (load 4 from %ir.ptr0)
... ...
--- ---
name: load_global_uniform name: load_global_uniform
legalized: true legalized: true
# CHECK-LABEL: name: load_global_uniform # CHECK-LABEL: name: load_global_uniform
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test/CodeGen/AMDGPU/GlobalISel/smrd.ll

; FIXME: Need to add support for mubuf stores to enable this on SI. ; FIXME: Need to add support for mubuf stores to enable this on SI.
; XUN: llc < %s -march=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s ; XUN: llc < %s -march=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=SI --check-prefix=GCN --check-prefix=SIVI %s
; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=CI --check-prefix=GCN %s ; RUN: llc < %s -march=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=CI --check-prefix=GCN %s
; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s ; RUN: llc < %s -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefix=VI --check-prefix=GCN --check-prefix=SIVI %s
; REQUIRES: global-isel ; REQUIRES: global-isel
; SMRD load with an immediate offset. ; SMRD load with an immediate offset.
; GCN-LABEL: {{^}}smrd0: ; GCN-LABEL: {{^}}smrd0:
; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01 ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) {
entry: entry:
%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 1 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 1
%1 = load i32, i32 addrspace(2)* %0 %1 = load i32, i32 addrspace(4)* %0
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with the largest possible immediate offset. ; SMRD load with the largest possible immediate offset.
; GCN-LABEL: {{^}}smrd1: ; GCN-LABEL: {{^}}smrd1:
; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}} ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) {
entry: entry:
%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 255 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 255
%1 = load i32, i32 addrspace(2)* %0 %1 = load i32, i32 addrspace(4)* %0
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with an offset greater than the largest possible immediate. ; SMRD load with an offset greater than the largest possible immediate.
; GCN-LABEL: {{^}}smrd2: ; GCN-LABEL: {{^}}smrd2:
; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) {
entry: entry:
%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 256 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 256
%1 = load i32, i32 addrspace(2)* %0 %1 = load i32, i32 addrspace(4)* %0
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with a 64-bit offset ; SMRD load with a 64-bit offset
; GCN-LABEL: {{^}}smrd3: ; GCN-LABEL: {{^}}smrd3:
; FIXME: There are too many copies here because we don't fold immediates ; FIXME: There are too many copies here because we don't fold immediates
; through REG_SEQUENCE ; through REG_SEQUENCE
; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b ; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
; TODO: Add VI checks ; TODO: Add VI checks
; XGCN: s_endpgm ; XGCN: s_endpgm
define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) {
entry: entry:
%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 4294967296 ; 2 ^ 32 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 4294967296 ; 2 ^ 32
%1 = load i32, i32 addrspace(2)* %0 %1 = load i32, i32 addrspace(4)* %0
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with the largest possible immediate offset on VI ; SMRD load with the largest possible immediate offset on VI
; GCN-LABEL: {{^}}smrd4: ; GCN-LABEL: {{^}}smrd4:
; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc ; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) {
entry: entry:
%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262143 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262143
%1 = load i32, i32 addrspace(2)* %0 %1 = load i32, i32 addrspace(4)* %0
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with an offset greater than the largest possible immediate on VI ; SMRD load with an offset greater than the largest possible immediate on VI
; GCN-LABEL: {{^}}smrd5: ; GCN-LABEL: {{^}}smrd5:
; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 ; SIVI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) { define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) {
entry: entry:
%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262144 %0 = getelementptr i32, i32 addrspace(4)* %ptr, i64 262144
%1 = load i32, i32 addrspace(2)* %0 %1 = load i32, i32 addrspace(4)* %0
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/add.v2i16.ll

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; GCN-LABEL: {{^}}s_test_add_v2i16: ; GCN-LABEL: {{^}}s_test_add_v2i16:
; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]] ; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]]
; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]] ; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]]
; VI: s_add_i32 ; VI: s_add_i32
; VI: s_add_i32 ; VI: s_add_i32
define amdgpu_kernel void @s_test_add_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %in0, <2 x i16> addrspace(2)* %in1) #1 { define amdgpu_kernel void @s_test_add_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0, <2 x i16> addrspace(4)* %in1) #1 {
%a = load <2 x i16>, <2 x i16> addrspace(2)* %in0 %a = load <2 x i16>, <2 x i16> addrspace(4)* %in0
%b = load <2 x i16>, <2 x i16> addrspace(2)* %in1 %b = load <2 x i16>, <2 x i16> addrspace(4)* %in1
%add = add <2 x i16> %a, %b %add = add <2 x i16> %a, %b
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_test_add_self_v2i16: ; GCN-LABEL: {{^}}s_test_add_self_v2i16:
; GFX9: s_load_dword [[VAL:s[0-9]+]] ; GFX9: s_load_dword [[VAL:s[0-9]+]]
; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL]], [[VAL]] ; GFX9: v_pk_add_u16 v{{[0-9]+}}, [[VAL]], [[VAL]]
; VI: s_add_i32 ; VI: s_add_i32
; VI: s_add_i32 ; VI: s_add_i32
define amdgpu_kernel void @s_test_add_self_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %in0) #1 { define amdgpu_kernel void @s_test_add_self_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0) #1 {
%a = load <2 x i16>, <2 x i16> addrspace(2)* %in0 %a = load <2 x i16>, <2 x i16> addrspace(4)* %in0
%add = add <2 x i16> %a, %a %add = add <2 x i16> %a, %a
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FIXME: VI should not scalarize arg access. ; FIXME: VI should not scalarize arg access.
; GCN-LABEL: {{^}}s_test_add_v2i16_kernarg: ; GCN-LABEL: {{^}}s_test_add_v2i16_kernarg:
; GFX9: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} ; GFX9: v_pk_add_u16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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test/CodeGen/AMDGPU/addrspacecast.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
} }
; no-op ; no-op
; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: ; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} ; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(2)* %ptr to i32* %stof = addrspacecast i32 addrspace(4)* %ptr to i32*
%ld = load volatile i32, i32* %stof %ld = load volatile i32, i32* %stof
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
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} }
; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast:
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 ; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0
define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 { define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32* %ptr to i32 addrspace(2)* %ftos = addrspacecast i32* %ptr to i32 addrspace(4)*
load volatile i32, i32 addrspace(2)* %ftos load volatile i32, i32 addrspace(4)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast:
; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 ; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] ; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
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test/CodeGen/AMDGPU/amdgcn.bitcast.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; This test just checks that the compiler doesn't crash. ; This test just checks that the compiler doesn't crash.
; FUNC-LABEL: {{^}}v32i8_to_v8i32: ; FUNC-LABEL: {{^}}v32i8_to_v8i32:
define amdgpu_ps float @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { define amdgpu_ps float @v32i8_to_v8i32(<32 x i8> addrspace(4)* inreg) #0 {
entry: entry:
%1 = load <32 x i8>, <32 x i8> addrspace(2)* %0 %1 = load <32 x i8>, <32 x i8> addrspace(4)* %0
%2 = bitcast <32 x i8> %1 to <8 x i32> %2 = bitcast <32 x i8> %1 to <8 x i32>
%3 = extractelement <8 x i32> %2, i32 1 %3 = extractelement <8 x i32> %2, i32 1
%4 = icmp ne i32 %3, 0 %4 = icmp ne i32 %3, 0
%5 = select i1 %4, float 0.0, float 1.0 %5 = select i1 %4, float 0.0, float 1.0
ret float %5 ret float %5
} }
; FUNC-LABEL: {{^}}i8ptr_v16i8ptr: ; FUNC-LABEL: {{^}}i8ptr_v16i8ptr:
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test/CodeGen/AMDGPU/amdgpu.private-memory.ll

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; HSA-ALLOCA: s_mov_b32 flat_scratch_lo, s7 ; HSA-ALLOCA: s_mov_b32 flat_scratch_lo, s7
; HSA-ALLOCA: s_add_u32 s6, s6, s9 ; HSA-ALLOCA: s_add_u32 s6, s6, s9
; HSA-ALLOCA: s_lshr_b32 flat_scratch_hi, s6, 8 ; HSA-ALLOCA: s_lshr_b32 flat_scratch_hi, s6, 8
; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 ; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0
; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0 ; SI-ALLOCA: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; encoding: [0x00,0x10,0x70,0xe0
; HSAOPT: [[DISPATCH_PTR:%[0-9]+]] = call noalias nonnull dereferenceable(64) i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() ; HSAOPT: [[DISPATCH_PTR:%[0-9]+]] = call noalias nonnull dereferenceable(64) i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
; HSAOPT: [[CAST_DISPATCH_PTR:%[0-9]+]] = bitcast i8 addrspace(2)* [[DISPATCH_PTR]] to i32 addrspace(2)* ; HSAOPT: [[CAST_DISPATCH_PTR:%[0-9]+]] = bitcast i8 addrspace(4)* [[DISPATCH_PTR]] to i32 addrspace(4)*
; HSAOPT: [[GEP0:%[0-9]+]] = getelementptr inbounds i32, i32 addrspace(2)* [[CAST_DISPATCH_PTR]], i64 1 ; HSAOPT: [[GEP0:%[0-9]+]] = getelementptr inbounds i32, i32 addrspace(4)* [[CAST_DISPATCH_PTR]], i64 1
; HSAOPT: [[LDXY:%[0-9]+]] = load i32, i32 addrspace(2)* [[GEP0]], align 4, !invariant.load !0 ; HSAOPT: [[LDXY:%[0-9]+]] = load i32, i32 addrspace(4)* [[GEP0]], align 4, !invariant.load !0
; HSAOPT: [[GEP1:%[0-9]+]] = getelementptr inbounds i32, i32 addrspace(2)* [[CAST_DISPATCH_PTR]], i64 2 ; HSAOPT: [[GEP1:%[0-9]+]] = getelementptr inbounds i32, i32 addrspace(4)* [[CAST_DISPATCH_PTR]], i64 2
; HSAOPT: [[LDZU:%[0-9]+]] = load i32, i32 addrspace(2)* [[GEP1]], align 4, !range !1, !invariant.load !0 ; HSAOPT: [[LDZU:%[0-9]+]] = load i32, i32 addrspace(4)* [[GEP1]], align 4, !range !1, !invariant.load !0
; HSAOPT: [[EXTRACTY:%[0-9]+]] = lshr i32 [[LDXY]], 16 ; HSAOPT: [[EXTRACTY:%[0-9]+]] = lshr i32 [[LDXY]], 16
; HSAOPT: [[WORKITEM_ID_X:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.x(), !range !2 ; HSAOPT: [[WORKITEM_ID_X:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.x(), !range !2
; HSAOPT: [[WORKITEM_ID_Y:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.y(), !range !2 ; HSAOPT: [[WORKITEM_ID_Y:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.y(), !range !2
; HSAOPT: [[WORKITEM_ID_Z:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.z(), !range !2 ; HSAOPT: [[WORKITEM_ID_Z:%[0-9]+]] = call i32 @llvm.amdgcn.workitem.id.z(), !range !2
; HSAOPT: [[Y_SIZE_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[EXTRACTY]], [[LDZU]] ; HSAOPT: [[Y_SIZE_X_Z_SIZE:%[0-9]+]] = mul nuw nsw i32 [[EXTRACTY]], [[LDZU]]
; HSAOPT: [[YZ_X_XID:%[0-9]+]] = mul i32 [[Y_SIZE_X_Z_SIZE]], [[WORKITEM_ID_X]] ; HSAOPT: [[YZ_X_XID:%[0-9]+]] = mul i32 [[Y_SIZE_X_Z_SIZE]], [[WORKITEM_ID_X]]
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test/CodeGen/AMDGPU/annotate-kernel-features-hsa-call.ll

; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -amdgpu-annotate-kernel-features %s | FileCheck -check-prefix=HSA %s
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0
declare i32 @llvm.amdgcn.workgroup.id.z() #0 declare i32 @llvm.amdgcn.workgroup.id.z() #0
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0
declare i32 @llvm.amdgcn.workitem.id.z() #0 declare i32 @llvm.amdgcn.workitem.id.z() #0
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
declare i64 @llvm.amdgcn.dispatch.id() #0 declare i64 @llvm.amdgcn.dispatch.id() #0
; HSA: define void @use_workitem_id_x() #1 { ; HSA: define void @use_workitem_id_x() #1 {
define void @use_workitem_id_x() #1 { define void @use_workitem_id_x() #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x() %val = call i32 @llvm.amdgcn.workitem.id.x()
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
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define void @use_workgroup_id_z() #1 { define void @use_workgroup_id_z() #1 {
%val = call i32 @llvm.amdgcn.workgroup.id.z() %val = call i32 @llvm.amdgcn.workgroup.id.z()
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
; HSA: define void @use_dispatch_ptr() #7 { ; HSA: define void @use_dispatch_ptr() #7 {
define void @use_dispatch_ptr() #1 { define void @use_dispatch_ptr() #1 {
%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
store volatile i8 addrspace(2)* %dispatch.ptr, i8 addrspace(2)* addrspace(1)* undef store volatile i8 addrspace(4)* %dispatch.ptr, i8 addrspace(4)* addrspace(1)* undef
ret void ret void
} }
; HSA: define void @use_queue_ptr() #8 { ; HSA: define void @use_queue_ptr() #8 {
define void @use_queue_ptr() #1 { define void @use_queue_ptr() #1 {
%queue.ptr = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr() %queue.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
store volatile i8 addrspace(2)* %queue.ptr, i8 addrspace(2)* addrspace(1)* undef store volatile i8 addrspace(4)* %queue.ptr, i8 addrspace(4)* addrspace(1)* undef
ret void ret void
} }
; HSA: define void @use_dispatch_id() #9 { ; HSA: define void @use_dispatch_id() #9 {
define void @use_dispatch_id() #1 { define void @use_dispatch_id() #1 {
%val = call i64 @llvm.amdgcn.dispatch.id() %val = call i64 @llvm.amdgcn.dispatch.id()
store volatile i64 %val, i64 addrspace(1)* undef store volatile i64 %val, i64 addrspace(1)* undef
ret void ret void
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; HSA: define void @call_recursive_use_workitem_id_y() #2 { ; HSA: define void @call_recursive_use_workitem_id_y() #2 {
define void @call_recursive_use_workitem_id_y() #1 { define void @call_recursive_use_workitem_id_y() #1 {
call void @recursive_use_workitem_id_y() call void @recursive_use_workitem_id_y()
ret void ret void
} }
; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #8 { ; HSA: define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #8 {
define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { define void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(2)*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32 addrspace(2)* %stof
ret void ret void
} }
; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #12 { ; HSA: define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #12 {
define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 { define void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* %ptr) #2 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(2)*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32 addrspace(2)* %stof
ret void ret void
} }
; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #13 { ; HSA: define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #13 {
define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 { define void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* %ptr) #2 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(2)*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32 addrspace(2)* %stof
call void @func_indirect_use_queue_ptr() call void @func_indirect_use_queue_ptr()
ret void ret void
} }
; HSA: define void @indirect_use_group_to_flat_addrspacecast() #8 { ; HSA: define void @indirect_use_group_to_flat_addrspacecast() #8 {
define void @indirect_use_group_to_flat_addrspacecast() #1 { define void @indirect_use_group_to_flat_addrspacecast() #1 {
call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null) call void @use_group_to_flat_addrspacecast(i32 addrspace(3)* null)
ret void ret void
} }
; HSA: define void @indirect_use_group_to_flat_addrspacecast_gfx9() #11 { ; HSA: define void @indirect_use_group_to_flat_addrspacecast_gfx9() #11 {
define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 { define void @indirect_use_group_to_flat_addrspacecast_gfx9() #1 {
call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null) call void @use_group_to_flat_addrspacecast_gfx9(i32 addrspace(3)* null)
ret void ret void
} }
; HSA: define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #8 { ; HSA: define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #8 {
define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 { define void @indirect_use_group_to_flat_addrspacecast_queue_ptr_gfx9() #1 {
call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null) call void @use_group_to_flat_addrspacecast_queue_ptr_gfx9(i32 addrspace(3)* null)
ret void ret void
} }
; HSA: define void @use_kernarg_segment_ptr() #14 { ; HSA: define void @use_kernarg_segment_ptr() #14 {
define void @use_kernarg_segment_ptr() #1 { define void @use_kernarg_segment_ptr() #1 {
%kernarg.segment.ptr = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
store volatile i8 addrspace(2)* %kernarg.segment.ptr, i8 addrspace(2)* addrspace(1)* undef store volatile i8 addrspace(4)* %kernarg.segment.ptr, i8 addrspace(4)* addrspace(1)* undef
ret void ret void
} }
; HSA: define void @func_indirect_use_kernarg_segment_ptr() #14 { ; HSA: define void @func_indirect_use_kernarg_segment_ptr() #14 {
define void @func_indirect_use_kernarg_segment_ptr() #1 { define void @func_indirect_use_kernarg_segment_ptr() #1 {
call void @use_kernarg_segment_ptr() call void @use_kernarg_segment_ptr()
ret void ret void
} }
; HSA: define amdgpu_kernel void @kern_use_implicitarg_ptr() #15 { ; HSA: define amdgpu_kernel void @kern_use_implicitarg_ptr() #15 {
define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 { define amdgpu_kernel void @kern_use_implicitarg_ptr() #1 {
%implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
store volatile i8 addrspace(2)* %implicitarg.ptr, i8 addrspace(2)* addrspace(1)* undef store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef
ret void ret void
} }
; HSA: define void @use_implicitarg_ptr() #15 { ; HSA: define void @use_implicitarg_ptr() #15 {
define void @use_implicitarg_ptr() #1 { define void @use_implicitarg_ptr() #1 {
%implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
store volatile i8 addrspace(2)* %implicitarg.ptr, i8 addrspace(2)* addrspace(1)* undef store volatile i8 addrspace(4)* %implicitarg.ptr, i8 addrspace(4)* addrspace(1)* undef
ret void ret void
} }
; HSA: define void @func_indirect_use_implicitarg_ptr() #15 { ; HSA: define void @func_indirect_use_implicitarg_ptr() #15 {
define void @func_indirect_use_implicitarg_ptr() #1 { define void @func_indirect_use_implicitarg_ptr() #1 {
call void @use_implicitarg_ptr() call void @use_implicitarg_ptr()
ret void ret void
} }
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test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll

; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA %s ; RUN: opt -mtriple=amdgcn-unknown-amdhsa -S -amdgpu-annotate-kernel-features < %s | FileCheck -check-prefix=HSA %s
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0
declare i32 @llvm.amdgcn.workgroup.id.z() #0 declare i32 @llvm.amdgcn.workgroup.id.z() #0
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.y() #0 declare i32 @llvm.amdgcn.workitem.id.y() #0
declare i32 @llvm.amdgcn.workitem.id.z() #0 declare i32 @llvm.amdgcn.workitem.id.z() #0
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
declare i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
; HSA: define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 {
define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_tgid_x(i32 addrspace(1)* %ptr) #1 {
%val = call i32 @llvm.amdgcn.workgroup.id.x() %val = call i32 @llvm.amdgcn.workgroup.id.x()
store i32 %val, i32 addrspace(1)* %ptr store i32 %val, i32 addrspace(1)* %ptr
ret void ret void
} }
▲ Show 20 Lines • Show All 122 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @use_all_workitems(i32 addrspace(1)* %ptr) #1 {
store volatile i32 %val3, i32 addrspace(1)* %ptr store volatile i32 %val3, i32 addrspace(1)* %ptr
store volatile i32 %val4, i32 addrspace(1)* %ptr store volatile i32 %val4, i32 addrspace(1)* %ptr
store volatile i32 %val5, i32 addrspace(1)* %ptr store volatile i32 %val5, i32 addrspace(1)* %ptr
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #10 { ; HSA: define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #10 {
define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 {
%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* %bc = bitcast i8 addrspace(4)* %dispatch.ptr to i32 addrspace(4)*
%val = load i32, i32 addrspace(2)* %bc %val = load i32, i32 addrspace(4)* %bc
store i32 %val, i32 addrspace(1)* %ptr store i32 %val, i32 addrspace(1)* %ptr
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_queue_ptr(i32 addrspace(1)* %ptr) #11 { ; HSA: define amdgpu_kernel void @use_queue_ptr(i32 addrspace(1)* %ptr) #11 {
define amdgpu_kernel void @use_queue_ptr(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_queue_ptr(i32 addrspace(1)* %ptr) #1 {
%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.queue.ptr() %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.queue.ptr()
%bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* %bc = bitcast i8 addrspace(4)* %dispatch.ptr to i32 addrspace(4)*
%val = load i32, i32 addrspace(2)* %bc %val = load i32, i32 addrspace(4)* %bc
store i32 %val, i32 addrspace(1)* %ptr store i32 %val, i32 addrspace(1)* %ptr
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_kernarg_segment_ptr(i32 addrspace(1)* %ptr) #12 { ; HSA: define amdgpu_kernel void @use_kernarg_segment_ptr(i32 addrspace(1)* %ptr) #12 {
define amdgpu_kernel void @use_kernarg_segment_ptr(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_kernarg_segment_ptr(i32 addrspace(1)* %ptr) #1 {
%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* %bc = bitcast i8 addrspace(4)* %dispatch.ptr to i32 addrspace(4)*
%val = load i32, i32 addrspace(2)* %bc %val = load i32, i32 addrspace(4)* %bc
store i32 %val, i32 addrspace(1)* %ptr store i32 %val, i32 addrspace(1)* %ptr
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #11 { ; HSA: define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #11 {
define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 0, i32* %stof store volatile i32 0, i32* %stof
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; No-op addrspacecast should not use queue ptr ; No-op addrspacecast should not use queue ptr
; HSA: define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 {
define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(1)* %ptr to i32* %stof = addrspacecast i32 addrspace(1)* %ptr to i32*
store volatile i32 0, i32* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #1 {
define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(4)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(2)* %ptr to i32* %stof = addrspacecast i32 addrspace(4)* %ptr to i32*
%ld = load volatile i32, i32* %stof %ld = load volatile i32, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 { define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32* %ptr to i32 addrspace(1)* %ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
store volatile i32 0, i32 addrspace(1)* %ftos store volatile i32 0, i32 addrspace(1)* %ftos
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 { define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32* %ptr to i32 addrspace(2)* %ftos = addrspacecast i32* %ptr to i32 addrspace(4)*
%ld = load volatile i32, i32 addrspace(2)* %ftos %ld = load volatile i32, i32 addrspace(4)* %ftos
ret void ret void
} }
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind } attributes #1 = { nounwind }
; HSA: attributes #0 = { nounwind readnone speculatable } ; HSA: attributes #0 = { nounwind readnone speculatable }
; HSA: attributes #1 = { nounwind } ; HSA: attributes #1 = { nounwind }
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test/CodeGen/AMDGPU/branch-relaxation.ll

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; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 { define amdgpu_kernel void @expand_requires_expand(i32 %cond0) #0 {
bb0: bb0:
%tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x() #0
%cmp0 = icmp slt i32 %cond0, 0 %cmp0 = icmp slt i32 %cond0, 0
br i1 %cmp0, label %bb2, label %bb1 br i1 %cmp0, label %bb2, label %bb1
bb1: bb1:
%val = load volatile i32, i32 addrspace(2)* undef %val = load volatile i32, i32 addrspace(4)* undef
%cmp1 = icmp eq i32 %val, 3 %cmp1 = icmp eq i32 %val, 3
br i1 %cmp1, label %bb3, label %bb2 br i1 %cmp1, label %bb3, label %bb2
bb2: bb2:
call void asm sideeffect call void asm sideeffect
"v_nop_e64 "v_nop_e64
v_nop_e64 v_nop_e64
v_nop_e64 v_nop_e64
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test/CodeGen/AMDGPU/call-argument-types.ll

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} }
; GCN-LABEL: {{^}}test_call_external_void_func_v8i32: ; GCN-LABEL: {{^}}test_call_external_void_func_v8i32:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 { define amdgpu_kernel void @test_call_external_void_func_v8i32() #0 {
%ptr = load <8 x i32> addrspace(1)*, <8 x i32> addrspace(1)* addrspace(2)* undef %ptr = load <8 x i32> addrspace(1)*, <8 x i32> addrspace(1)* addrspace(4)* undef
%val = load <8 x i32>, <8 x i32> addrspace(1)* %ptr %val = load <8 x i32>, <8 x i32> addrspace(1)* %ptr
call void @external_void_func_v8i32(<8 x i32> %val) call void @external_void_func_v8i32(<8 x i32> %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v16i32: ; GCN-LABEL: {{^}}test_call_external_void_func_v16i32:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 { define amdgpu_kernel void @test_call_external_void_func_v16i32() #0 {
%ptr = load <16 x i32> addrspace(1)*, <16 x i32> addrspace(1)* addrspace(2)* undef %ptr = load <16 x i32> addrspace(1)*, <16 x i32> addrspace(1)* addrspace(4)* undef
%val = load <16 x i32>, <16 x i32> addrspace(1)* %ptr %val = load <16 x i32>, <16 x i32> addrspace(1)* %ptr
call void @external_void_func_v16i32(<16 x i32> %val) call void @external_void_func_v16i32(<16 x i32> %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v32i32: ; GCN-LABEL: {{^}}test_call_external_void_func_v32i32:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN-DAG: buffer_load_dwordx4 v[16:19], off ; GCN-DAG: buffer_load_dwordx4 v[16:19], off
; GCN-DAG: buffer_load_dwordx4 v[20:23], off ; GCN-DAG: buffer_load_dwordx4 v[20:23], off
; GCN-DAG: buffer_load_dwordx4 v[24:27], off ; GCN-DAG: buffer_load_dwordx4 v[24:27], off
; GCN-DAG: buffer_load_dwordx4 v[28:31], off ; GCN-DAG: buffer_load_dwordx4 v[28:31], off
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 { define amdgpu_kernel void @test_call_external_void_func_v32i32() #0 {
%ptr = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(2)* undef %ptr = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef
%val = load <32 x i32>, <32 x i32> addrspace(1)* %ptr %val = load <32 x i32>, <32 x i32> addrspace(1)* %ptr
call void @external_void_func_v32i32(<32 x i32> %val) call void @external_void_func_v32i32(<32 x i32> %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v32i32_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_v32i32_i32:
; HSA-DAG: s_mov_b32 s33, s9 ; HSA-DAG: s_mov_b32 s33, s9
; HSA-NOT: s_add_u32 s32 ; HSA-NOT: s_add_u32 s32
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; GCN-DAG: buffer_load_dwordx4 v[24:27], off ; GCN-DAG: buffer_load_dwordx4 v[24:27], off
; GCN-DAG: buffer_load_dwordx4 v[28:31], off ; GCN-DAG: buffer_load_dwordx4 v[28:31], off
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: buffer_store_dword [[VAL1]], off, s[{{[0-9]+}}:{{[0-9]+}}], s32 offset:4{{$}} ; GCN: buffer_store_dword [[VAL1]], off, s[{{[0-9]+}}:{{[0-9]+}}], s32 offset:4{{$}}
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-NEXT: s_endpgm ; GCN-NEXT: s_endpgm
define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_v32i32_i32(i32) #0 {
%ptr0 = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(2)* undef %ptr0 = load <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef
%val0 = load <32 x i32>, <32 x i32> addrspace(1)* %ptr0 %val0 = load <32 x i32>, <32 x i32> addrspace(1)* %ptr0
%val1 = load i32, i32 addrspace(1)* undef %val1 = load i32, i32 addrspace(1)* undef
call void @external_void_func_v32i32_i32(<32 x i32> %val0, i32 %val1) call void @external_void_func_v32i32_i32(<32 x i32> %val0, i32 %val1)
ret void ret void
} }
; FIXME: No wait after call ; FIXME: No wait after call
; GCN-LABEL: {{^}}test_call_external_i32_func_i32_imm: ; GCN-LABEL: {{^}}test_call_external_i32_func_i32_imm:
; GCN: v_mov_b32_e32 v0, 42 ; GCN: v_mov_b32_e32 v0, 42
; GCN: s_swappc_b64 s[30:31], ; GCN: s_swappc_b64 s[30:31],
; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: buffer_store_dword v0, off, s[36:39], 0 ; GCN-NEXT: buffer_store_dword v0, off, s[36:39], 0
define amdgpu_kernel void @test_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @test_call_external_i32_func_i32_imm(i32 addrspace(1)* %out) #0 {
%val = call i32 @external_i32_func_i32(i32 42) %val = call i32 @external_i32_func_i32(i32 42)
store volatile i32 %val, i32 addrspace(1)* %out store volatile i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_struct_i8_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_struct_i8_i32:
; GCN: buffer_load_ubyte v0, off ; GCN: buffer_load_ubyte v0, off
; GCN: buffer_load_dword v1, off ; GCN: buffer_load_dword v1, off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 { define amdgpu_kernel void @test_call_external_void_func_struct_i8_i32() #0 {
%ptr0 = load { i8, i32 } addrspace(1)*, { i8, i32 } addrspace(1)* addrspace(2)* undef %ptr0 = load { i8, i32 } addrspace(1)*, { i8, i32 } addrspace(1)* addrspace(4)* undef
%val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0 %val = load { i8, i32 }, { i8, i32 } addrspace(1)* %ptr0
call void @external_void_func_struct_i8_i32({ i8, i32 } %val) call void @external_void_func_struct_i8_i32({ i8, i32 } %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_byval_struct_i8_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_byval_struct_i8_i32:
; GCN-DAG: s_add_u32 [[SP:s[0-9]+]], s33, 0x400{{$}} ; GCN-DAG: s_add_u32 [[SP:s[0-9]+]], s33, 0x400{{$}}
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store volatile i8 %out.val0, i8 addrspace(1)* undef store volatile i8 %out.val0, i8 addrspace(1)* undef
store volatile i32 %out.val1, i32 addrspace(1)* undef store volatile i32 %out.val1, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v16i8: ; GCN-LABEL: {{^}}test_call_external_void_func_v16i8:
define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 { define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
%ptr = load <16 x i8> addrspace(1)*, <16 x i8> addrspace(1)* addrspace(2)* undef %ptr = load <16 x i8> addrspace(1)*, <16 x i8> addrspace(1)* addrspace(4)* undef
%val = load <16 x i8>, <16 x i8> addrspace(1)* %ptr %val = load <16 x i8>, <16 x i8> addrspace(1)* %ptr
call void @external_void_func_v16i8(<16 x i8> %val) call void @external_void_func_v16i8(<16 x i8> %val)
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind noinline } attributes #2 = { nounwind noinline }
Context not available.

test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CIVI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}use_dispatch_ptr: ; GCN-LABEL: {{^}}use_dispatch_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0
define void @use_dispatch_ptr() #1 { define void @use_dispatch_ptr() #1 {
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
%header_ptr = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %header_ptr = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
%value = load volatile i32, i32 addrspace(2)* %header_ptr %value = load volatile i32, i32 addrspace(4)* %header_ptr
ret void ret void
} }
; GCN-LABEL: {{^}}kern_indirect_use_dispatch_ptr: ; GCN-LABEL: {{^}}kern_indirect_use_dispatch_ptr:
; GCN: enable_sgpr_dispatch_ptr = 1 ; GCN: enable_sgpr_dispatch_ptr = 1
; GCN: s_mov_b64 s[6:7], s[4:5] ; GCN: s_mov_b64 s[6:7], s[4:5]
define amdgpu_kernel void @kern_indirect_use_dispatch_ptr(i32) #1 { define amdgpu_kernel void @kern_indirect_use_dispatch_ptr(i32) #1 {
call void @use_dispatch_ptr() call void @use_dispatch_ptr()
ret void ret void
} }
; GCN-LABEL: {{^}}use_queue_ptr: ; GCN-LABEL: {{^}}use_queue_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0
define void @use_queue_ptr() #1 { define void @use_queue_ptr() #1 {
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
%header_ptr = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %header_ptr = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
%value = load volatile i32, i32 addrspace(2)* %header_ptr %value = load volatile i32, i32 addrspace(4)* %header_ptr
ret void ret void
} }
; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr: ; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr:
; GCN: enable_sgpr_queue_ptr = 1 ; GCN: enable_sgpr_queue_ptr = 1
; GCN: s_mov_b64 s[6:7], s[4:5] ; GCN: s_mov_b64 s[6:7], s[4:5]
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kern_indirect_use_queue_ptr(i32) #1 { define amdgpu_kernel void @kern_indirect_use_queue_ptr(i32) #1 {
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define amdgpu_kernel void @kern_indirect_use_queue_ptr_addrspacecast(i32) #1 { define amdgpu_kernel void @kern_indirect_use_queue_ptr_addrspacecast(i32) #1 {
call void @use_queue_ptr_addrspacecast() call void @use_queue_ptr_addrspacecast()
ret void ret void
} }
; GCN-LABEL: {{^}}use_kernarg_segment_ptr: ; GCN-LABEL: {{^}}use_kernarg_segment_ptr:
; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0
define void @use_kernarg_segment_ptr() #1 { define void @use_kernarg_segment_ptr() #1 {
%kernarg_segment_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
%header_ptr = bitcast i8 addrspace(2)* %kernarg_segment_ptr to i32 addrspace(2)* %header_ptr = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
%value = load volatile i32, i32 addrspace(2)* %header_ptr %value = load volatile i32, i32 addrspace(4)* %header_ptr
ret void ret void
} }
; GCN-LABEL: {{^}}kern_indirect_use_kernarg_segment_ptr: ; GCN-LABEL: {{^}}kern_indirect_use_kernarg_segment_ptr:
; GCN: enable_sgpr_kernarg_segment_ptr = 1 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
; GCN: s_mov_b64 s[6:7], s[4:5] ; GCN: s_mov_b64 s[6:7], s[4:5]
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kern_indirect_use_kernarg_segment_ptr(i32) #1 { define amdgpu_kernel void @kern_indirect_use_kernarg_segment_ptr(i32) #1 {
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; GCN: ; use s[12:13] ; GCN: ; use s[12:13]
; GCN: ; use s14 ; GCN: ; use s14
; GCN: ; use s15 ; GCN: ; use s15
; GCN: ; use s16 ; GCN: ; use s16
define void @use_every_sgpr_input() #1 { define void @use_every_sgpr_input() #1 {
%alloca = alloca i32, align 4, addrspace(5) %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
%val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
%queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
%val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
%kernarg_segment_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
%kernarg_segment_ptr.bc = bitcast i8 addrspace(2)* %kernarg_segment_ptr to i32 addrspace(2)* %kernarg_segment_ptr.bc = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
%val2 = load volatile i32, i32 addrspace(2)* %kernarg_segment_ptr.bc %val2 = load volatile i32, i32 addrspace(4)* %kernarg_segment_ptr.bc
%val3 = call i64 @llvm.amdgcn.dispatch.id() %val3 = call i64 @llvm.amdgcn.dispatch.id()
call void asm sideeffect "; use $0", "s"(i64 %val3) call void asm sideeffect "; use $0", "s"(i64 %val3)
%val4 = call i32 @llvm.amdgcn.workgroup.id.x() %val4 = call i32 @llvm.amdgcn.workgroup.id.x()
call void asm sideeffect "; use $0", "s"(i32 %val4) call void asm sideeffect "; use $0", "s"(i32 %val4)
%val5 = call i32 @llvm.amdgcn.workgroup.id.y() %val5 = call i32 @llvm.amdgcn.workgroup.id.y()
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; GCN-DAG: s_mov_b32 s6, s14 ; GCN-DAG: s_mov_b32 s6, s14
; GCN-DAG: s_mov_b32 s7, s15 ; GCN-DAG: s_mov_b32 s7, s15
; GCN-DAG: s_mov_b32 s8, s16 ; GCN-DAG: s_mov_b32 s8, s16
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 { define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 {
%alloca = alloca i32, align 4, addrspace(5) %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
%val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
%queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
%val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
%kernarg_segment_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
%kernarg_segment_ptr.bc = bitcast i8 addrspace(2)* %kernarg_segment_ptr to i32 addrspace(2)* %kernarg_segment_ptr.bc = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
%val2 = load volatile i32, i32 addrspace(2)* %kernarg_segment_ptr.bc %val2 = load volatile i32, i32 addrspace(4)* %kernarg_segment_ptr.bc
%val3 = call i64 @llvm.amdgcn.dispatch.id() %val3 = call i64 @llvm.amdgcn.dispatch.id()
call void asm sideeffect "; use $0", "s"(i64 %val3) call void asm sideeffect "; use $0", "s"(i64 %val3)
%val4 = call i32 @llvm.amdgcn.workgroup.id.x() %val4 = call i32 @llvm.amdgcn.workgroup.id.x()
call void asm sideeffect "; use $0", "s"(i32 %val4) call void asm sideeffect "; use $0", "s"(i32 %val4)
%val5 = call i32 @llvm.amdgcn.workgroup.id.y() %val5 = call i32 @llvm.amdgcn.workgroup.id.y()
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; GCN: ; use [[SAVE_Y]] ; GCN: ; use [[SAVE_Y]]
; GCN: ; use [[SAVE_Z]] ; GCN: ; use [[SAVE_Z]]
define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 { define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 {
%alloca = alloca i32, align 4, addrspace(5) %alloca = alloca i32, align 4, addrspace(5)
call void @use_workgroup_id_xyz() call void @use_workgroup_id_xyz()
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
%val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc %val0 = load volatile i32, i32 addrspace(4)* %dispatch_ptr.bc
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
%queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %queue_ptr.bc = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
%val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc %val1 = load volatile i32, i32 addrspace(4)* %queue_ptr.bc
%kernarg_segment_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 %kernarg_segment_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
%kernarg_segment_ptr.bc = bitcast i8 addrspace(2)* %kernarg_segment_ptr to i32 addrspace(2)* %kernarg_segment_ptr.bc = bitcast i8 addrspace(4)* %kernarg_segment_ptr to i32 addrspace(4)*
%val2 = load volatile i32, i32 addrspace(2)* %kernarg_segment_ptr.bc %val2 = load volatile i32, i32 addrspace(4)* %kernarg_segment_ptr.bc
%val3 = call i64 @llvm.amdgcn.dispatch.id() %val3 = call i64 @llvm.amdgcn.dispatch.id()
call void asm sideeffect "; use $0", "s"(i64 %val3) call void asm sideeffect "; use $0", "s"(i64 %val3)
%val4 = call i32 @llvm.amdgcn.workgroup.id.x() %val4 = call i32 @llvm.amdgcn.workgroup.id.x()
call void asm sideeffect "; use $0", "s"(i32 %val4) call void asm sideeffect "; use $0", "s"(i32 %val4)
%val5 = call i32 @llvm.amdgcn.workgroup.id.y() %val5 = call i32 @llvm.amdgcn.workgroup.id.y()
call void asm sideeffect "; use $0", "s"(i32 %val5) call void asm sideeffect "; use $0", "s"(i32 %val5)
%val6 = call i32 @llvm.amdgcn.workgroup.id.z() %val6 = call i32 @llvm.amdgcn.workgroup.id.z()
call void asm sideeffect "; use $0", "s"(i32 %val6) call void asm sideeffect "; use $0", "s"(i32 %val6)
ret void ret void
} }
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workgroup.id.y() #0 declare i32 @llvm.amdgcn.workgroup.id.y() #0
declare i32 @llvm.amdgcn.workgroup.id.z() #0 declare i32 @llvm.amdgcn.workgroup.id.z() #0
declare noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
declare noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 declare noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
declare i64 @llvm.amdgcn.dispatch.id() #0 declare i64 @llvm.amdgcn.dispatch.id() #0
declare noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind noinline } attributes #1 = { nounwind noinline }
Context not available.

test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll

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; OPT: br label ; OPT: br label
; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32: ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32:
; CI: s_load_dword {{s[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; CI: s_load_dword {{s[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_constant_i32(i32* %out, i32* %in, i32 %cond) { define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_constant_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%cast = addrspacecast i32* %in.gep to i32 addrspace(2)* %cast = addrspacecast i32* %in.gep to i32 addrspace(4)*
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %cast %tmp1 = load i32, i32 addrspace(4)* %cast
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
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test/CodeGen/AMDGPU/cgp-addressing-modes.ll

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store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_constant_small_offset_i32 ; OPT-LABEL: @test_sink_constant_small_offset_i32
; OPT-NOT: getelementptr i32, i32 addrspace(2)* ; OPT-NOT: getelementptr i32, i32 addrspace(4)*
; OPT: br i1 ; OPT: br i1
; GCN-LABEL: {{^}}test_sink_constant_small_offset_i32: ; GCN-LABEL: {{^}}test_sink_constant_small_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x7{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x7{{$}}
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define amdgpu_kernel void @test_sink_constant_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 7 %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %in.gep %tmp1 = load i32, i32 addrspace(4)* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_constant_max_8_bit_offset_i32 ; OPT-LABEL: @test_sink_constant_max_8_bit_offset_i32
; OPT-NOT: getelementptr i32, i32 addrspace(2)* ; OPT-NOT: getelementptr i32, i32 addrspace(4)*
; OPT: br i1 ; OPT: br i1
; GCN-LABEL: {{^}}test_sink_constant_max_8_bit_offset_i32: ; GCN-LABEL: {{^}}test_sink_constant_max_8_bit_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xff{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xff{{$}}
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define amdgpu_kernel void @test_sink_constant_max_8_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_max_8_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 255 %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 255
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %in.gep %tmp1 = load i32, i32 addrspace(4)* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_constant_max_8_bit_offset_p1_i32 ; OPT-LABEL: @test_sink_constant_max_8_bit_offset_p1_i32
; OPT-SI: getelementptr i32, i32 addrspace(2)* ; OPT-SI: getelementptr i32, i32 addrspace(4)*
; OPT-CI-NOT: getelementptr i32, i32 addrspace(2)* ; OPT-CI-NOT: getelementptr i32, i32 addrspace(4)*
; OPT-VI-NOT: getelementptr i32, i32 addrspace(2)* ; OPT-VI-NOT: getelementptr i32, i32 addrspace(4)*
; OPT: br i1 ; OPT: br i1
; GCN-LABEL: {{^}}test_sink_constant_max_8_bit_offset_p1_i32: ; GCN-LABEL: {{^}}test_sink_constant_max_8_bit_offset_p1_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x400 ; SI: s_movk_i32 [[OFFSET:s[0-9]+]], 0x400
; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define amdgpu_kernel void @test_sink_constant_max_8_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_max_8_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 256 %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 256
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %in.gep %tmp1 = load i32, i32 addrspace(4)* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_constant_max_32_bit_offset_i32 ; OPT-LABEL: @test_sink_constant_max_32_bit_offset_i32
; OPT-SI: getelementptr i32, i32 addrspace(2)* ; OPT-SI: getelementptr i32, i32 addrspace(4)*
; OPT-CI-NOT: getelementptr i32, i32 addrspace(2)* ; OPT-CI-NOT: getelementptr i32, i32 addrspace(4)*
; OPT: br i1 ; OPT: br i1
; GCN-LABEL: {{^}}test_sink_constant_max_32_bit_offset_i32: ; GCN-LABEL: {{^}}test_sink_constant_max_32_bit_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, -4{{$}} ; GCN: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, -4{{$}}
; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 3{{$}} ; GCN: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 3{{$}}
; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define amdgpu_kernel void @test_sink_constant_max_32_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_max_32_bit_offset_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 4294967295 %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 4294967295
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %in.gep %tmp1 = load i32, i32 addrspace(4)* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_constant_max_32_bit_offset_p1_i32 ; OPT-LABEL: @test_sink_constant_max_32_bit_offset_p1_i32
; OPT: getelementptr i32, i32 addrspace(2)* ; OPT: getelementptr i32, i32 addrspace(4)*
; OPT: br i1 ; OPT: br i1
; GCN-LABEL: {{^}}test_sink_constant_max_32_bit_offset_p1_i32: ; GCN-LABEL: {{^}}test_sink_constant_max_32_bit_offset_p1_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: s_add_u32 ; GCN: s_add_u32
; GCN: s_addc_u32 ; GCN: s_addc_u32
; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define amdgpu_kernel void @test_sink_constant_max_32_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_max_32_bit_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 17179869181 %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 17179869181
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %in.gep %tmp1 = load i32, i32 addrspace(4)* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; GCN-LABEL: {{^}}test_sink_constant_max_20_bit_byte_offset_i32: ; GCN-LABEL: {{^}}test_sink_constant_max_20_bit_byte_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc{{$}} ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc{{$}}
; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
; CI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x3ffff{{$}} ; CI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x3ffff{{$}}
; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xffffc{{$}} ; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0xffffc{{$}}
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define amdgpu_kernel void @test_sink_constant_max_20_bit_byte_offset_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_max_20_bit_byte_offset_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 262143 %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 262143
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %in.gep %tmp1 = load i32, i32 addrspace(4)* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_constant_max_20_bit_byte_offset_p1_i32 ; OPT-LABEL: @test_sink_constant_max_20_bit_byte_offset_p1_i32
; OPT-SI: getelementptr i32, i32 addrspace(2)* ; OPT-SI: getelementptr i32, i32 addrspace(4)*
; OPT-CI-NOT: getelementptr i32, i32 addrspace(2)* ; OPT-CI-NOT: getelementptr i32, i32 addrspace(4)*
; OPT-VI: getelementptr i32, i32 addrspace(2)* ; OPT-VI: getelementptr i32, i32 addrspace(4)*
; OPT: br i1 ; OPT: br i1
; GCN-LABEL: {{^}}test_sink_constant_max_20_bit_byte_offset_p1_i32: ; GCN-LABEL: {{^}}test_sink_constant_max_20_bit_byte_offset_p1_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000{{$}} ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000{{$}}
; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}} ; SI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
; CI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x40000{{$}} ; CI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0x40000{{$}}
; VI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000{{$}} ; VI: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000{{$}}
; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}} ; VI: s_load_dword s{{[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, [[OFFSET]]{{$}}
; GCN: s_or_b64 exec, exec ; GCN: s_or_b64 exec, exec
define amdgpu_kernel void @test_sink_constant_max_20_bit_byte_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_max_20_bit_byte_offset_p1_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(2)* %in, i64 262144 %in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 262144
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %in.gep %tmp1 = load i32, i32 addrspace(4)* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
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; Address offset is not a multiple of 4. This is a valid mubuf offset, ; Address offset is not a multiple of 4. This is a valid mubuf offset,
; but not smrd. ; but not smrd.
; OPT-LABEL: @test_sink_constant_small_max_mubuf_offset_load_i32_align_1( ; OPT-LABEL: @test_sink_constant_small_max_mubuf_offset_load_i32_align_1(
; OPT: br i1 %tmp0, ; OPT: br i1 %tmp0,
; OPT: if: ; OPT: if:
; OPT: getelementptr i8, {{.*}} 4095 ; OPT: getelementptr i8, {{.*}} 4095
define amdgpu_kernel void @test_sink_constant_small_max_mubuf_offset_load_i32_align_1(i32 addrspace(1)* %out, i8 addrspace(2)* %in) { define amdgpu_kernel void @test_sink_constant_small_max_mubuf_offset_load_i32_align_1(i32 addrspace(1)* %out, i8 addrspace(4)* %in) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024 %out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 1024
%in.gep = getelementptr i8, i8 addrspace(2)* %in, i64 4095 %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4095
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%bitcast = bitcast i8 addrspace(2)* %in.gep to i32 addrspace(2)* %bitcast = bitcast i8 addrspace(4)* %in.gep to i32 addrspace(4)*
%tmp1 = load i32, i32 addrspace(2)* %bitcast, align 1 %tmp1 = load i32, i32 addrspace(4)* %bitcast, align 1
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep store i32 %x, i32 addrspace(1)* %out.gep
br label %done br label %done
done: done:
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test/CodeGen/AMDGPU/early-if-convert-cost.ll

Show All 26 Lines
} }
; vcc branch with SGPR inputs ; vcc branch with SGPR inputs
; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle64: ; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle64:
; GCN: v_cmp_neq_f64 ; GCN: v_cmp_neq_f64
; GCN: v_add_f64 ; GCN: v_add_f64
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
; GCN: v_cndmask_b32_e32 ; GCN: v_cndmask_b32_e32
define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(2)* %in) #0 { define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle64(double addrspace(1)* %out, double addrspace(4)* %in) #0 {
entry: entry:
%v = load double, double addrspace(2)* %in %v = load double, double addrspace(4)* %in
%cc = fcmp oeq double %v, 1.000000e+00 %cc = fcmp oeq double %v, 1.000000e+00
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = fadd double %v, %v %u = fadd double %v, %v
br label %endif br label %endif
endif: endif:
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test/CodeGen/AMDGPU/early-if-convert.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle: ; GCN-LABEL: {{^}}test_vccnz_sgpr_ifcvt_triangle:
; GCN: v_cmp_neq_f32_e64 ; GCN: v_cmp_neq_f32_e64
; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]] ; GCN: s_cbranch_vccnz [[ENDIF:BB[0-9]+_[0-9]+]]
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: [[ENDIF]]: ; GCN: [[ENDIF]]:
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle(i32 addrspace(1)* %out, i32 addrspace(2)* %in, float %cnd) #0 { define amdgpu_kernel void @test_vccnz_sgpr_ifcvt_triangle(i32 addrspace(1)* %out, i32 addrspace(4)* %in, float %cnd) #0 {
entry: entry:
%v = load i32, i32 addrspace(2)* %in %v = load i32, i32 addrspace(4)* %in
%cc = fcmp oeq float %cnd, 1.000000e+00 %cc = fcmp oeq float %cnd, 1.000000e+00
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = add i32 %v, %v %u = add i32 %v, %v
br label %endif br label %endif
endif: endif:
%r = phi i32 [ %v, %entry ], [ %u, %if ] %r = phi i32 [ %v, %entry ], [ %u, %if ]
store i32 %r, i32 addrspace(1)* %out store i32 %r, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_constant_load: ; GCN-LABEL: {{^}}test_vccnz_ifcvt_triangle_constant_load:
; GCN: v_cndmask_b32 ; GCN: v_cndmask_b32
define amdgpu_kernel void @test_vccnz_ifcvt_triangle_constant_load(float addrspace(1)* %out, float addrspace(2)* %in) #0 { define amdgpu_kernel void @test_vccnz_ifcvt_triangle_constant_load(float addrspace(1)* %out, float addrspace(4)* %in) #0 {
entry: entry:
%v = load float, float addrspace(2)* %in %v = load float, float addrspace(4)* %in
%cc = fcmp oeq float %v, 1.000000e+00 %cc = fcmp oeq float %v, 1.000000e+00
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = fadd float %v, %v %u = fadd float %v, %v
br label %endif br label %endif
endif: endif:
Show All 23 Lines
} }
; Scalar branch and scalar inputs ; Scalar branch and scalar inputs
; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle: ; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle:
; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0 ; GCN: s_load_dword [[VAL:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0x0
; GCN: s_add_i32 [[ADD:s[0-9]+]], [[VAL]], [[VAL]] ; GCN: s_add_i32 [[ADD:s[0-9]+]], [[VAL]], [[VAL]]
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
; GCN-NEXT: s_cselect_b32 [[SELECT:s[0-9]+]], [[ADD]], [[VAL]] ; GCN-NEXT: s_cselect_b32 [[SELECT:s[0-9]+]], [[ADD]], [[VAL]]
define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle(i32 addrspace(2)* %in, i32 %cond) #0 { define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle(i32 addrspace(4)* %in, i32 %cond) #0 {
entry: entry:
%v = load i32, i32 addrspace(2)* %in %v = load i32, i32 addrspace(4)* %in
%cc = icmp eq i32 %cond, 1 %cc = icmp eq i32 %cond, 1
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = add i32 %v, %v %u = add i32 %v, %v
br label %endif br label %endif
endif: endif:
Show All 28 Lines
ret void ret void
} }
; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle64: ; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle64:
; GCN: s_add_u32 ; GCN: s_add_u32
; GCN: s_addc_u32 ; GCN: s_addc_u32
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle64(i64 addrspace(2)* %in, i32 %cond) #0 { define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle64(i64 addrspace(4)* %in, i32 %cond) #0 {
entry: entry:
%v = load i64, i64 addrspace(2)* %in %v = load i64, i64 addrspace(4)* %in
%cc = icmp eq i32 %cond, 1 %cc = icmp eq i32 %cond, 1
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = add i64 %v, %v %u = add i64 %v, %v
br label %endif br label %endif
endif: endif:
%r = phi i64 [ %v, %entry ], [ %u, %if ] %r = phi i64 [ %v, %entry ], [ %u, %if ]
call void asm sideeffect "; reg use $0", "s"(i64 %r) #0 call void asm sideeffect "; reg use $0", "s"(i64 %r) #0
ret void ret void
} }
; TODO: Can do s_cselect_b64; s_cselect_b32 ; TODO: Can do s_cselect_b64; s_cselect_b32
; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle96: ; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle96:
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle96(<3 x i32> addrspace(2)* %in, i32 %cond) #0 { define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle96(<3 x i32> addrspace(4)* %in, i32 %cond) #0 {
entry: entry:
%v = load <3 x i32>, <3 x i32> addrspace(2)* %in %v = load <3 x i32>, <3 x i32> addrspace(4)* %in
%cc = icmp eq i32 %cond, 1 %cc = icmp eq i32 %cond, 1
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = add <3 x i32> %v, %v %u = add <3 x i32> %v, %v
br label %endif br label %endif
endif: endif:
%r = phi <3 x i32> [ %v, %entry ], [ %u, %if ] %r = phi <3 x i32> [ %v, %entry ], [ %u, %if ]
%r.ext = shufflevector <3 x i32> %r, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3> %r.ext = shufflevector <3 x i32> %r, <3 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
call void asm sideeffect "; reg use $0", "s"(<4 x i32> %r.ext) #0 call void asm sideeffect "; reg use $0", "s"(<4 x i32> %r.ext) #0
ret void ret void
} }
; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle128: ; GCN-LABEL: {{^}}test_scc1_sgpr_ifcvt_triangle128:
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_add_i32 ; GCN: s_add_i32
; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1 ; GCN: s_cmp_lg_u32 s{{[0-9]+}}, 1
; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}} ; GCN-NEXT: s_cselect_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}
define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle128(<4 x i32> addrspace(2)* %in, i32 %cond) #0 { define amdgpu_kernel void @test_scc1_sgpr_ifcvt_triangle128(<4 x i32> addrspace(4)* %in, i32 %cond) #0 {
entry: entry:
%v = load <4 x i32>, <4 x i32> addrspace(2)* %in %v = load <4 x i32>, <4 x i32> addrspace(4)* %in
%cc = icmp eq i32 %cond, 1 %cc = icmp eq i32 %cond, 1
br i1 %cc, label %if, label %endif br i1 %cc, label %if, label %endif
if: if:
%u = add <4 x i32> %v, %v %u = add <4 x i32> %v, %v
br label %endif br label %endif
endif: endif:
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test/CodeGen/AMDGPU/extract_vector_elt-f16.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; GCN-LABEL: {{^}}extract_vector_elt_v2f16: ; GCN-LABEL: {{^}}extract_vector_elt_v2f16:
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]] ; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
; GCN-DAG: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]] ; GCN-DAG: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
; GCN-DAG: buffer_store_short [[VELT0]] ; GCN-DAG: buffer_store_short [[VELT0]]
; GCN-DAG: buffer_store_short [[VELT1]] ; GCN-DAG: buffer_store_short [[VELT1]]
define amdgpu_kernel void @extract_vector_elt_v2f16(half addrspace(1)* %out, <2 x half> addrspace(2)* %vec.ptr) #0 { define amdgpu_kernel void @extract_vector_elt_v2f16(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr) #0 {
%vec = load <2 x half>, <2 x half> addrspace(2)* %vec.ptr %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
%p0 = extractelement <2 x half> %vec, i32 0 %p0 = extractelement <2 x half> %vec, i32 0
%p1 = extractelement <2 x half> %vec, i32 1 %p1 = extractelement <2 x half> %vec, i32 1
%out1 = getelementptr half, half addrspace(1)* %out, i32 10 %out1 = getelementptr half, half addrspace(1)* %out, i32 10
store half %p1, half addrspace(1)* %out, align 2 store half %p1, half addrspace(1)* %out, align 2
store half %p0, half addrspace(1)* %out1, align 2 store half %p0, half addrspace(1)* %out1, align 2
ret void ret void
} }
; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_sgpr: ; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_sgpr:
; GCN: s_load_dword [[IDX:s[0-9]+]] ; GCN: s_load_dword [[IDX:s[0-9]+]]
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 16 ; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 16
; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]] ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
; GCN: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]] ; GCN: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
; GCN: buffer_store_short [[VELT1]] ; GCN: buffer_store_short [[VELT1]]
; GCN: ScratchSize: 0 ; GCN: ScratchSize: 0
define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_sgpr(half addrspace(1)* %out, <2 x half> addrspace(2)* %vec.ptr, i32 %idx) #0 { define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_sgpr(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr, i32 %idx) #0 {
%vec = load <2 x half>, <2 x half> addrspace(2)* %vec.ptr %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
%elt = extractelement <2 x half> %vec, i32 %idx %elt = extractelement <2 x half> %vec, i32 %idx
store half %elt, half addrspace(1)* %out, align 2 store half %elt, half addrspace(1)* %out, align 2
ret void ret void
} }
; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_vgpr: ; GCN-LABEL: {{^}}extract_vector_elt_v2f16_dynamic_vgpr:
; GCN-DAG: s_load_dword [[VEC:s[0-9]+]] ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
; GCN-DAG: {{flat|buffer}}_load_dword [[IDX:v[0-9]+]] ; GCN-DAG: {{flat|buffer}}_load_dword [[IDX:v[0-9]+]]
; GCN: v_lshlrev_b32_e32 [[IDX_SCALED:v[0-9]+]], 16, [[IDX]] ; GCN: v_lshlrev_b32_e32 [[IDX_SCALED:v[0-9]+]], 16, [[IDX]]
; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]] ; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]] ; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
; SI: buffer_store_short [[ELT]] ; SI: buffer_store_short [[ELT]]
; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[ELT]] ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[ELT]]
; GCN: ScratchSize: 0{{$}} ; GCN: ScratchSize: 0{{$}}
define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_vgpr(half addrspace(1)* %out, <2 x half> addrspace(2)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 { define amdgpu_kernel void @extract_vector_elt_v2f16_dynamic_vgpr(half addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext %gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds half, half addrspace(1)* %out, i64 %tid.ext
%vec = load <2 x half>, <2 x half> addrspace(2)* %vec.ptr %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
%idx = load i32, i32 addrspace(1)* %gep %idx = load i32, i32 addrspace(1)* %gep
%elt = extractelement <2 x half> %vec, i32 %idx %elt = extractelement <2 x half> %vec, i32 %idx
store half %elt, half addrspace(1)* %out.gep, align 2 store half %elt, half addrspace(1)* %out.gep, align 2
ret void ret void
} }
; GCN-LABEL: {{^}}extract_vector_elt_v3f16: ; GCN-LABEL: {{^}}extract_vector_elt_v3f16:
; GCN: buffer_load_ushort ; GCN: buffer_load_ushort
▲ Show 20 Lines • Show All 67 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/extract_vector_elt-i16.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s
; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; GCN-LABEL: {{^}}extract_vector_elt_v2i16: ; GCN-LABEL: {{^}}extract_vector_elt_v2i16:
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16 ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]] ; GCN-DAG: v_mov_b32_e32 [[VELT0:v[0-9]+]], [[VEC]]
; GCN-DAG: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]] ; GCN-DAG: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
; GCN-DAG: buffer_store_short [[VELT0]] ; GCN-DAG: buffer_store_short [[VELT0]]
; GCN-DAG: buffer_store_short [[VELT1]] ; GCN-DAG: buffer_store_short [[VELT1]]
define amdgpu_kernel void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr) #0 { define amdgpu_kernel void @extract_vector_elt_v2i16(i16 addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%p0 = extractelement <2 x i16> %vec, i32 0 %p0 = extractelement <2 x i16> %vec, i32 0
%p1 = extractelement <2 x i16> %vec, i32 1 %p1 = extractelement <2 x i16> %vec, i32 1
%out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10 %out1 = getelementptr i16, i16 addrspace(1)* %out, i32 10
store i16 %p1, i16 addrspace(1)* %out, align 2 store i16 %p1, i16 addrspace(1)* %out, align 2
store i16 %p0, i16 addrspace(1)* %out1, align 2 store i16 %p0, i16 addrspace(1)* %out1, align 2
ret void ret void
} }
; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_sgpr: ; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_sgpr:
; GCN: s_load_dword [[IDX:s[0-9]+]] ; GCN: s_load_dword [[IDX:s[0-9]+]]
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 16 ; GCN: s_lshl_b32 [[IDX_SCALED:s[0-9]+]], [[IDX]], 16
; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]] ; GCN: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], [[IDX_SCALED]]
; GCN: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]] ; GCN: v_mov_b32_e32 [[VELT1:v[0-9]+]], [[ELT1]]
; GCN: buffer_store_short [[VELT1]] ; GCN: buffer_store_short [[VELT1]]
; GCN: ScratchSize: 0 ; GCN: ScratchSize: 0
define amdgpu_kernel void @extract_vector_elt_v2i16_dynamic_sgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %idx) #0 { define amdgpu_kernel void @extract_vector_elt_v2i16_dynamic_sgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %idx) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt = extractelement <2 x i16> %vec, i32 %idx %elt = extractelement <2 x i16> %vec, i32 %idx
store i16 %elt, i16 addrspace(1)* %out, align 2 store i16 %elt, i16 addrspace(1)* %out, align 2
ret void ret void
} }
; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_vgpr: ; GCN-LABEL: {{^}}extract_vector_elt_v2i16_dynamic_vgpr:
; GCN-DAG: s_load_dword [[VEC:s[0-9]+]] ; GCN-DAG: s_load_dword [[VEC:s[0-9]+]]
; GCN-DAG: {{flat|buffer|global}}_load_dword [[IDX:v[0-9]+]] ; GCN-DAG: {{flat|buffer|global}}_load_dword [[IDX:v[0-9]+]]
; GCN: v_lshlrev_b32_e32 [[IDX_SCALED:v[0-9]+]], 16, [[IDX]] ; GCN: v_lshlrev_b32_e32 [[IDX_SCALED:v[0-9]+]], 16, [[IDX]]
; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]] ; SI: v_lshr_b32_e32 [[ELT:v[0-9]+]], [[VEC]], [[IDX_SCALED]]
; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]] ; VI: v_lshrrev_b32_e64 [[ELT:v[0-9]+]], [[IDX_SCALED]], [[VEC]]
; SI: buffer_store_short [[ELT]] ; SI: buffer_store_short [[ELT]]
; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[ELT]] ; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[ELT]]
; GCN: ScratchSize: 0{{$}} ; GCN: ScratchSize: 0{{$}}
define amdgpu_kernel void @extract_vector_elt_v2i16_dynamic_vgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 { define amdgpu_kernel void @extract_vector_elt_v2i16_dynamic_vgpr(i16 addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 addrspace(1)* %idx.ptr) #0 {
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%tid.ext = sext i32 %tid to i64 %tid.ext = sext i32 %tid to i64
%gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext %gep = getelementptr inbounds i32, i32 addrspace(1)* %idx.ptr, i64 %tid.ext
%out.gep = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext %out.gep = getelementptr inbounds i16, i16 addrspace(1)* %out, i64 %tid.ext
%idx = load volatile i32, i32 addrspace(1)* %gep %idx = load volatile i32, i32 addrspace(1)* %gep
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt = extractelement <2 x i16> %vec, i32 %idx %elt = extractelement <2 x i16> %vec, i32 %idx
store i16 %elt, i16 addrspace(1)* %out.gep, align 2 store i16 %elt, i16 addrspace(1)* %out.gep, align 2
ret void ret void
} }
; GCN-LABEL: {{^}}extract_vector_elt_v3i16: ; GCN-LABEL: {{^}}extract_vector_elt_v3i16:
; GCN: buffer_load_ushort ; GCN: buffer_load_ushort
; GCN: buffer_store_short ; GCN: buffer_store_short
▲ Show 20 Lines • Show All 87 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/fence-barrier.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs | FileCheck --check-prefix=GCN %s ; RUN: llvm-as -data-layout=A5 < %s | llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx803 -enable-si-insert-waitcnts=1 -verify-machineinstrs | FileCheck --check-prefix=GCN %s
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
declare i32 @llvm.amdgcn.workgroup.id.x() declare i32 @llvm.amdgcn.workgroup.id.x()
declare void @llvm.amdgcn.s.barrier() declare void @llvm.amdgcn.s.barrier()
@test_local.temp = internal addrspace(3) global [1 x i32] undef, align 4 @test_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
@test_global_local.temp = internal addrspace(3) global [1 x i32] undef, align 4 @test_global_local.temp = internal addrspace(3) global [1 x i32] undef, align 4
; GCN-LABEL: {{^}}test_local ; GCN-LABEL: {{^}}test_local
Show All 15 Lines; <label>:6: ; preds = %1
br label %7 br label %7
; <label>:7: ; preds = %6, %1 ; <label>:7: ; preds = %6, %1
fence syncscope("workgroup") release fence syncscope("workgroup") release
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
fence syncscope("workgroup") acquire fence syncscope("workgroup") acquire
%8 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4 %8 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_local.temp, i64 0, i64 0), align 4
%9 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4 %9 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%10 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %10 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%11 = call i32 @llvm.amdgcn.workitem.id.x() %11 = call i32 @llvm.amdgcn.workitem.id.x()
%12 = call i32 @llvm.amdgcn.workgroup.id.x() %12 = call i32 @llvm.amdgcn.workgroup.id.x()
%13 = getelementptr inbounds i8, i8 addrspace(2)* %10, i64 4 %13 = getelementptr inbounds i8, i8 addrspace(4)* %10, i64 4
%14 = bitcast i8 addrspace(2)* %13 to i16 addrspace(2)* %14 = bitcast i8 addrspace(4)* %13 to i16 addrspace(4)*
%15 = load i16, i16 addrspace(2)* %14, align 4 %15 = load i16, i16 addrspace(4)* %14, align 4
%16 = zext i16 %15 to i32 %16 = zext i16 %15 to i32
%17 = mul i32 %12, %16 %17 = mul i32 %12, %16
%18 = add i32 %17, %11 %18 = add i32 %17, %11
%19 = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %19 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%20 = zext i32 %18 to i64 %20 = zext i32 %18 to i64
%21 = bitcast i8 addrspace(2)* %19 to i64 addrspace(2)* %21 = bitcast i8 addrspace(4)* %19 to i64 addrspace(4)*
%22 = load i64, i64 addrspace(2)* %21, align 8 %22 = load i64, i64 addrspace(4)* %21, align 8
%23 = add i64 %22, %20 %23 = add i64 %22, %20
%24 = getelementptr inbounds i32, i32 addrspace(1)* %9, i64 %23 %24 = getelementptr inbounds i32, i32 addrspace(1)* %9, i64 %23
store i32 %8, i32 addrspace(1)* %24, align 4 store i32 %8, i32 addrspace(1)* %24, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}test_global ; GCN-LABEL: {{^}}test_global
; GCN: v_add_u32_e32 v{{[0-9]+}}, vcc, 0x888, v{{[0-9]+}} ; GCN: v_add_u32_e32 v{{[0-9]+}}, vcc, 0x888, v{{[0-9]+}}
; GCN: flat_store_dword ; GCN: flat_store_dword
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GCN-NEXT: s_barrier ; GCN-NEXT: s_barrier
define amdgpu_kernel void @test_global(i32 addrspace(1)*) { define amdgpu_kernel void @test_global(i32 addrspace(1)*) {
%2 = alloca i32 addrspace(1)*, align 4, addrspace(5) %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
%3 = alloca i32, align 4, addrspace(5) %3 = alloca i32, align 4, addrspace(5)
store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
store i32 0, i32 addrspace(5)* %3, align 4 store i32 0, i32 addrspace(5)* %3, align 4
br label %4 br label %4
; <label>:4: ; preds = %58, %1 ; <label>:4: ; preds = %58, %1
%5 = load i32, i32 addrspace(5)* %3, align 4 %5 = load i32, i32 addrspace(5)* %3, align 4
%6 = sext i32 %5 to i64 %6 = sext i32 %5 to i64
%7 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %7 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%8 = call i32 @llvm.amdgcn.workitem.id.x() %8 = call i32 @llvm.amdgcn.workitem.id.x()
%9 = call i32 @llvm.amdgcn.workgroup.id.x() %9 = call i32 @llvm.amdgcn.workgroup.id.x()
%10 = getelementptr inbounds i8, i8 addrspace(2)* %7, i64 4 %10 = getelementptr inbounds i8, i8 addrspace(4)* %7, i64 4
%11 = bitcast i8 addrspace(2)* %10 to i16 addrspace(2)* %11 = bitcast i8 addrspace(4)* %10 to i16 addrspace(4)*
%12 = load i16, i16 addrspace(2)* %11, align 4 %12 = load i16, i16 addrspace(4)* %11, align 4
%13 = zext i16 %12 to i32 %13 = zext i16 %12 to i32
%14 = mul i32 %9, %13 %14 = mul i32 %9, %13
%15 = add i32 %14, %8 %15 = add i32 %14, %8
%16 = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %16 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%17 = zext i32 %15 to i64 %17 = zext i32 %15 to i64
%18 = bitcast i8 addrspace(2)* %16 to i64 addrspace(2)* %18 = bitcast i8 addrspace(4)* %16 to i64 addrspace(4)*
%19 = load i64, i64 addrspace(2)* %18, align 8 %19 = load i64, i64 addrspace(4)* %18, align 8
%20 = add i64 %19, %17 %20 = add i64 %19, %17
%21 = icmp ult i64 %6, %20 %21 = icmp ult i64 %6, %20
br i1 %21, label %22, label %61 br i1 %21, label %22, label %61
; <label>:22: ; preds = %4 ; <label>:22: ; preds = %4
%23 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %23 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%24 = call i32 @llvm.amdgcn.workitem.id.x() %24 = call i32 @llvm.amdgcn.workitem.id.x()
%25 = call i32 @llvm.amdgcn.workgroup.id.x() %25 = call i32 @llvm.amdgcn.workgroup.id.x()
%26 = getelementptr inbounds i8, i8 addrspace(2)* %23, i64 4 %26 = getelementptr inbounds i8, i8 addrspace(4)* %23, i64 4
%27 = bitcast i8 addrspace(2)* %26 to i16 addrspace(2)* %27 = bitcast i8 addrspace(4)* %26 to i16 addrspace(4)*
%28 = load i16, i16 addrspace(2)* %27, align 4 %28 = load i16, i16 addrspace(4)* %27, align 4
%29 = zext i16 %28 to i32 %29 = zext i16 %28 to i32
%30 = mul i32 %25, %29 %30 = mul i32 %25, %29
%31 = add i32 %30, %24 %31 = add i32 %30, %24
%32 = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %32 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%33 = zext i32 %31 to i64 %33 = zext i32 %31 to i64
%34 = bitcast i8 addrspace(2)* %32 to i64 addrspace(2)* %34 = bitcast i8 addrspace(4)* %32 to i64 addrspace(4)*
%35 = load i64, i64 addrspace(2)* %34, align 8 %35 = load i64, i64 addrspace(4)* %34, align 8
%36 = add i64 %35, %33 %36 = add i64 %35, %33
%37 = add i64 %36, 2184 %37 = add i64 %36, 2184
%38 = trunc i64 %37 to i32 %38 = trunc i64 %37 to i32
%39 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4 %39 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%40 = load i32, i32 addrspace(5)* %3, align 4 %40 = load i32, i32 addrspace(5)* %3, align 4
%41 = sext i32 %40 to i64 %41 = sext i32 %40 to i64
%42 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %42 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%43 = call i32 @llvm.amdgcn.workitem.id.x() %43 = call i32 @llvm.amdgcn.workitem.id.x()
%44 = call i32 @llvm.amdgcn.workgroup.id.x() %44 = call i32 @llvm.amdgcn.workgroup.id.x()
%45 = getelementptr inbounds i8, i8 addrspace(2)* %42, i64 4 %45 = getelementptr inbounds i8, i8 addrspace(4)* %42, i64 4
%46 = bitcast i8 addrspace(2)* %45 to i16 addrspace(2)* %46 = bitcast i8 addrspace(4)* %45 to i16 addrspace(4)*
%47 = load i16, i16 addrspace(2)* %46, align 4 %47 = load i16, i16 addrspace(4)* %46, align 4
%48 = zext i16 %47 to i32 %48 = zext i16 %47 to i32
%49 = mul i32 %44, %48 %49 = mul i32 %44, %48
%50 = add i32 %49, %43 %50 = add i32 %49, %43
%51 = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %51 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%52 = zext i32 %50 to i64 %52 = zext i32 %50 to i64
%53 = bitcast i8 addrspace(2)* %51 to i64 addrspace(2)* %53 = bitcast i8 addrspace(4)* %51 to i64 addrspace(4)*
%54 = load i64, i64 addrspace(2)* %53, align 8 %54 = load i64, i64 addrspace(4)* %53, align 8
%55 = add i64 %54, %52 %55 = add i64 %54, %52
%56 = add i64 %41, %55 %56 = add i64 %41, %55
%57 = getelementptr inbounds i32, i32 addrspace(1)* %39, i64 %56 %57 = getelementptr inbounds i32, i32 addrspace(1)* %39, i64 %56
store i32 %38, i32 addrspace(1)* %57, align 4 store i32 %38, i32 addrspace(1)* %57, align 4
fence syncscope("workgroup") release fence syncscope("workgroup") release
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
fence syncscope("workgroup") acquire fence syncscope("workgroup") acquire
br label %58 br label %58
Show All 13 Lines
; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]] ; GCN: ds_write_b32 v{{[0-9]+}}, v[[VAL]]
; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0){{$}}
; GCN-NEXT: s_barrier ; GCN-NEXT: s_barrier
; GCN: flat_store_dword ; GCN: flat_store_dword
define amdgpu_kernel void @test_global_local(i32 addrspace(1)*) { define amdgpu_kernel void @test_global_local(i32 addrspace(1)*) {
%2 = alloca i32 addrspace(1)*, align 4, addrspace(5) %2 = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4 store i32 addrspace(1)* %0, i32 addrspace(1)* addrspace(5)* %2, align 4
%3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4 %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%4 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %4 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%5 = call i32 @llvm.amdgcn.workitem.id.x() %5 = call i32 @llvm.amdgcn.workitem.id.x()
%6 = call i32 @llvm.amdgcn.workgroup.id.x() %6 = call i32 @llvm.amdgcn.workgroup.id.x()
%7 = getelementptr inbounds i8, i8 addrspace(2)* %4, i64 4 %7 = getelementptr inbounds i8, i8 addrspace(4)* %4, i64 4
%8 = bitcast i8 addrspace(2)* %7 to i16 addrspace(2)* %8 = bitcast i8 addrspace(4)* %7 to i16 addrspace(4)*
%9 = load i16, i16 addrspace(2)* %8, align 4 %9 = load i16, i16 addrspace(4)* %8, align 4
%10 = zext i16 %9 to i32 %10 = zext i16 %9 to i32
%11 = mul i32 %6, %10 %11 = mul i32 %6, %10
%12 = add i32 %11, %5 %12 = add i32 %11, %5
%13 = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %13 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%14 = zext i32 %12 to i64 %14 = zext i32 %12 to i64
%15 = bitcast i8 addrspace(2)* %13 to i64 addrspace(2)* %15 = bitcast i8 addrspace(4)* %13 to i64 addrspace(4)*
%16 = load i64, i64 addrspace(2)* %15, align 8 %16 = load i64, i64 addrspace(4)* %15, align 8
%17 = add i64 %16, %14 %17 = add i64 %16, %14
%18 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %17 %18 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %17
store i32 1, i32 addrspace(1)* %18, align 4 store i32 1, i32 addrspace(1)* %18, align 4
%19 = call i32 @llvm.amdgcn.workitem.id.x() %19 = call i32 @llvm.amdgcn.workitem.id.x()
%20 = zext i32 %19 to i64 %20 = zext i32 %19 to i64
%21 = icmp eq i64 %20, 0 %21 = icmp eq i64 %20, 0
br i1 %21, label %22, label %23 br i1 %21, label %22, label %23
; <label>:22: ; preds = %1 ; <label>:22: ; preds = %1
store i32 2457, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4 store i32 2457, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4
br label %23 br label %23
; <label>:23: ; preds = %22, %1 ; <label>:23: ; preds = %22, %1
fence syncscope("workgroup") release fence syncscope("workgroup") release
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
fence syncscope("workgroup") acquire fence syncscope("workgroup") acquire
%24 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4 %24 = load i32, i32 addrspace(3)* getelementptr inbounds ([1 x i32], [1 x i32] addrspace(3)* @test_global_local.temp, i64 0, i64 0), align 4
%25 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4 %25 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %2, align 4
%26 = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %26 = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%27 = call i32 @llvm.amdgcn.workitem.id.x() %27 = call i32 @llvm.amdgcn.workitem.id.x()
%28 = call i32 @llvm.amdgcn.workgroup.id.x() %28 = call i32 @llvm.amdgcn.workgroup.id.x()
%29 = getelementptr inbounds i8, i8 addrspace(2)* %26, i64 4 %29 = getelementptr inbounds i8, i8 addrspace(4)* %26, i64 4
%30 = bitcast i8 addrspace(2)* %29 to i16 addrspace(2)* %30 = bitcast i8 addrspace(4)* %29 to i16 addrspace(4)*
%31 = load i16, i16 addrspace(2)* %30, align 4 %31 = load i16, i16 addrspace(4)* %30, align 4
%32 = zext i16 %31 to i32 %32 = zext i16 %31 to i32
%33 = mul i32 %28, %32 %33 = mul i32 %28, %32
%34 = add i32 %33, %27 %34 = add i32 %33, %27
%35 = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %35 = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%36 = zext i32 %34 to i64 %36 = zext i32 %34 to i64
%37 = bitcast i8 addrspace(2)* %35 to i64 addrspace(2)* %37 = bitcast i8 addrspace(4)* %35 to i64 addrspace(4)*
%38 = load i64, i64 addrspace(2)* %37, align 8 %38 = load i64, i64 addrspace(4)* %37, align 8
%39 = add i64 %38, %36 %39 = add i64 %38, %36
%40 = getelementptr inbounds i32, i32 addrspace(1)* %25, i64 %39 %40 = getelementptr inbounds i32, i32 addrspace(1)* %25, i64 %39
store i32 %24, i32 addrspace(1)* %40, align 4 store i32 %24, i32 addrspace(1)* %40, align 4
ret void ret void
} }

test/CodeGen/AMDGPU/function-returns.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
} }
; GCN-LABEL: {{^}}v8i32_func_void: ; GCN-LABEL: {{^}}v8i32_func_void:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <8 x i32> @v8i32_func_void() #0 { define <8 x i32> @v8i32_func_void() #0 {
%ptr = load volatile <8 x i32> addrspace(1)*, <8 x i32> addrspace(1)* addrspace(2)* undef %ptr = load volatile <8 x i32> addrspace(1)*, <8 x i32> addrspace(1)* addrspace(4)* undef
%val = load <8 x i32>, <8 x i32> addrspace(1)* %ptr %val = load <8 x i32>, <8 x i32> addrspace(1)* %ptr
ret <8 x i32> %val ret <8 x i32> %val
} }
; GCN-LABEL: {{^}}v16i32_func_void: ; GCN-LABEL: {{^}}v16i32_func_void:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <16 x i32> @v16i32_func_void() #0 { define <16 x i32> @v16i32_func_void() #0 {
%ptr = load volatile <16 x i32> addrspace(1)*, <16 x i32> addrspace(1)* addrspace(2)* undef %ptr = load volatile <16 x i32> addrspace(1)*, <16 x i32> addrspace(1)* addrspace(4)* undef
%val = load <16 x i32>, <16 x i32> addrspace(1)* %ptr %val = load <16 x i32>, <16 x i32> addrspace(1)* %ptr
ret <16 x i32> %val ret <16 x i32> %val
} }
; GCN-LABEL: {{^}}v32i32_func_void: ; GCN-LABEL: {{^}}v32i32_func_void:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN-DAG: buffer_load_dwordx4 v[16:19], off ; GCN-DAG: buffer_load_dwordx4 v[16:19], off
; GCN-DAG: buffer_load_dwordx4 v[20:23], off ; GCN-DAG: buffer_load_dwordx4 v[20:23], off
; GCN-DAG: buffer_load_dwordx4 v[24:27], off ; GCN-DAG: buffer_load_dwordx4 v[24:27], off
; GCN-DAG: buffer_load_dwordx4 v[28:31], off ; GCN-DAG: buffer_load_dwordx4 v[28:31], off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <32 x i32> @v32i32_func_void() #0 { define <32 x i32> @v32i32_func_void() #0 {
%ptr = load volatile <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(2)* undef %ptr = load volatile <32 x i32> addrspace(1)*, <32 x i32> addrspace(1)* addrspace(4)* undef
%val = load <32 x i32>, <32 x i32> addrspace(1)* %ptr %val = load <32 x i32>, <32 x i32> addrspace(1)* %ptr
ret <32 x i32> %val ret <32 x i32> %val
} }
; GCN-LABEL: {{^}}v2i64_func_void: ; GCN-LABEL: {{^}}v2i64_func_void:
; GCN: buffer_load_dwordx4 v[0:3], off ; GCN: buffer_load_dwordx4 v[0:3], off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <2 x i64> @v2i64_func_void() #0 { define <2 x i64> @v2i64_func_void() #0 {
%val = load <2 x i64>, <2 x i64> addrspace(1)* undef %val = load <2 x i64>, <2 x i64> addrspace(1)* undef
ret <2 x i64> %val ret <2 x i64> %val
} }
; GCN-LABEL: {{^}}v3i64_func_void: ; GCN-LABEL: {{^}}v3i64_func_void:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <3 x i64> @v3i64_func_void() #0 { define <3 x i64> @v3i64_func_void() #0 {
%ptr = load volatile <3 x i64> addrspace(1)*, <3 x i64> addrspace(1)* addrspace(2)* undef %ptr = load volatile <3 x i64> addrspace(1)*, <3 x i64> addrspace(1)* addrspace(4)* undef
%val = load <3 x i64>, <3 x i64> addrspace(1)* %ptr %val = load <3 x i64>, <3 x i64> addrspace(1)* %ptr
ret <3 x i64> %val ret <3 x i64> %val
} }
; GCN-LABEL: {{^}}v4i64_func_void: ; GCN-LABEL: {{^}}v4i64_func_void:
; GCN: buffer_load_dwordx4 v[0:3], off ; GCN: buffer_load_dwordx4 v[0:3], off
; GCN: buffer_load_dwordx4 v[4:7], off ; GCN: buffer_load_dwordx4 v[4:7], off
; GCN-NEXT: s_waitcnt vmcnt(0) ; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <4 x i64> @v4i64_func_void() #0 { define <4 x i64> @v4i64_func_void() #0 {
%ptr = load volatile <4 x i64> addrspace(1)*, <4 x i64> addrspace(1)* addrspace(2)* undef %ptr = load volatile <4 x i64> addrspace(1)*, <4 x i64> addrspace(1)* addrspace(4)* undef
%val = load <4 x i64>, <4 x i64> addrspace(1)* %ptr %val = load <4 x i64>, <4 x i64> addrspace(1)* %ptr
ret <4 x i64> %val ret <4 x i64> %val
} }
; GCN-LABEL: {{^}}v5i64_func_void: ; GCN-LABEL: {{^}}v5i64_func_void:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <5 x i64> @v5i64_func_void() #0 { define <5 x i64> @v5i64_func_void() #0 {
%ptr = load volatile <5 x i64> addrspace(1)*, <5 x i64> addrspace(1)* addrspace(2)* undef %ptr = load volatile <5 x i64> addrspace(1)*, <5 x i64> addrspace(1)* addrspace(4)* undef
%val = load <5 x i64>, <5 x i64> addrspace(1)* %ptr %val = load <5 x i64>, <5 x i64> addrspace(1)* %ptr
ret <5 x i64> %val ret <5 x i64> %val
} }
; GCN-LABEL: {{^}}v8i64_func_void: ; GCN-LABEL: {{^}}v8i64_func_void:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <8 x i64> @v8i64_func_void() #0 { define <8 x i64> @v8i64_func_void() #0 {
%ptr = load volatile <8 x i64> addrspace(1)*, <8 x i64> addrspace(1)* addrspace(2)* undef %ptr = load volatile <8 x i64> addrspace(1)*, <8 x i64> addrspace(1)* addrspace(4)* undef
%val = load <8 x i64>, <8 x i64> addrspace(1)* %ptr %val = load <8 x i64>, <8 x i64> addrspace(1)* %ptr
ret <8 x i64> %val ret <8 x i64> %val
} }
; GCN-LABEL: {{^}}v16i64_func_void: ; GCN-LABEL: {{^}}v16i64_func_void:
; GCN-DAG: buffer_load_dwordx4 v[0:3], off ; GCN-DAG: buffer_load_dwordx4 v[0:3], off
; GCN-DAG: buffer_load_dwordx4 v[4:7], off ; GCN-DAG: buffer_load_dwordx4 v[4:7], off
; GCN-DAG: buffer_load_dwordx4 v[8:11], off ; GCN-DAG: buffer_load_dwordx4 v[8:11], off
; GCN-DAG: buffer_load_dwordx4 v[12:15], off ; GCN-DAG: buffer_load_dwordx4 v[12:15], off
; GCN-DAG: buffer_load_dwordx4 v[16:19], off ; GCN-DAG: buffer_load_dwordx4 v[16:19], off
; GCN-DAG: buffer_load_dwordx4 v[20:23], off ; GCN-DAG: buffer_load_dwordx4 v[20:23], off
; GCN-DAG: buffer_load_dwordx4 v[24:27], off ; GCN-DAG: buffer_load_dwordx4 v[24:27], off
; GCN-DAG: buffer_load_dwordx4 v[28:31], off ; GCN-DAG: buffer_load_dwordx4 v[28:31], off
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define <16 x i64> @v16i64_func_void() #0 { define <16 x i64> @v16i64_func_void() #0 {
%ptr = load volatile <16 x i64> addrspace(1)*, <16 x i64> addrspace(1)* addrspace(2)* undef %ptr = load volatile <16 x i64> addrspace(1)*, <16 x i64> addrspace(1)* addrspace(4)* undef
%val = load <16 x i64>, <16 x i64> addrspace(1)* %ptr %val = load <16 x i64>, <16 x i64> addrspace(1)* %ptr
ret <16 x i64> %val ret <16 x i64> %val
} }
; GCN-LABEL: {{^}}v2i16_func_void: ; GCN-LABEL: {{^}}v2i16_func_void:
; GFX9: buffer_load_dword v0, off ; GFX9: buffer_load_dword v0, off
; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
Show All 25 Lines
; GCN-LABEL: {{^}}v5i16_func_void: ; GCN-LABEL: {{^}}v5i16_func_void:
; GFX9: buffer_load_dwordx2 v[0:1] ; GFX9: buffer_load_dwordx2 v[0:1]
; GFX9: buffer_load_ushort v4 ; GFX9: buffer_load_ushort v4
; GFX9: v_lshrrev_b32_e32 v3, 16, v1 ; GFX9: v_lshrrev_b32_e32 v3, 16, v1
; GFX9: v_mov_b32_e32 v2, v1 ; GFX9: v_mov_b32_e32 v2, v1
; GFX9: v_lshrrev_b32_e32 v1, 16, v0 ; GFX9: v_lshrrev_b32_e32 v1, 16, v0
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define <5 x i16> @v5i16_func_void() #0 { define <5 x i16> @v5i16_func_void() #0 {
%ptr = load volatile <5 x i16> addrspace(1)*, <5 x i16> addrspace(1)* addrspace(2)* undef %ptr = load volatile <5 x i16> addrspace(1)*, <5 x i16> addrspace(1)* addrspace(4)* undef
%val = load <5 x i16>, <5 x i16> addrspace(1)* %ptr %val = load <5 x i16>, <5 x i16> addrspace(1)* %ptr
ret <5 x i16> %val ret <5 x i16> %val
} }
; GCN-LABEL: {{^}}v8i16_func_void: ; GCN-LABEL: {{^}}v8i16_func_void:
; GFX9-DAG: buffer_load_dwordx4 v[0:3], off ; GFX9-DAG: buffer_load_dwordx4 v[0:3], off
; GFX9: s_waitcnt vmcnt(0) ; GFX9: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define <8 x i16> @v8i16_func_void() #0 { define <8 x i16> @v8i16_func_void() #0 {
%ptr = load volatile <8 x i16> addrspace(1)*, <8 x i16> addrspace(1)* addrspace(2)* undef %ptr = load volatile <8 x i16> addrspace(1)*, <8 x i16> addrspace(1)* addrspace(4)* undef
%val = load <8 x i16>, <8 x i16> addrspace(1)* %ptr %val = load <8 x i16>, <8 x i16> addrspace(1)* %ptr
ret <8 x i16> %val ret <8 x i16> %val
} }
; GCN-LABEL: {{^}}v16i16_func_void: ; GCN-LABEL: {{^}}v16i16_func_void:
; GFX9: buffer_load_dwordx4 v[0:3], off ; GFX9: buffer_load_dwordx4 v[0:3], off
; GFX9: buffer_load_dwordx4 v[4:7], off ; GFX9: buffer_load_dwordx4 v[4:7], off
; GFX9: s_waitcnt vmcnt(0) ; GFX9: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define <16 x i16> @v16i16_func_void() #0 { define <16 x i16> @v16i16_func_void() #0 {
%ptr = load volatile <16 x i16> addrspace(1)*, <16 x i16> addrspace(1)* addrspace(2)* undef %ptr = load volatile <16 x i16> addrspace(1)*, <16 x i16> addrspace(1)* addrspace(4)* undef
%val = load <16 x i16>, <16 x i16> addrspace(1)* %ptr %val = load <16 x i16>, <16 x i16> addrspace(1)* %ptr
ret <16 x i16> %val ret <16 x i16> %val
} }
; FIXME: Should pack ; FIXME: Should pack
; GCN-LABEL: {{^}}v16i8_func_void: ; GCN-LABEL: {{^}}v16i8_func_void:
; GCN-DAG: v12 ; GCN-DAG: v12
; GCN-DAG: v13 ; GCN-DAG: v13
; GCN-DAG: v14 ; GCN-DAG: v14
; GCN-DAG: v15 ; GCN-DAG: v15
define <16 x i8> @v16i8_func_void() #0 { define <16 x i8> @v16i8_func_void() #0 {
%ptr = load volatile <16 x i8> addrspace(1)*, <16 x i8> addrspace(1)* addrspace(2)* undef %ptr = load volatile <16 x i8> addrspace(1)*, <16 x i8> addrspace(1)* addrspace(4)* undef
%val = load <16 x i8>, <16 x i8> addrspace(1)* %ptr %val = load <16 x i8>, <16 x i8> addrspace(1)* %ptr
ret <16 x i8> %val ret <16 x i8> %val
} }
; FIXME: Should pack ; FIXME: Should pack
; GCN-LABEL: {{^}}v4i8_func_void: ; GCN-LABEL: {{^}}v4i8_func_void:
; GCN: buffer_load_dword v0 ; GCN: buffer_load_dword v0
; GCN-DAG: v_lshrrev_b32_e32 v2, 16, v0 ; GCN-DAG: v_lshrrev_b32_e32 v2, 16, v0
; GCN-DAG: v_lshrrev_b32_e32 v3, 24, v0 ; GCN-DAG: v_lshrrev_b32_e32 v3, 24, v0
; CI-DAG: v_bfe_u32 v1, v0, 8, 8 ; CI-DAG: v_bfe_u32 v1, v0, 8, 8
; GFX89-DAG: v_lshrrev_b16_e32 v1, 8, v0 ; GFX89-DAG: v_lshrrev_b16_e32 v1, 8, v0
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define <4 x i8> @v4i8_func_void() #0 { define <4 x i8> @v4i8_func_void() #0 {
%ptr = load volatile <4 x i8> addrspace(1)*, <4 x i8> addrspace(1)* addrspace(2)* undef %ptr = load volatile <4 x i8> addrspace(1)*, <4 x i8> addrspace(1)* addrspace(4)* undef
%val = load <4 x i8>, <4 x i8> addrspace(1)* %ptr %val = load <4 x i8>, <4 x i8> addrspace(1)* %ptr
ret <4 x i8> %val ret <4 x i8> %val
} }
; GCN-LABEL: {{^}}struct_i8_i32_func_void: ; GCN-LABEL: {{^}}struct_i8_i32_func_void:
; GCN-DAG: buffer_load_dword v1 ; GCN-DAG: buffer_load_dword v1
; GCN-DAG: buffer_load_ubyte v0 ; GCN-DAG: buffer_load_ubyte v0
; GCN: s_waitcnt vmcnt(0) ; GCN: s_waitcnt vmcnt(0)
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; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:112{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:112{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:116{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:116{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:120{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:120{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:124{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:124{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:128{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:128{{$}}
; GFX9: s_waitcnt vmcnt(0) ; GFX9: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define <33 x i32> @v33i32_func_void() #0 { define <33 x i32> @v33i32_func_void() #0 {
%ptr = load volatile <33 x i32> addrspace(1)*, <33 x i32> addrspace(1)* addrspace(2)* undef %ptr = load volatile <33 x i32> addrspace(1)*, <33 x i32> addrspace(1)* addrspace(4)* undef
%val = load <33 x i32>, <33 x i32> addrspace(1)* %ptr %val = load <33 x i32>, <33 x i32> addrspace(1)* %ptr
ret <33 x i32> %val ret <33 x i32> %val
} }
; GCN-LABEL: {{^}}struct_v32i32_i32_func_void: ; GCN-LABEL: {{^}}struct_v32i32_i32_func_void:
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:4{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:8{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:8{{$}}
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; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:112{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:112{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:116{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:116{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:120{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:120{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:124{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:124{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:128{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:128{{$}}
; GFX9: s_waitcnt vmcnt(0) ; GFX9: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define { <32 x i32>, i32 } @struct_v32i32_i32_func_void() #0 { define { <32 x i32>, i32 } @struct_v32i32_i32_func_void() #0 {
%ptr = load volatile { <32 x i32>, i32 } addrspace(1)*, { <32 x i32>, i32 } addrspace(1)* addrspace(2)* undef %ptr = load volatile { <32 x i32>, i32 } addrspace(1)*, { <32 x i32>, i32 } addrspace(1)* addrspace(4)* undef
%val = load { <32 x i32>, i32 }, { <32 x i32>, i32 } addrspace(1)* %ptr %val = load { <32 x i32>, i32 }, { <32 x i32>, i32 } addrspace(1)* %ptr
ret { <32 x i32>, i32 }%val ret { <32 x i32>, i32 }%val
} }
; GCN-LABEL: {{^}}struct_i32_v32i32_func_void: ; GCN-LABEL: {{^}}struct_i32_v32i32_func_void:
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:128{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:128{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:132{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:132{{$}}
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; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:236{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:236{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:240{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:240{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:244{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:244{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:248{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:248{{$}}
; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:252{{$}} ; GFX9-DAG: buffer_store_dword v{{[0-9]+}}, v0, s[0:3], s4 offen offset:252{{$}}
; GFX9: s_waitcnt vmcnt(0) ; GFX9: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define { i32, <32 x i32> } @struct_i32_v32i32_func_void() #0 { define { i32, <32 x i32> } @struct_i32_v32i32_func_void() #0 {
%ptr = load volatile { i32, <32 x i32> } addrspace(1)*, { i32, <32 x i32> } addrspace(1)* addrspace(2)* undef %ptr = load volatile { i32, <32 x i32> } addrspace(1)*, { i32, <32 x i32> } addrspace(1)* addrspace(4)* undef
%val = load { i32, <32 x i32> }, { i32, <32 x i32> } addrspace(1)* %ptr %val = load { i32, <32 x i32> }, { i32, <32 x i32> } addrspace(1)* %ptr
ret { i32, <32 x i32> }%val ret { i32, <32 x i32> }%val
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
Context not available.

test/CodeGen/AMDGPU/global-constant.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOHSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=HSA %s
@private1 = private unnamed_addr addrspace(2) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0] @private1 = private unnamed_addr addrspace(4) constant [4 x float] [float 0.0, float 1.0, float 2.0, float 3.0]
@private2 = private unnamed_addr addrspace(2) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0] @private2 = private unnamed_addr addrspace(4) constant [4 x float] [float 4.0, float 5.0, float 6.0, float 7.0]
@available_externally = available_externally addrspace(2) global [256 x i32] zeroinitializer @available_externally = available_externally addrspace(4) global [256 x i32] zeroinitializer
; GCN-LABEL: {{^}}private_test: ; GCN-LABEL: {{^}}private_test:
; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
; Non-HSA OSes use fixup into .text section. ; Non-HSA OSes use fixup into .text section.
; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1 ; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1
; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0 ; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], 0
; HSA OSes use relocations. ; HSA OSes use relocations.
; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], private1@rel32@lo+4
; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], private1@rel32@hi+4
; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC1_LO:[0-9]+]]:[[PC1_HI:[0-9]+]]{{\]}}
; Non-HSA OSes use fixup into .text section. ; Non-HSA OSes use fixup into .text section.
; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2 ; NOHSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2
; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0 ; NOHSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], 0
; HSA OSes use relocations. ; HSA OSes use relocations.
; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC1_LO]], private2@rel32@lo+4
; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC1_HI]], private2@rel32@hi+4
define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) { define amdgpu_kernel void @private_test(i32 %index, float addrspace(1)* %out) {
%ptr = getelementptr [4 x float], [4 x float] addrspace(2) * @private1, i32 0, i32 %index %ptr = getelementptr [4 x float], [4 x float] addrspace(4) * @private1, i32 0, i32 %index
%val = load float, float addrspace(2)* %ptr %val = load float, float addrspace(4)* %ptr
store volatile float %val, float addrspace(1)* %out store volatile float %val, float addrspace(1)* %out
%ptr2 = getelementptr [4 x float], [4 x float] addrspace(2) * @private2, i32 0, i32 %index %ptr2 = getelementptr [4 x float], [4 x float] addrspace(4) * @private2, i32 0, i32 %index
%val2 = load float, float addrspace(2)* %ptr2 %val2 = load float, float addrspace(4)* %ptr2
store volatile float %val2, float addrspace(1)* %out store volatile float %val2, float addrspace(1)* %out
ret void ret void
} }
; HSA-LABEL: {{^}}available_externally_test: ; HSA-LABEL: {{^}}available_externally_test:
; HSA: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}} ; HSA: s_getpc_b64 s{{\[}}[[PC0_LO:[0-9]+]]:[[PC0_HI:[0-9]+]]{{\]}}
; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4 ; HSA: s_add_u32 s{{[0-9]+}}, s[[PC0_LO]], available_externally@gotpcrel32@lo+4
; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+4 ; HSA: s_addc_u32 s{{[0-9]+}}, s[[PC0_HI]], available_externally@gotpcrel32@hi+4
define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) { define amdgpu_kernel void @available_externally_test(i32 addrspace(1)* %out) {
%ptr = getelementptr [256 x i32], [256 x i32] addrspace(2)* @available_externally, i32 0, i32 1 %ptr = getelementptr [256 x i32], [256 x i32] addrspace(4)* @available_externally, i32 0, i32 1
%val = load i32, i32 addrspace(2)* %ptr %val = load i32, i32 addrspace(4)* %ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; NOHSA: .text ; NOHSA: .text
; HSA: .section .rodata ; HSA: .section .rodata
; GCN: private1: ; GCN: private1:
; GCN: private2: ; GCN: private2:

test/CodeGen/AMDGPU/gv-const-addrspace.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
@b = internal addrspace(2) constant [1 x i16] [ i16 7 ], align 2 @b = internal addrspace(4) constant [1 x i16] [ i16 7 ], align 2
@float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4 @float_gv = internal unnamed_addr addrspace(4) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4
; FUNC-LABEL: {{^}}float: ; FUNC-LABEL: {{^}}float:
; GCN: s_load_dword ; GCN: s_load_dword
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: @float_gv ; EG: @float_gv
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; EG-NOT: MOV ; EG-NOT: MOV
define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @float(float addrspace(1)* %out, i32 %index) {
entry: entry:
%0 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index %0 = getelementptr inbounds [5 x float], [5 x float] addrspace(4)* @float_gv, i32 0, i32 %index
%1 = load float, float addrspace(2)* %0 %1 = load float, float addrspace(4)* %0
store float %1, float addrspace(1)* %out store float %1, float addrspace(1)* %out
ret void ret void
} }
@i32_gv = internal unnamed_addr addrspace(2) constant [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4], align 4 @i32_gv = internal unnamed_addr addrspace(4) constant [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4], align 4
; FUNC-LABEL: {{^}}i32: ; FUNC-LABEL: {{^}}i32:
; GCN: s_load_dword ; GCN: s_load_dword
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: @i32_gv ; EG: @i32_gv
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; EG-NOT: MOV ; EG-NOT: MOV
define amdgpu_kernel void @i32(i32 addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @i32(i32 addrspace(1)* %out, i32 %index) {
entry: entry:
%0 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(2)* @i32_gv, i32 0, i32 %index %0 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(4)* @i32_gv, i32 0, i32 %index
%1 = load i32, i32 addrspace(2)* %0 %1 = load i32, i32 addrspace(4)* %0
store i32 %1, i32 addrspace(1)* %out store i32 %1, i32 addrspace(1)* %out
ret void ret void
} }
%struct.foo = type { float, [5 x i32] } %struct.foo = type { float, [5 x i32] }
@struct_foo_gv = internal unnamed_addr addrspace(2) constant [1 x %struct.foo] [ %struct.foo { float 16.0, [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4] } ] @struct_foo_gv = internal unnamed_addr addrspace(4) constant [1 x %struct.foo] [ %struct.foo { float 16.0, [5 x i32] [i32 0, i32 1, i32 2, i32 3, i32 4] } ]
; FUNC-LABEL: {{^}}struct_foo_gv_load: ; FUNC-LABEL: {{^}}struct_foo_gv_load:
; GCN: s_load_dword ; GCN: s_load_dword
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: @struct_foo_gv ; EG: @struct_foo_gv
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; EG-NOT: MOV ; EG-NOT: MOV
define amdgpu_kernel void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @struct_foo_gv_load(i32 addrspace(1)* %out, i32 %index) {
%gep = getelementptr inbounds [1 x %struct.foo], [1 x %struct.foo] addrspace(2)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index %gep = getelementptr inbounds [1 x %struct.foo], [1 x %struct.foo] addrspace(4)* @struct_foo_gv, i32 0, i32 0, i32 1, i32 %index
%load = load i32, i32 addrspace(2)* %gep, align 4 %load = load i32, i32 addrspace(4)* %gep, align 4
store i32 %load, i32 addrspace(1)* %out, align 4 store i32 %load, i32 addrspace(1)* %out, align 4
ret void ret void
} }
@array_v1_gv = internal addrspace(2) constant [4 x <1 x i32>] [ <1 x i32> <i32 1>, @array_v1_gv = internal addrspace(4) constant [4 x <1 x i32>] [ <1 x i32> <i32 1>,
<1 x i32> <i32 2>, <1 x i32> <i32 2>,
<1 x i32> <i32 3>, <1 x i32> <i32 3>,
<1 x i32> <i32 4> ] <1 x i32> <i32 4> ]
; FUNC-LABEL: {{^}}array_v1_gv_load: ; FUNC-LABEL: {{^}}array_v1_gv_load:
; GCN: s_load_dword ; GCN: s_load_dword
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: @array_v1_gv ; EG: @array_v1_gv
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; EG-NOT: MOV ; EG-NOT: MOV
define amdgpu_kernel void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) {
%gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(4)* @array_v1_gv, i32 0, i32 %index
%load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4 %load = load <1 x i32>, <1 x i32> addrspace(4)* %gep, align 4
store <1 x i32> %load, <1 x i32> addrspace(1)* %out, align 4 store <1 x i32> %load, <1 x i32> addrspace(1)* %out, align 4
ret void ret void
} }
; FUNC-LABEL: {{^}}gv_addressing_in_branch: ; FUNC-LABEL: {{^}}gv_addressing_in_branch:
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: @float_gv ; EG: @float_gv
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
define amdgpu_kernel void @gv_addressing_in_branch(float addrspace(1)* %out, i32 %index, i32 %a) { define amdgpu_kernel void @gv_addressing_in_branch(float addrspace(1)* %out, i32 %index, i32 %a) {
entry: entry:
%0 = icmp eq i32 0, %a %0 = icmp eq i32 0, %a
br i1 %0, label %if, label %else br i1 %0, label %if, label %else
if: if:
%1 = getelementptr inbounds [5 x float], [5 x float] addrspace(2)* @float_gv, i32 0, i32 %index %1 = getelementptr inbounds [5 x float], [5 x float] addrspace(4)* @float_gv, i32 0, i32 %index
%2 = load float, float addrspace(2)* %1 %2 = load float, float addrspace(4)* %1
store float %2, float addrspace(1)* %out store float %2, float addrspace(1)* %out
br label %endif br label %endif
else: else:
store float 1.0, float addrspace(1)* %out store float 1.0, float addrspace(1)* %out
br label %endif br label %endif
endif: endif:
ret void ret void
} }

test/CodeGen/AMDGPU/hsa-func-align.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=HSA %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -check-prefix=HSA %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj < %s | llvm-readobj -symbols -s -sd | FileCheck -check-prefix=ELF %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -filetype=obj < %s | llvm-readobj -symbols -s -sd | FileCheck -check-prefix=ELF %s
; ELF: Section { ; ELF: Section {
; ELF: Name: .text ; ELF: Name: .text
; ELF: SHF_ALLOC (0x2) ; ELF: SHF_ALLOC (0x2)
; ELF: SHF_EXECINSTR (0x4) ; ELF: SHF_EXECINSTR (0x4)
; ELF: AddressAlignment: 32 ; ELF: AddressAlignment: 32
; ELF: } ; ELF: }
; HSA: .globl simple_align16 ; HSA: .globl simple_align16
; HSA: .p2align 5 ; HSA: .p2align 5
define void @simple_align16(i32 addrspace(1)* addrspace(2)* %ptr.out) align 32 { define void @simple_align16(i32 addrspace(1)* addrspace(4)* %ptr.out) align 32 {
entry: entry:
%out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %ptr.out %out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %ptr.out
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/hsa-func.ll

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
; Make sure we are setting the ATC bit: ; Make sure we are setting the ATC bit:
; Make sure we generate flat store for HSA ; Make sure we generate flat store for HSA
; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} ; HSA: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
; HSA: .Lfunc_end0: ; HSA: .Lfunc_end0:
; HSA: .size simple, .Lfunc_end0-simple ; HSA: .size simple, .Lfunc_end0-simple
; HSA: ; Function info: ; HSA: ; Function info:
; HSA-NOT: COMPUTE_PGM_RSRC2 ; HSA-NOT: COMPUTE_PGM_RSRC2
define void @simple(i32 addrspace(1)* addrspace(2)* %ptr.out) { define void @simple(i32 addrspace(1)* addrspace(4)* %ptr.out) {
entry: entry:
%out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %ptr.out %out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %ptr.out
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
ret void ret void
} }
; Ignore explicit alignment that is too low. ; Ignore explicit alignment that is too low.
; HSA: .globl simple_align2 ; HSA: .globl simple_align2
; HSA: .p2align 2 ; HSA: .p2align 2
define void @simple_align2(i32 addrspace(1)* addrspace(2)* %ptr.out) align 2 { define void @simple_align2(i32 addrspace(1)* addrspace(4)* %ptr.out) align 2 {
entry: entry:
%out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %ptr.out %out = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %ptr.out
store i32 0, i32 addrspace(1)* %out store i32 0, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @test_addr_space(i32 addrspace(1)* %g, define amdgpu_kernel void @test_addr_space(i32 addrspace(1)* %g,
i32 addrspace(2)* %c, i32 addrspace(4)* %c,
i32 addrspace(3)* %l) i32 addrspace(3)* %l)
!kernel_arg_addr_space !50 !kernel_arg_access_qual !23 !kernel_arg_type !51 !kernel_arg_addr_space !50 !kernel_arg_access_qual !23 !kernel_arg_type !51
!kernel_arg_base_type !51 !kernel_arg_type_qual !25 { !kernel_arg_base_type !51 !kernel_arg_type_qual !25 {
ret void ret void
} }
; CHECK: - Name: test_type_qual ; CHECK: - Name: test_type_qual
; CHECK-NEXT: SymbolName: 'test_type_qual@kd' ; CHECK-NEXT: SymbolName: 'test_type_qual@kd'
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test/CodeGen/AMDGPU/image-schedule.ll

Show All 14 Lines
define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <3 x i32> inreg %arg3, i32 inreg %arg4, <3 x i32> %arg5) local_unnamed_addr #0 { define dllexport amdgpu_cs void @_amdgpu_cs_main(i32 inreg %arg, i32 inreg %arg1, i32 inreg %arg2, <3 x i32> inreg %arg3, i32 inreg %arg4, <3 x i32> %arg5) local_unnamed_addr #0 {
.entry: .entry:
%tmp = call i64 @llvm.amdgcn.s.getpc() #1 %tmp = call i64 @llvm.amdgcn.s.getpc() #1
%tmp6 = bitcast i64 %tmp to <2 x i32> %tmp6 = bitcast i64 %tmp to <2 x i32>
%.0.vec.insert = insertelement <2 x i32> undef, i32 %arg2, i32 0 %.0.vec.insert = insertelement <2 x i32> undef, i32 %arg2, i32 0
%.4.vec.insert = shufflevector <2 x i32> %.0.vec.insert, <2 x i32> %tmp6, <2 x i32> <i32 0, i32 3> %.4.vec.insert = shufflevector <2 x i32> %.0.vec.insert, <2 x i32> %tmp6, <2 x i32> <i32 0, i32 3>
%tmp7 = bitcast <2 x i32> %.4.vec.insert to i64 %tmp7 = bitcast <2 x i32> %.4.vec.insert to i64
%tmp8 = inttoptr i64 %tmp7 to [4294967295 x i8] addrspace(2)* %tmp8 = inttoptr i64 %tmp7 to [4294967295 x i8] addrspace(4)*
%tmp9 = add <3 x i32> %arg3, %arg5 %tmp9 = add <3 x i32> %arg3, %arg5
%tmp10 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(2)* %tmp8, i64 0, i64 32 %tmp10 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(4)* %tmp8, i64 0, i64 32
%tmp11 = bitcast i8 addrspace(2)* %tmp10 to <8 x i32> addrspace(2)*, !amdgpu.uniform !0 %tmp11 = bitcast i8 addrspace(4)* %tmp10 to <8 x i32> addrspace(4)*, !amdgpu.uniform !0
%tmp12 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp11, align 16 %tmp12 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp11, align 16
%tmp13 = shufflevector <3 x i32> %tmp9, <3 x i32> undef, <2 x i32> <i32 0, i32 1> %tmp13 = shufflevector <3 x i32> %tmp9, <3 x i32> undef, <2 x i32> <i32 0, i32 1>
%tmp14 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp13, <8 x i32> %tmp12, i32 15, i1 false, i1 false, i1 false, i1 false) #0 %tmp14 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp13, <8 x i32> %tmp12, i32 15, i1 false, i1 false, i1 false, i1 false) #0
%tmp15 = inttoptr i64 %tmp7 to <8 x i32> addrspace(2)* %tmp15 = inttoptr i64 %tmp7 to <8 x i32> addrspace(4)*
%tmp16 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp15, align 16 %tmp16 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp15, align 16
call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %tmp14, <2 x i32> %tmp13, <8 x i32> %tmp16, i32 15, i1 false, i1 false, i1 false, i1 false) #0 call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %tmp14, <2 x i32> %tmp13, <8 x i32> %tmp16, i32 15, i1 false, i1 false, i1 false, i1 false) #0
%tmp17 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp15, align 16 %tmp17 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp15, align 16
%tmp18 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp13, <8 x i32> %tmp17, i32 15, i1 false, i1 false, i1 false, i1 false) #0 %tmp18 = call <4 x float> @llvm.amdgcn.image.load.v4f32.v2i32.v8i32(<2 x i32> %tmp13, <8 x i32> %tmp17, i32 15, i1 false, i1 false, i1 false, i1 false) #0
%tmp19 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(2)* %tmp8, i64 0, i64 64 %tmp19 = getelementptr [4294967295 x i8], [4294967295 x i8] addrspace(4)* %tmp8, i64 0, i64 64
%tmp20 = bitcast i8 addrspace(2)* %tmp19 to <8 x i32> addrspace(2)*, !amdgpu.uniform !0 %tmp20 = bitcast i8 addrspace(4)* %tmp19 to <8 x i32> addrspace(4)*, !amdgpu.uniform !0
%tmp21 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp20, align 16 %tmp21 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp20, align 16
call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %tmp18, <2 x i32> %tmp13, <8 x i32> %tmp21, i32 15, i1 false, i1 false, i1 false, i1 false) #0 call void @llvm.amdgcn.image.store.v4f32.v2i32.v8i32(<4 x float> %tmp18, <2 x i32> %tmp13, <8 x i32> %tmp21, i32 15, i1 false, i1 false, i1 false, i1 false) #0
ret void ret void
} }
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare i64 @llvm.amdgcn.s.getpc() #1 declare i64 @llvm.amdgcn.s.getpc() #1
; Function Attrs: nounwind readonly ; Function Attrs: nounwind readonly
Show All 11 Lines

test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll

; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -enable-amdgpu-aa=0 -mattr=+flat-for-global,-fp64-fp16-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=gfx900 -enable-amdgpu-aa=0 -mattr=+flat-for-global,-fp64-fp16-denormals < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 -check-prefix=GFX89 %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=VI -check-prefix=GFX89 %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=fiji -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=VI -check-prefix=GFX89 %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=CI %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=hawaii -enable-amdgpu-aa=0 -mattr=+flat-for-global < %s | FileCheck -check-prefix=GCN -check-prefix=CIVI -check-prefix=CI %s
; GCN-LABEL: {{^}}s_insertelement_v2i16_0: ; GCN-LABEL: {{^}}s_insertelement_v2i16_0:
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; CIVI: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}} ; CIVI: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}}
; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], 0x3e7{{$}} ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], 0x3e7{{$}}
; GFX9-NOT: lshr ; GFX9-NOT: lshr
; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, 0x3e7, [[VEC]] ; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, 0x3e7, [[VEC]]
define amdgpu_kernel void @s_insertelement_v2i16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 999, i32 0 %vecins = insertelement <2 x i16> %vec, i16 999, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reg: ; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reg:
; GCN: s_load_dword [[ELT0:s[0-9]+]] ; GCN: s_load_dword [[ELT0:s[0-9]+]]
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; CIVI-DAG: s_and_b32 [[ELT0]], [[ELT0]], 0xffff{{$}} ; CIVI-DAG: s_and_b32 [[ELT0]], [[ELT0]], 0xffff{{$}}
; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}} ; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}}
; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]]
; GFX9-NOT: [[ELT0]] ; GFX9-NOT: [[ELT0]]
; GFX9-NOT: [[VEC]] ; GFX9-NOT: [[VEC]]
; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, [[ELT0]], [[VEC]] ; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, [[ELT0]], [[VEC]]
define amdgpu_kernel void @s_insertelement_v2i16_0_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i16 %elt) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i16 %elt) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2i16_0_multi_use_hi_reg: ; GCN-LABEL: {{^}}s_insertelement_v2i16_0_multi_use_hi_reg:
; GCN: s_load_dword [[ELT0:s[0-9]+]] ; GCN: s_load_dword [[ELT0:s[0-9]+]]
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; CIVI-DAG: s_and_b32 [[ELT0]], [[ELT0]], 0xffff{{$}} ; CIVI-DAG: s_and_b32 [[ELT0]], [[ELT0]], 0xffff{{$}}
; CIVI: s_lshr_b32 [[SHR:s[0-9]+]], [[VEC]], 16 ; CIVI: s_lshr_b32 [[SHR:s[0-9]+]], [[VEC]], 16
; CIVI: s_lshl_b32 [[ELT1:s[0-9]+]], [[SHR]], 16 ; CIVI: s_lshl_b32 [[ELT1:s[0-9]+]], [[SHR]], 16
; CIVI-DAG: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] ; CIVI-DAG: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]]
; CIVI-DAG: ; use [[SHR]] ; CIVI-DAG: ; use [[SHR]]
; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16 ; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
; GFX9-DAG: s_pack_ll_b32_b16 s{{[0-9]+}}, [[ELT0]], [[ELT1]] ; GFX9-DAG: s_pack_ll_b32_b16 s{{[0-9]+}}, [[ELT0]], [[ELT1]]
; GFX9-DAG: ; use [[ELT1]] ; GFX9-DAG: ; use [[ELT1]]
define amdgpu_kernel void @s_insertelement_v2i16_0_multi_use_hi_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i16 %elt) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0_multi_use_hi_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i16 %elt) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt1 = extractelement <2 x i16> %vec, i32 1 %elt1 = extractelement <2 x i16> %vec, i32 1
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
%use1 = zext i16 %elt1 to i32 %use1 = zext i16 %elt1 to i32
call void asm sideeffect "; use $0", "s"(i32 %use1) #0 call void asm sideeffect "; use $0", "s"(i32 %use1) #0
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi: ; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi:
; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1] ; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1]
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}} ; CIVI-DAG: s_and_b32 [[ELT1:s[0-9]+]], [[VEC]], 0xffff0000{{$}}
; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT_ARG]], [[ELT1]] ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT_ARG]], [[ELT1]]
; GFX9-NOT: [[ELT0]] ; GFX9-NOT: [[ELT0]]
; GFX9-NOT: [[VEC]] ; GFX9-NOT: [[VEC]]
; GFX9: s_pack_hh_b32_b16 s{{[0-9]+}}, [[ELT_ARG]], [[VEC]] ; GFX9: s_pack_hh_b32_b16 s{{[0-9]+}}, [[ELT_ARG]], [[VEC]]
define amdgpu_kernel void @s_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %elt.arg) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0_reghi(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %elt.arg) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt.hi = lshr i32 %elt.arg, 16 %elt.hi = lshr i32 %elt.arg, 16
%elt = trunc i32 %elt.hi to i16 %elt = trunc i32 %elt.hi to i16
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi_multi_use_1: ; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi_multi_use_1:
; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1] ; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1]
; GCN: s_load_dword [[VEC:s[0-9]+]], ; GCN: s_load_dword [[VEC:s[0-9]+]],
; CIVI-DAG: s_lshr_b32 [[ELT1:s[0-9]+]], [[ELT_ARG]], 16 ; CIVI-DAG: s_lshr_b32 [[ELT1:s[0-9]+]], [[ELT_ARG]], 16
; CIVI-DAG: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff0000{{$}} ; CIVI-DAG: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff0000{{$}}
; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], [[ELT0]] ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], [[ELT0]]
; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[ELT_ARG]], 16 ; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[ELT_ARG]], 16
; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, [[ELT1]], [[VEC]] ; GFX9: s_pack_lh_b32_b16 s{{[0-9]+}}, [[ELT1]], [[VEC]]
; GFX9: ; use [[ELT1]] ; GFX9: ; use [[ELT1]]
define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %elt.arg) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %elt.arg) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt.hi = lshr i32 %elt.arg, 16 %elt.hi = lshr i32 %elt.arg, 16
%elt = trunc i32 %elt.hi to i16 %elt = trunc i32 %elt.hi to i16
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
%use1 = zext i16 %elt to i32 %use1 = zext i16 %elt to i32
call void asm sideeffect "; use $0", "s"(i32 %use1) #0 call void asm sideeffect "; use $0", "s"(i32 %use1) #0
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi_both_multi_use_1: ; GCN-LABEL: {{^}}s_insertelement_v2i16_0_reghi_both_multi_use_1:
; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1] ; GCN: s_load_dword [[ELT_ARG:s[0-9]+]], s[0:1]
; GCN: s_load_dword [[VEC:s[0-9]+]], ; GCN: s_load_dword [[VEC:s[0-9]+]],
; CIVI-DAG: s_lshr_b32 [[ELT_HI:s[0-9]+]], [[ELT_ARG]], 16 ; CIVI-DAG: s_lshr_b32 [[ELT_HI:s[0-9]+]], [[ELT_ARG]], 16
; CIVI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VEC]], 16 ; CIVI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VEC]], 16
; CIVI-DAG: s_lshl_b32 [[VEC_HI:s[0-9]+]], [[SHR]], 16 ; CIVI-DAG: s_lshl_b32 [[VEC_HI:s[0-9]+]], [[SHR]], 16
; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT_HI]], [[VEC_HI]] ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT_HI]], [[VEC_HI]]
; GFX9-DAG: s_lshr_b32 [[ELT_HI:s[0-9]+]], [[ELT_ARG]], 16 ; GFX9-DAG: s_lshr_b32 [[ELT_HI:s[0-9]+]], [[ELT_ARG]], 16
; GFX9-DAG: s_lshr_b32 [[VEC_HI:s[0-9]+]], [[VEC]], 16 ; GFX9-DAG: s_lshr_b32 [[VEC_HI:s[0-9]+]], [[VEC]], 16
; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[ELT_HI]], [[VEC_HI]] ; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[ELT_HI]], [[VEC_HI]]
; GFX9: ; use [[ELT_HI]] ; GFX9: ; use [[ELT_HI]]
; GFX9: ; use [[VEC_HI]] ; GFX9: ; use [[VEC_HI]]
define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_both_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 %elt.arg) #0 { define amdgpu_kernel void @s_insertelement_v2i16_0_reghi_both_multi_use_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 %elt.arg) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%elt.hi = lshr i32 %elt.arg, 16 %elt.hi = lshr i32 %elt.arg, 16
%elt = trunc i32 %elt.hi to i16 %elt = trunc i32 %elt.hi to i16
%vec.hi = extractelement <2 x i16> %vec, i32 1 %vec.hi = extractelement <2 x i16> %vec, i32 1
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 0
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
%use1 = zext i16 %elt to i32 %use1 = zext i16 %elt to i32
%vec.hi.use1 = zext i16 %vec.hi to i32 %vec.hi.use1 = zext i16 %vec.hi to i32
call void asm sideeffect "; use $0", "s"(i32 %use1) #0 call void asm sideeffect "; use $0", "s"(i32 %use1) #0
call void asm sideeffect "; use $0", "s"(i32 %vec.hi.use1) #0 call void asm sideeffect "; use $0", "s"(i32 %vec.hi.use1) #0
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2i16_1: ; GCN-LABEL: {{^}}s_insertelement_v2i16_1:
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; GCN-NOT: s_lshr ; GCN-NOT: s_lshr
; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}} ; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}}
; CIVI: s_or_b32 [[INS:s[0-9]+]], [[ELT0]], 0x3e70000 ; CIVI: s_or_b32 [[INS:s[0-9]+]], [[ELT0]], 0x3e70000
; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], 0x3e7 ; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], 0x3e7
define amdgpu_kernel void @s_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr) #0 { define amdgpu_kernel void @s_insertelement_v2i16_1(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 999, i32 1 %vecins = insertelement <2 x i16> %vec, i16 999, i32 1
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2i16_1_reg: ; GCN-LABEL: {{^}}s_insertelement_v2i16_1_reg:
; GCN: s_load_dword [[ELT1:s[0-9]+]] ; GCN: s_load_dword [[ELT1:s[0-9]+]]
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}} ; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}}
; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]] ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT0]], [[ELT1]]
; GCN-NOT: shlr ; GCN-NOT: shlr
; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], [[ELT1]] ; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], [[ELT1]]
define amdgpu_kernel void @s_insertelement_v2i16_1_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i16 %elt) #0 { define amdgpu_kernel void @s_insertelement_v2i16_1_reg(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i16 %elt) #0 {
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 %elt, i32 1 %vecins = insertelement <2 x i16> %vec, i16 %elt, i32 1
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2f16_0: ; GCN-LABEL: {{^}}s_insertelement_v2f16_0:
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; CIVI: s_and_b32 [[ELT1:s[0-9]+]], [[VEC:s[0-9]+]], 0xffff0000 ; CIVI: s_and_b32 [[ELT1:s[0-9]+]], [[VEC:s[0-9]+]], 0xffff0000
; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], 0x4500 ; CIVI: s_or_b32 s{{[0-9]+}}, [[ELT1]], 0x4500
; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16 ; GFX9: s_lshr_b32 [[ELT1:s[0-9]+]], [[VEC]], 16
; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, 0x4500, [[ELT1]] ; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, 0x4500, [[ELT1]]
define amdgpu_kernel void @s_insertelement_v2f16_0(<2 x half> addrspace(1)* %out, <2 x half> addrspace(2)* %vec.ptr) #0 { define amdgpu_kernel void @s_insertelement_v2f16_0(<2 x half> addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr) #0 {
%vec = load <2 x half>, <2 x half> addrspace(2)* %vec.ptr %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 0 %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 0
store <2 x half> %vecins, <2 x half> addrspace(1)* %out store <2 x half> %vecins, <2 x half> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_insertelement_v2f16_1: ; GCN-LABEL: {{^}}s_insertelement_v2f16_1:
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; GCN-NOT: s_lshr ; GCN-NOT: s_lshr
; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}} ; CIVI: s_and_b32 [[ELT0:s[0-9]+]], [[VEC]], 0xffff{{$}}
; CIVI: s_or_b32 [[INS:s[0-9]+]], [[ELT0]], 0x45000000 ; CIVI: s_or_b32 [[INS:s[0-9]+]], [[ELT0]], 0x45000000
; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], 0x4500 ; GFX9: s_pack_ll_b32_b16 s{{[0-9]+}}, [[VEC]], 0x4500
define amdgpu_kernel void @s_insertelement_v2f16_1(<2 x half> addrspace(1)* %out, <2 x half> addrspace(2)* %vec.ptr) #0 { define amdgpu_kernel void @s_insertelement_v2f16_1(<2 x half> addrspace(1)* %out, <2 x half> addrspace(4)* %vec.ptr) #0 {
%vec = load <2 x half>, <2 x half> addrspace(2)* %vec.ptr %vec = load <2 x half>, <2 x half> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 1 %vecins = insertelement <2 x half> %vec, half 5.000000e+00, i32 1
store <2 x half> %vecins, <2 x half> addrspace(1)* %out store <2 x half> %vecins, <2 x half> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_insertelement_v2i16_0: ; GCN-LABEL: {{^}}v_insertelement_v2i16_0:
; GCN-DAG: {{flat|global}}_load_dword [[VEC:v[0-9]+]] ; GCN-DAG: {{flat|global}}_load_dword [[VEC:v[0-9]+]]
; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]] ; CIVI: v_and_b32_e32 [[ELT1:v[0-9]+]], 0xffff0000, [[VEC]]
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; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7
; GCN: s_load_dword [[IDX:s[0-9]+]] ; GCN: s_load_dword [[IDX:s[0-9]+]]
; GCN: s_load_dword [[VEC:s[0-9]+]] ; GCN: s_load_dword [[VEC:s[0-9]+]]
; GCN-DAG: v_mov_b32_e32 [[VVEC:v[0-9]+]], [[VEC]] ; GCN-DAG: v_mov_b32_e32 [[VVEC:v[0-9]+]], [[VEC]]
; GCN-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 16 ; GCN-DAG: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 16
; GCN-DAG: s_lshl_b32 [[MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]] ; GCN-DAG: s_lshl_b32 [[MASK:s[0-9]+]], 0xffff, [[SCALED_IDX]]
; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[MASK]], [[K]], [[VVEC]] ; GCN: v_bfi_b32 [[RESULT:v[0-9]+]], [[MASK]], [[K]], [[VVEC]]
; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]] ; GCN: {{flat|global}}_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
define amdgpu_kernel void @s_insertelement_v2i16_dynamic(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %vec.ptr, i32 addrspace(2)* %idx.ptr) #0 { define amdgpu_kernel void @s_insertelement_v2i16_dynamic(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %vec.ptr, i32 addrspace(4)* %idx.ptr) #0 {
%idx = load volatile i32, i32 addrspace(2)* %idx.ptr %idx = load volatile i32, i32 addrspace(4)* %idx.ptr
%vec = load <2 x i16>, <2 x i16> addrspace(2)* %vec.ptr %vec = load <2 x i16>, <2 x i16> addrspace(4)* %vec.ptr
%vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx %vecins = insertelement <2 x i16> %vec, i16 999, i32 %idx
store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out store <2 x i16> %vecins, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_insertelement_v2i16_dynamic_sgpr: ; GCN-LABEL: {{^}}v_insertelement_v2i16_dynamic_sgpr:
; GCN-DAG: {{flat|global}}_load_dword [[VEC:v[0-9]+]] ; GCN-DAG: {{flat|global}}_load_dword [[VEC:v[0-9]+]]
; GCN-DAG: s_load_dword [[IDX:s[0-9]+]] ; GCN-DAG: s_load_dword [[IDX:s[0-9]+]]
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test/CodeGen/AMDGPU/invariant-load-no-alias-store.ll

Show All 16 Linesdefine amdgpu_kernel void @test_merge_store_constant_i16_invariant_global_pointer_load(i16 addrspace(1)* addrspace(1)* dereferenceable(4096) nonnull %in) #0 {
store i16 456, i16 addrspace(1)* %ptr.1 store i16 456, i16 addrspace(1)* %ptr.1
ret void ret void
} }
; GCN-LABEL: {{^}}test_merge_store_constant_i16_invariant_constant_pointer_load: ; GCN-LABEL: {{^}}test_merge_store_constant_i16_invariant_constant_pointer_load:
; GCN: s_load_dwordx2 s{{\[}}[[SPTR_LO:[0-9]+]]:[[SPTR_HI:[0-9]+]]{{\]}} ; GCN: s_load_dwordx2 s{{\[}}[[SPTR_LO:[0-9]+]]:[[SPTR_HI:[0-9]+]]{{\]}}
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x1c8007b
; GCN: buffer_store_dword [[K]], off, s{{\[}}[[SPTR_LO]]: ; GCN: buffer_store_dword [[K]], off, s{{\[}}[[SPTR_LO]]:
define amdgpu_kernel void @test_merge_store_constant_i16_invariant_constant_pointer_load(i16 addrspace(1)* addrspace(2)* dereferenceable(4096) nonnull %in) #0 { define amdgpu_kernel void @test_merge_store_constant_i16_invariant_constant_pointer_load(i16 addrspace(1)* addrspace(4)* dereferenceable(4096) nonnull %in) #0 {
%ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(2)* %in, !invariant.load !0 %ptr = load i16 addrspace(1)*, i16 addrspace(1)* addrspace(4)* %in, !invariant.load !0
%ptr.1 = getelementptr i16, i16 addrspace(1)* %ptr, i64 1 %ptr.1 = getelementptr i16, i16 addrspace(1)* %ptr, i64 1
store i16 123, i16 addrspace(1)* %ptr, align 4 store i16 123, i16 addrspace(1)* %ptr, align 4
store i16 456, i16 addrspace(1)* %ptr.1 store i16 456, i16 addrspace(1)* %ptr.1
ret void ret void
} }
!0 = !{} !0 = !{}
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/llvm.SI.load.dword.ll

; RUN: llc -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=verde -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs < %s | FileCheck %s
; Example of a simple geometry shader loading vertex attributes from the ; Example of a simple geometry shader loading vertex attributes from the
; ESGS ring buffer ; ESGS ring buffer
; FIXME: Out of bounds immediate offset crashes ; FIXME: Out of bounds immediate offset crashes
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, 0 glc slc
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen glc slc
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen glc slc
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen glc slc
; CHECK: s_movk_i32 [[K:s[0-9]+]], 0x4d2 ; encoding ; CHECK: s_movk_i32 [[K:s[0-9]+]], 0x4d2 ; encoding
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, [[K]] idxen offen offset:65535 glc slc
define amdgpu_vs void @main([17 x <4 x i32>] addrspace(2)* byval %arg, [32 x <4 x i32>] addrspace(2)* byval %arg1, [16 x <32 x i8>] addrspace(2)* byval %arg2, [2 x <4 x i32>] addrspace(2)* byval %arg3, [17 x <4 x i32>] addrspace(2)* inreg %arg4, [17 x <4 x i32>] addrspace(2)* inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9) { define amdgpu_vs void @main([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <32 x i8>] addrspace(4)* byval %arg2, [2 x <4 x i32>] addrspace(4)* byval %arg3, [17 x <4 x i32>] addrspace(4)* inreg %arg4, [17 x <4 x i32>] addrspace(4)* inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9) {
main_body: main_body:
%tmp = getelementptr [2 x <4 x i32>], [2 x <4 x i32>] addrspace(2)* %arg3, i64 0, i32 1 %tmp = getelementptr [2 x <4 x i32>], [2 x <4 x i32>] addrspace(4)* %arg3, i64 0, i32 1
%tmp10 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp10 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp11 = shl i32 %arg6, 2 %tmp11 = shl i32 %arg6, 2
%tmp12 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0) %tmp12 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp10, i32 0, i32 0, i32 0, i32 0, i32 0, i32 1, i32 1, i32 0)
%tmp13 = bitcast i32 %tmp12 to float %tmp13 = bitcast i32 %tmp12 to float
%tmp14 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp10, i32 %tmp11, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0) %tmp14 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp10, i32 %tmp11, i32 0, i32 0, i32 1, i32 0, i32 1, i32 1, i32 0)
%tmp15 = bitcast i32 %tmp14 to float %tmp15 = bitcast i32 %tmp14 to float
%tmp16 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp10, i32 %tmp11, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 0) %tmp16 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp10, i32 %tmp11, i32 0, i32 0, i32 0, i32 1, i32 1, i32 1, i32 0)
%tmp17 = bitcast i32 %tmp16 to float %tmp17 = bitcast i32 %tmp16 to float
%tmp18 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<4 x i32> %tmp10, <2 x i32> zeroinitializer, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 0) %tmp18 = call i32 @llvm.SI.buffer.load.dword.i32.v2i32(<4 x i32> %tmp10, <2 x i32> zeroinitializer, i32 0, i32 0, i32 1, i32 1, i32 1, i32 1, i32 0)
Show All 26 Lines

test/CodeGen/AMDGPU/llvm.amdgcn.dispatch.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target
; GCN-LABEL: {{^}}test: ; GCN-LABEL: {{^}}test:
; GCN: enable_sgpr_dispatch_ptr = 1 ; GCN: enable_sgpr_dispatch_ptr = 1
; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
define amdgpu_kernel void @test(i32 addrspace(1)* %out) { define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
%header_ptr = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %header_ptr = bitcast i8 addrspace(4)* %dispatch_ptr to i32 addrspace(4)*
%value = load i32, i32 addrspace(2)* %header_ptr %value = load i32, i32 addrspace(4)* %header_ptr
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
declare noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 declare noalias i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
attributes #0 = { readnone } attributes #0 = { readnone }

test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.hsa.ll

; RUN: not llc -mtriple=amdgcn-amd-amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-amd-amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test_kernel{{.*}}: non-hsa intrinsic with hsa target ; ERROR: in function test_kernel{{.*}}: non-hsa intrinsic with hsa target
define amdgpu_kernel void @test_kernel(i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @test_kernel(i32 addrspace(1)* %out) #1 {
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr()
%header_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %header_ptr = bitcast i8 addrspace(4)* %implicit_buffer_ptr to i32 addrspace(4)*
%value = load i32, i32 addrspace(2)* %header_ptr %value = load i32, i32 addrspace(4)* %header_ptr
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; ERROR: in function test_func{{.*}}: non-hsa intrinsic with hsa target ; ERROR: in function test_func{{.*}}: non-hsa intrinsic with hsa target
define void @test_func(i32 addrspace(1)* %out) #1 { define void @test_func(i32 addrspace(1)* %out) #1 {
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr()
%header_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %header_ptr = bitcast i8 addrspace(4)* %implicit_buffer_ptr to i32 addrspace(4)*
%value = load i32, i32 addrspace(2)* %header_ptr %value = load i32, i32 addrspace(4)* %header_ptr
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
declare i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Requires stack object to not assert ; FIXME: Requires stack object to not assert
; GCN-LABEL: {{^}}test_ps: ; GCN-LABEL: {{^}}test_ps:
; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GCN: buffer_store_dword v0, off, s[4:7], s2 offset:4 ; GCN: buffer_store_dword v0, off, s[4:7], s2 offset:4
; GCN: s_load_dword s{{[0-9]+}}, s[0:1], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[0:1], 0x0
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: ; return ; GCN-NEXT: ; return
define amdgpu_ps i32 @test_ps() #1 { define amdgpu_ps i32 @test_ps() #1 {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr()
%buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %buffer_ptr = bitcast i8 addrspace(4)* %implicit_buffer_ptr to i32 addrspace(4)*
%value = load volatile i32, i32 addrspace(2)* %buffer_ptr %value = load volatile i32, i32 addrspace(4)* %buffer_ptr
ret i32 %value ret i32 %value
} }
; GCN-LABEL: {{^}}test_cs: ; GCN-LABEL: {{^}}test_cs:
; GCN: s_mov_b64 s[4:5], s[0:1] ; GCN: s_mov_b64 s[4:5], s[0:1]
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:4 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:4
; GCN: s_load_dword s0, s[0:1], 0x0 ; GCN: s_load_dword s0, s[0:1], 0x0
define amdgpu_cs i32 @test_cs() #1 { define amdgpu_cs i32 @test_cs() #1 {
%alloca = alloca i32, addrspace(5) %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32 addrspace(5)* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr()
%buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %buffer_ptr = bitcast i8 addrspace(4)* %implicit_buffer_ptr to i32 addrspace(4)*
%value = load volatile i32, i32 addrspace(2)* %buffer_ptr %value = load volatile i32, i32 addrspace(4)* %buffer_ptr
ret i32 %value ret i32 %value
} }
declare i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.implicit.buffer.ptr() #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/AMDGPU/llvm.amdgcn.implicitarg.ptr.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-NOENV %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,HSA,HSA-OPENCL %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,MESA %s
; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty: ; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
; GCN: enable_sgpr_kernarg_segment_ptr = 1 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA-NOENV: kernarg_segment_byte_size = 0 ; HSA-NOENV: kernarg_segment_byte_size = 0
; HSA-OPENCL: kernarg_segment_byte_size = 32 ; HSA-OPENCL: kernarg_segment_byte_size = 32
; MESA: kernarg_segment_byte_size = 16 ; MESA: kernarg_segment_byte_size = 16
; HSA: s_load_dword s0, s[4:5], 0x0 ; HSA: s_load_dword s0, s[4:5], 0x0
define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 { define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
%implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%cast = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%load = load volatile i32, i32 addrspace(2)* %cast %load = load volatile i32, i32 addrspace(4)* %cast
ret void ret void
} }
; GCN-LABEL: {{^}}kernel_implicitarg_ptr: ; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
; GCN: enable_sgpr_kernarg_segment_ptr = 1 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA-NOENV: kernarg_segment_byte_size = 112 ; HSA-NOENV: kernarg_segment_byte_size = 112
; HSA-OPENCL: kernarg_segment_byte_size = 144 ; HSA-OPENCL: kernarg_segment_byte_size = 144
; MESA: kernarg_segment_byte_size = 464 ; MESA: kernarg_segment_byte_size = 464
; HSA: s_load_dword s0, s[4:5], 0x1c ; HSA: s_load_dword s0, s[4:5], 0x1c
define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 { define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
%implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%cast = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%load = load volatile i32, i32 addrspace(2)* %cast %load = load volatile i32, i32 addrspace(4)* %cast
ret void ret void
} }
; GCN-LABEL: {{^}}func_implicitarg_ptr: ; GCN-LABEL: {{^}}func_implicitarg_ptr:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} ; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @func_implicitarg_ptr() #1 { define void @func_implicitarg_ptr() #1 {
%implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%cast = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* %cast = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%load = load volatile i32, i32 addrspace(2)* %cast %load = load volatile i32, i32 addrspace(4)* %cast
ret void ret void
} }
; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty: ; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
; GCN: enable_sgpr_kernarg_segment_ptr = 1 ; GCN: enable_sgpr_kernarg_segment_ptr = 1
; HSA-NOENV: kernarg_segment_byte_size = 0 ; HSA-NOENV: kernarg_segment_byte_size = 0
; HSA-OPENCL: kernarg_segment_byte_size = 32 ; HSA-OPENCL: kernarg_segment_byte_size = 32
; MESA: kernarg_segment_byte_size = 16 ; MESA: kernarg_segment_byte_size = 16
Show All 29 Linesdefine void @func_call_implicitarg_ptr_func() #1 {
ret void ret void
} }
; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr: ; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}} ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0{{$}}
; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0{{$}} ; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0{{$}}
define void @func_kernarg_implicitarg_ptr() #1 { define void @func_kernarg_implicitarg_ptr() #1 {
%kernarg.segment.ptr = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernarg.segment.ptr = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%implicitarg.ptr = call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%cast.kernarg.segment.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)* %cast.kernarg.segment.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
%cast.implicitarg = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* %cast.implicitarg = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%load0 = load volatile i32, i32 addrspace(2)* %cast.kernarg.segment.ptr %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
%load1 = load volatile i32, i32 addrspace(2)* %cast.implicitarg %load1 = load volatile i32, i32 addrspace(4)* %cast.implicitarg
ret void ret void
} }
; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func: ; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func:
; GCN: s_mov_b64 s[6:7], s[4:5] ; GCN: s_mov_b64 s[6:7], s[4:5]
; HSA: s_add_u32 s8, s6, 0x70 ; HSA: s_add_u32 s8, s6, 0x70
; MESA: s_add_u32 s8, s6, 0x1c0 ; MESA: s_add_u32 s8, s6, 0x1c0
; GCN: s_addc_u32 s9, s7, 0 ; GCN: s_addc_u32 s9, s7, 0
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 { define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 {
call void @func_kernarg_implicitarg_ptr() call void @func_kernarg_implicitarg_ptr()
ret void ret void
} }
declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #2 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #2
declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #2 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #2
attributes #0 = { nounwind noinline } attributes #0 = { nounwind noinline }
attributes #1 = { nounwind noinline } attributes #1 = { nounwind noinline }
attributes #2 = { nounwind readnone speculatable } attributes #2 = { nounwind readnone speculatable }

test/CodeGen/AMDGPU/llvm.amdgcn.kernarg.segment.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s ; RUN: llc -mtriple=amdgcn--amdhsa-opencl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,OS-MESA3D,MESA,ALL %s
; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s ; RUN: llc -mtriple=amdgcn-mesa-unknown -verify-machineinstrs < %s | FileCheck -check-prefixes=OS-UNKNOWN,MESA,ALL %s
; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgiz -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-NOENV %s
; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s ; RUN: llc -mtriple=amdgcn--amdhsa-amdgizcl -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=CO-V2,HSA,ALL,HSA-OPENCL %s
; ALL-LABEL: {{^}}test: ; ALL-LABEL: {{^}}test:
; CO-V2: enable_sgpr_kernarg_segment_ptr = 1 ; CO-V2: enable_sgpr_kernarg_segment_ptr = 1
; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa ; CO-V2: s_load_dword s{{[0-9]+}}, s[4:5], 0xa
; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa ; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0xa
define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @test(i32 addrspace(1)* %out) #1 {
%kernarg.segment.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%header.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)* %header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
%gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
%value = load i32, i32 addrspace(2)* %gep %value = load i32, i32 addrspace(4)* %gep
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}test_implicit: ; ALL-LABEL: {{^}}test_implicit:
; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15 ; 10 + 9 (36 prepended implicit bytes) + 2(out pointer) = 21 = 0x15
; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15 ; OS-UNKNOWN: s_load_dword s{{[0-9]+}}, s[0:1], 0x15
define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @test_implicit(i32 addrspace(1)* %out) #1 {
%implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%header.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* %header.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
%value = load i32, i32 addrspace(2)* %gep %value = load i32, i32 addrspace(4)* %gep
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}test_implicit_alignment ; ALL-LABEL: {{^}}test_implicit_alignment
; HSA-NOENV: kernarg_segment_byte_size = 10 ; HSA-NOENV: kernarg_segment_byte_size = 10
; HSA-OPENCL: kernarg_segment_byte_size = 48 ; HSA-OPENCL: kernarg_segment_byte_size = 48
; OS-MESA3D: kernarg_segment_byte_size = 28 ; OS-MESA3D: kernarg_segment_byte_size = 28
; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc ; OS-UNKNOWN: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0xc
; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4 ; HSA: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x4
; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3 ; OS-MESA3D: s_load_dword [[VAL:s[0-9]+]], s[{{[0-9]+:[0-9]+}}], 0x3
; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]] ; ALL: v_mov_b32_e32 [[V_VAL:v[0-9]+]], [[VAL]]
; MESA: buffer_store_dword [[V_VAL]] ; MESA: buffer_store_dword [[V_VAL]]
; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]] ; HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[V_VAL]]
define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 { define amdgpu_kernel void @test_implicit_alignment(i32 addrspace(1)* %out, <2 x i8> %in) #1 {
%implicitarg.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %implicitarg.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%arg.ptr = bitcast i8 addrspace(2)* %implicitarg.ptr to i32 addrspace(2)* %arg.ptr = bitcast i8 addrspace(4)* %implicitarg.ptr to i32 addrspace(4)*
%val = load i32, i32 addrspace(2)* %arg.ptr %val = load i32, i32 addrspace(4)* %arg.ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}test_no_kernargs: ; ALL-LABEL: {{^}}test_no_kernargs:
; HSA: enable_sgpr_kernarg_segment_ptr = 1 ; HSA: enable_sgpr_kernarg_segment_ptr = 1
; HSA: s_load_dword s{{[0-9]+}}, s[4:5] ; HSA: s_load_dword s{{[0-9]+}}, s[4:5]
define amdgpu_kernel void @test_no_kernargs() #1 { define amdgpu_kernel void @test_no_kernargs() #1 {
%kernarg.segment.ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernarg.segment.ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%header.ptr = bitcast i8 addrspace(2)* %kernarg.segment.ptr to i32 addrspace(2)* %header.ptr = bitcast i8 addrspace(4)* %kernarg.segment.ptr to i32 addrspace(4)*
%gep = getelementptr i32, i32 addrspace(2)* %header.ptr, i64 10 %gep = getelementptr i32, i32 addrspace(4)* %header.ptr, i64 10
%value = load i32, i32 addrspace(2)* %gep %value = load i32, i32 addrspace(4)* %gep
store volatile i32 %value, i32 addrspace(1)* undef store volatile i32 %value, i32 addrspace(1)* undef
ret void ret void
} }
declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #0
declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/AMDGPU/llvm.amdgcn.queue.ptr.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -verify-machineinstrs < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target ; ERROR: in function test{{.*}}: unsupported hsa intrinsic without hsa target
; GCN-LABEL: {{^}}test: ; GCN-LABEL: {{^}}test:
; GCN: enable_sgpr_queue_ptr = 1 ; GCN: enable_sgpr_queue_ptr = 1
; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[4:5], 0x0
define amdgpu_kernel void @test(i32 addrspace(1)* %out) { define amdgpu_kernel void @test(i32 addrspace(1)* %out) {
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
%header_ptr = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %header_ptr = bitcast i8 addrspace(4)* %queue_ptr to i32 addrspace(4)*
%value = load i32, i32 addrspace(2)* %header_ptr %value = load i32, i32 addrspace(4)* %header_ptr
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
declare noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 declare noalias i8 addrspace(4)* @llvm.amdgcn.queue.ptr() #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

test/CodeGen/AMDGPU/llvm.memcpy.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
declare void @llvm.memcpy.p3i8.p3i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(3)* nocapture, i32, i1) nounwind declare void @llvm.memcpy.p3i8.p3i8.i32(i8 addrspace(3)* nocapture, i8 addrspace(3)* nocapture, i32, i1) nounwind
declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(1)* nocapture, i64, i1) nounwind
declare void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(2)* nocapture, i64, i1) nounwind declare void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* nocapture, i8 addrspace(4)* nocapture, i64, i1) nounwind
; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align1: ; FUNC-LABEL: {{^}}test_small_memcpy_i64_lds_to_lds_align1:
; SI-DAG: ds_read_u8 ; SI-DAG: ds_read_u8
; SI-DAG: ds_read_u8 ; SI-DAG: ds_read_u8
; SI-DAG: ds_read_u8 ; SI-DAG: ds_read_u8
; SI-DAG: ds_read_u8 ; SI-DAG: ds_read_u8
; SI-DAG: ds_read_u8 ; SI-DAG: ds_read_u8
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define amdgpu_kernel void @test_small_memcpy_i64_global_to_global_align16(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind { define amdgpu_kernel void @test_small_memcpy_i64_global_to_global_align16(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in) nounwind {
%bcin = bitcast i64 addrspace(1)* %in to i8 addrspace(1)* %bcin = bitcast i64 addrspace(1)* %in to i8 addrspace(1)*
%bcout = bitcast i64 addrspace(1)* %out to i8 addrspace(1)* %bcout = bitcast i64 addrspace(1)* %out to i8 addrspace(1)*
call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* align 16 %bcout, i8 addrspace(1)* align 16 %bcin, i64 32, i1 false) nounwind call void @llvm.memcpy.p1i8.p1i8.i64(i8 addrspace(1)* align 16 %bcout, i8 addrspace(1)* align 16 %bcin, i64 32, i1 false) nounwind
ret void ret void
} }
; Test shouldConvertConstantLoadToIntImm ; Test shouldConvertConstantLoadToIntImm
@hello.align4 = private unnamed_addr addrspace(2) constant [16 x i8] c"constant string\00", align 4 @hello.align4 = private unnamed_addr addrspace(4) constant [16 x i8] c"constant string\00", align 4
@hello.align1 = private unnamed_addr addrspace(2) constant [16 x i8] c"constant string\00", align 1 @hello.align1 = private unnamed_addr addrspace(4) constant [16 x i8] c"constant string\00", align 1
; FUNC-LABEL: {{^}}test_memcpy_const_string_align4: ; FUNC-LABEL: {{^}}test_memcpy_const_string_align4:
; SI: s_getpc_b64 ; SI: s_getpc_b64
; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, hello.align4+20 ; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, hello.align4+20
; SI: s_addc_u32 ; SI: s_addc_u32
; SI-DAG: s_load_dwordx4 ; SI-DAG: s_load_dwordx4
; SI-DAG: s_load_dwordx4 ; SI-DAG: s_load_dwordx4
; SI-DAG: s_load_dwordx2 ; SI-DAG: s_load_dwordx2
; SI-DAG: buffer_store_dwordx4 ; SI-DAG: buffer_store_dwordx4
; SI-DAG: buffer_store_dwordx4 ; SI-DAG: buffer_store_dwordx4
define amdgpu_kernel void @test_memcpy_const_string_align4(i8 addrspace(1)* noalias %out) nounwind { define amdgpu_kernel void @test_memcpy_const_string_align4(i8 addrspace(1)* noalias %out) nounwind {
%str = bitcast [16 x i8] addrspace(2)* @hello.align4 to i8 addrspace(2)* %str = bitcast [16 x i8] addrspace(4)* @hello.align4 to i8 addrspace(4)*
call void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* align 4 %out, i8 addrspace(2)* align 4 %str, i64 32, i1 false) call void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* align 4 %out, i8 addrspace(4)* align 4 %str, i64 32, i1 false)
ret void ret void
} }
; FUNC-LABEL: {{^}}test_memcpy_const_string_align1: ; FUNC-LABEL: {{^}}test_memcpy_const_string_align1:
; SI-NOT: buffer_load ; SI-NOT: buffer_load
; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x69 ; SI: v_mov_b32_e32 v{{[0-9]+}}, 0x69
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @test_memcpy_const_string_align1(i8 addrspace(1)* noalias %out) nounwind { define amdgpu_kernel void @test_memcpy_const_string_align1(i8 addrspace(1)* noalias %out) nounwind {
%str = bitcast [16 x i8] addrspace(2)* @hello.align1 to i8 addrspace(2)* %str = bitcast [16 x i8] addrspace(4)* @hello.align1 to i8 addrspace(4)*
call void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* %out, i8 addrspace(2)* %str, i64 32, i1 false) call void @llvm.memcpy.p1i8.p2i8.i64(i8 addrspace(1)* %out, i8 addrspace(4)* %str, i64 32, i1 false)
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/load-constant-f64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn-amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_f64: ; FUNC-LABEL: {{^}}constant_load_f64:
; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}] ; GCN: s_load_dwordx2 s[{{[0-9]+:[0-9]+}}]
; GCN-NOHSA: buffer_store_dwordx2 ; GCN-NOHSA: buffer_store_dwordx2
; GCN-HSA: flat_store_dwordx2 ; GCN-HSA: flat_store_dwordx2
define amdgpu_kernel void @constant_load_f64(double addrspace(1)* %out, double addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_f64(double addrspace(1)* %out, double addrspace(4)* %in) #0 {
%ld = load double, double addrspace(2)* %in %ld = load double, double addrspace(4)* %in
store double %ld, double addrspace(1)* %out store double %ld, double addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-constant-i1.ll

; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mtriple=amdgcn---amdgiz -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=FUNC %s
; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mtriple=r600---amdgiz -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i1: ; FUNC-LABEL: {{^}}constant_load_i1:
; GCN: buffer_load_ubyte ; GCN: buffer_load_ubyte
; GCN: v_and_b32_e32 v{{[0-9]+}}, 1 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1
; GCN: buffer_store_byte ; GCN: buffer_store_byte
; EG: VTX_READ_8 ; EG: VTX_READ_8
; EG: AND_INT ; EG: AND_INT
define amdgpu_kernel void @constant_load_i1(i1 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_i1(i1 addrspace(1)* %out, i1 addrspace(4)* nocapture %in) #0 {
%load = load i1, i1 addrspace(2)* %in %load = load i1, i1 addrspace(4)* %in
store i1 %load, i1 addrspace(1)* %out store i1 %load, i1 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v2i1: ; FUNC-LABEL: {{^}}constant_load_v2i1:
define amdgpu_kernel void @constant_load_v2i1(<2 x i1> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_v2i1(<2 x i1> addrspace(1)* %out, <2 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <2 x i1>, <2 x i1> addrspace(2)* %in %load = load <2 x i1>, <2 x i1> addrspace(4)* %in
store <2 x i1> %load, <2 x i1> addrspace(1)* %out store <2 x i1> %load, <2 x i1> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v3i1: ; FUNC-LABEL: {{^}}constant_load_v3i1:
define amdgpu_kernel void @constant_load_v3i1(<3 x i1> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_v3i1(<3 x i1> addrspace(1)* %out, <3 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <3 x i1>, <3 x i1> addrspace(2)* %in %load = load <3 x i1>, <3 x i1> addrspace(4)* %in
store <3 x i1> %load, <3 x i1> addrspace(1)* %out store <3 x i1> %load, <3 x i1> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v4i1: ; FUNC-LABEL: {{^}}constant_load_v4i1:
define amdgpu_kernel void @constant_load_v4i1(<4 x i1> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_v4i1(<4 x i1> addrspace(1)* %out, <4 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <4 x i1>, <4 x i1> addrspace(2)* %in %load = load <4 x i1>, <4 x i1> addrspace(4)* %in
store <4 x i1> %load, <4 x i1> addrspace(1)* %out store <4 x i1> %load, <4 x i1> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v8i1: ; FUNC-LABEL: {{^}}constant_load_v8i1:
define amdgpu_kernel void @constant_load_v8i1(<8 x i1> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_v8i1(<8 x i1> addrspace(1)* %out, <8 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <8 x i1>, <8 x i1> addrspace(2)* %in %load = load <8 x i1>, <8 x i1> addrspace(4)* %in
store <8 x i1> %load, <8 x i1> addrspace(1)* %out store <8 x i1> %load, <8 x i1> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v16i1: ; FUNC-LABEL: {{^}}constant_load_v16i1:
define amdgpu_kernel void @constant_load_v16i1(<16 x i1> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_v16i1(<16 x i1> addrspace(1)* %out, <16 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <16 x i1>, <16 x i1> addrspace(2)* %in %load = load <16 x i1>, <16 x i1> addrspace(4)* %in
store <16 x i1> %load, <16 x i1> addrspace(1)* %out store <16 x i1> %load, <16 x i1> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v32i1: ; FUNC-LABEL: {{^}}constant_load_v32i1:
define amdgpu_kernel void @constant_load_v32i1(<32 x i1> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_v32i1(<32 x i1> addrspace(1)* %out, <32 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <32 x i1>, <32 x i1> addrspace(2)* %in %load = load <32 x i1>, <32 x i1> addrspace(4)* %in
store <32 x i1> %load, <32 x i1> addrspace(1)* %out store <32 x i1> %load, <32 x i1> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v64i1: ; FUNC-LABEL: {{^}}constant_load_v64i1:
define amdgpu_kernel void @constant_load_v64i1(<64 x i1> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_load_v64i1(<64 x i1> addrspace(1)* %out, <64 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <64 x i1>, <64 x i1> addrspace(2)* %in %load = load <64 x i1>, <64 x i1> addrspace(4)* %in
store <64 x i1> %load, <64 x i1> addrspace(1)* %out store <64 x i1> %load, <64 x i1> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i1_to_i32: ; FUNC-LABEL: {{^}}constant_zextload_i1_to_i32:
; GCN: buffer_load_ubyte ; GCN: buffer_load_ubyte
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @constant_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(4)* nocapture %in) #0 {
%a = load i1, i1 addrspace(2)* %in %a = load i1, i1 addrspace(4)* %in
%ext = zext i1 %a to i32 %ext = zext i1 %a to i32
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i1_to_i32: ; FUNC-LABEL: {{^}}constant_sextload_i1_to_i32:
; GCN: buffer_load_ubyte ; GCN: buffer_load_ubyte
; GCN: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}} ; GCN: v_bfe_i32 {{v[0-9]+}}, {{v[0-9]+}}, 0, 1{{$}}
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; EG: VTX_READ_8 ; EG: VTX_READ_8
; EG: BFE_INT ; EG: BFE_INT
define amdgpu_kernel void @constant_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_i1_to_i32(i32 addrspace(1)* %out, i1 addrspace(4)* nocapture %in) #0 {
%a = load i1, i1 addrspace(2)* %in %a = load i1, i1 addrspace(4)* %in
%ext = sext i1 %a to i32 %ext = sext i1 %a to i32
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i32: ; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i32:
define amdgpu_kernel void @constant_zextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <1 x i1>, <1 x i1> addrspace(2)* %in %load = load <1 x i1>, <1 x i1> addrspace(4)* %in
%ext = zext <1 x i1> %load to <1 x i32> %ext = zext <1 x i1> %load to <1 x i32>
store <1 x i32> %ext, <1 x i32> addrspace(1)* %out store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i32: ; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i32:
define amdgpu_kernel void @constant_sextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v1i1_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <1 x i1>, <1 x i1> addrspace(2)* %in %load = load <1 x i1>, <1 x i1> addrspace(4)* %in
%ext = sext <1 x i1> %load to <1 x i32> %ext = sext <1 x i1> %load to <1 x i32>
store <1 x i32> %ext, <1 x i32> addrspace(1)* %out store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i32: ; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i32:
define amdgpu_kernel void @constant_zextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <2 x i1>, <2 x i1> addrspace(2)* %in %load = load <2 x i1>, <2 x i1> addrspace(4)* %in
%ext = zext <2 x i1> %load to <2 x i32> %ext = zext <2 x i1> %load to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i32: ; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i32:
define amdgpu_kernel void @constant_sextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v2i1_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <2 x i1>, <2 x i1> addrspace(2)* %in %load = load <2 x i1>, <2 x i1> addrspace(4)* %in
%ext = sext <2 x i1> %load to <2 x i32> %ext = sext <2 x i1> %load to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i32: ; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i32:
define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <3 x i1>, <3 x i1> addrspace(2)* %in %load = load <3 x i1>, <3 x i1> addrspace(4)* %in
%ext = zext <3 x i1> %load to <3 x i32> %ext = zext <3 x i1> %load to <3 x i32>
store <3 x i32> %ext, <3 x i32> addrspace(1)* %out store <3 x i32> %ext, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i32: ; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i32:
define amdgpu_kernel void @constant_sextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v3i1_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <3 x i1>, <3 x i1> addrspace(2)* %in %load = load <3 x i1>, <3 x i1> addrspace(4)* %in
%ext = sext <3 x i1> %load to <3 x i32> %ext = sext <3 x i1> %load to <3 x i32>
store <3 x i32> %ext, <3 x i32> addrspace(1)* %out store <3 x i32> %ext, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i32: ; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i32:
define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <4 x i1>, <4 x i1> addrspace(2)* %in %load = load <4 x i1>, <4 x i1> addrspace(4)* %in
%ext = zext <4 x i1> %load to <4 x i32> %ext = zext <4 x i1> %load to <4 x i32>
store <4 x i32> %ext, <4 x i32> addrspace(1)* %out store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i32: ; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i32:
define amdgpu_kernel void @constant_sextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v4i1_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <4 x i1>, <4 x i1> addrspace(2)* %in %load = load <4 x i1>, <4 x i1> addrspace(4)* %in
%ext = sext <4 x i1> %load to <4 x i32> %ext = sext <4 x i1> %load to <4 x i32>
store <4 x i32> %ext, <4 x i32> addrspace(1)* %out store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i32: ; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i32:
define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <8 x i1>, <8 x i1> addrspace(2)* %in %load = load <8 x i1>, <8 x i1> addrspace(4)* %in
%ext = zext <8 x i1> %load to <8 x i32> %ext = zext <8 x i1> %load to <8 x i32>
store <8 x i32> %ext, <8 x i32> addrspace(1)* %out store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i32: ; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i32:
define amdgpu_kernel void @constant_sextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v8i1_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <8 x i1>, <8 x i1> addrspace(2)* %in %load = load <8 x i1>, <8 x i1> addrspace(4)* %in
%ext = sext <8 x i1> %load to <8 x i32> %ext = sext <8 x i1> %load to <8 x i32>
store <8 x i32> %ext, <8 x i32> addrspace(1)* %out store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i32: ; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i32:
define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <16 x i1>, <16 x i1> addrspace(2)* %in %load = load <16 x i1>, <16 x i1> addrspace(4)* %in
%ext = zext <16 x i1> %load to <16 x i32> %ext = zext <16 x i1> %load to <16 x i32>
store <16 x i32> %ext, <16 x i32> addrspace(1)* %out store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i32: ; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i32:
define amdgpu_kernel void @constant_sextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v16i1_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <16 x i1>, <16 x i1> addrspace(2)* %in %load = load <16 x i1>, <16 x i1> addrspace(4)* %in
%ext = sext <16 x i1> %load to <16 x i32> %ext = sext <16 x i1> %load to <16 x i32>
store <16 x i32> %ext, <16 x i32> addrspace(1)* %out store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i32: ; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i32:
define amdgpu_kernel void @constant_zextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <32 x i1>, <32 x i1> addrspace(2)* %in %load = load <32 x i1>, <32 x i1> addrspace(4)* %in
%ext = zext <32 x i1> %load to <32 x i32> %ext = zext <32 x i1> %load to <32 x i32>
store <32 x i32> %ext, <32 x i32> addrspace(1)* %out store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i32: ; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i32:
define amdgpu_kernel void @constant_sextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v32i1_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <32 x i1>, <32 x i1> addrspace(2)* %in %load = load <32 x i1>, <32 x i1> addrspace(4)* %in
%ext = sext <32 x i1> %load to <32 x i32> %ext = sext <32 x i1> %load to <32 x i32>
store <32 x i32> %ext, <32 x i32> addrspace(1)* %out store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i32: ; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i32:
define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <64 x i1>, <64 x i1> addrspace(2)* %in %load = load <64 x i1>, <64 x i1> addrspace(4)* %in
%ext = zext <64 x i1> %load to <64 x i32> %ext = zext <64 x i1> %load to <64 x i32>
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i32: ; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i32:
define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v64i1_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <64 x i1>, <64 x i1> addrspace(2)* %in %load = load <64 x i1>, <64 x i1> addrspace(4)* %in
%ext = sext <64 x i1> %load to <64 x i32> %ext = sext <64 x i1> %load to <64 x i32>
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i1_to_i64: ; FUNC-LABEL: {{^}}constant_zextload_i1_to_i64:
; GCN-DAG: buffer_load_ubyte [[LOAD:v[0-9]+]], ; GCN-DAG: buffer_load_ubyte [[LOAD:v[0-9]+]],
; GCN-DAG: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}} ; GCN-DAG: v_mov_b32_e32 {{v[0-9]+}}, 0{{$}}
; GCN-DAG: v_and_b32_e32 {{v[0-9]+}}, 1, [[LOAD]] ; GCN-DAG: v_and_b32_e32 {{v[0-9]+}}, 1, [[LOAD]]
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @constant_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(4)* nocapture %in) #0 {
%a = load i1, i1 addrspace(2)* %in %a = load i1, i1 addrspace(4)* %in
%ext = zext i1 %a to i64 %ext = zext i1 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i1_to_i64: ; FUNC-LABEL: {{^}}constant_sextload_i1_to_i64:
; GCN: buffer_load_ubyte [[LOAD:v[0-9]+]], ; GCN: buffer_load_ubyte [[LOAD:v[0-9]+]],
; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}} ; GCN: v_bfe_i32 [[BFE:v[0-9]+]], {{v[0-9]+}}, 0, 1{{$}}
; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]] ; GCN: v_ashrrev_i32_e32 v{{[0-9]+}}, 31, [[BFE]]
; GCN: buffer_store_dwordx2 ; GCN: buffer_store_dwordx2
define amdgpu_kernel void @constant_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_i1_to_i64(i64 addrspace(1)* %out, i1 addrspace(4)* nocapture %in) #0 {
%a = load i1, i1 addrspace(2)* %in %a = load i1, i1 addrspace(4)* %in
%ext = sext i1 %a to i64 %ext = sext i1 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i64: ; FUNC-LABEL: {{^}}constant_zextload_v1i1_to_v1i64:
define amdgpu_kernel void @constant_zextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <1 x i1>, <1 x i1> addrspace(2)* %in %load = load <1 x i1>, <1 x i1> addrspace(4)* %in
%ext = zext <1 x i1> %load to <1 x i64> %ext = zext <1 x i1> %load to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i64: ; FUNC-LABEL: {{^}}constant_sextload_v1i1_to_v1i64:
define amdgpu_kernel void @constant_sextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v1i1_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <1 x i1>, <1 x i1> addrspace(2)* %in %load = load <1 x i1>, <1 x i1> addrspace(4)* %in
%ext = sext <1 x i1> %load to <1 x i64> %ext = sext <1 x i1> %load to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i64: ; FUNC-LABEL: {{^}}constant_zextload_v2i1_to_v2i64:
define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <2 x i1>, <2 x i1> addrspace(2)* %in %load = load <2 x i1>, <2 x i1> addrspace(4)* %in
%ext = zext <2 x i1> %load to <2 x i64> %ext = zext <2 x i1> %load to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i64: ; FUNC-LABEL: {{^}}constant_sextload_v2i1_to_v2i64:
define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v2i1_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <2 x i1>, <2 x i1> addrspace(2)* %in %load = load <2 x i1>, <2 x i1> addrspace(4)* %in
%ext = sext <2 x i1> %load to <2 x i64> %ext = sext <2 x i1> %load to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i64: ; FUNC-LABEL: {{^}}constant_zextload_v3i1_to_v3i64:
define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <3 x i1>, <3 x i1> addrspace(2)* %in %load = load <3 x i1>, <3 x i1> addrspace(4)* %in
%ext = zext <3 x i1> %load to <3 x i64> %ext = zext <3 x i1> %load to <3 x i64>
store <3 x i64> %ext, <3 x i64> addrspace(1)* %out store <3 x i64> %ext, <3 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i64: ; FUNC-LABEL: {{^}}constant_sextload_v3i1_to_v3i64:
define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v3i1_to_v3i64(<3 x i64> addrspace(1)* %out, <3 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <3 x i1>, <3 x i1> addrspace(2)* %in %load = load <3 x i1>, <3 x i1> addrspace(4)* %in
%ext = sext <3 x i1> %load to <3 x i64> %ext = sext <3 x i1> %load to <3 x i64>
store <3 x i64> %ext, <3 x i64> addrspace(1)* %out store <3 x i64> %ext, <3 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i64: ; FUNC-LABEL: {{^}}constant_zextload_v4i1_to_v4i64:
define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <4 x i1>, <4 x i1> addrspace(2)* %in %load = load <4 x i1>, <4 x i1> addrspace(4)* %in
%ext = zext <4 x i1> %load to <4 x i64> %ext = zext <4 x i1> %load to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i64: ; FUNC-LABEL: {{^}}constant_sextload_v4i1_to_v4i64:
define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v4i1_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <4 x i1>, <4 x i1> addrspace(2)* %in %load = load <4 x i1>, <4 x i1> addrspace(4)* %in
%ext = sext <4 x i1> %load to <4 x i64> %ext = sext <4 x i1> %load to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i64: ; FUNC-LABEL: {{^}}constant_zextload_v8i1_to_v8i64:
define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <8 x i1>, <8 x i1> addrspace(2)* %in %load = load <8 x i1>, <8 x i1> addrspace(4)* %in
%ext = zext <8 x i1> %load to <8 x i64> %ext = zext <8 x i1> %load to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i64: ; FUNC-LABEL: {{^}}constant_sextload_v8i1_to_v8i64:
define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v8i1_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <8 x i1>, <8 x i1> addrspace(2)* %in %load = load <8 x i1>, <8 x i1> addrspace(4)* %in
%ext = sext <8 x i1> %load to <8 x i64> %ext = sext <8 x i1> %load to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i64: ; FUNC-LABEL: {{^}}constant_zextload_v16i1_to_v16i64:
define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <16 x i1>, <16 x i1> addrspace(2)* %in %load = load <16 x i1>, <16 x i1> addrspace(4)* %in
%ext = zext <16 x i1> %load to <16 x i64> %ext = zext <16 x i1> %load to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i64: ; FUNC-LABEL: {{^}}constant_sextload_v16i1_to_v16i64:
define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v16i1_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <16 x i1>, <16 x i1> addrspace(2)* %in %load = load <16 x i1>, <16 x i1> addrspace(4)* %in
%ext = sext <16 x i1> %load to <16 x i64> %ext = sext <16 x i1> %load to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i64: ; FUNC-LABEL: {{^}}constant_zextload_v32i1_to_v32i64:
define amdgpu_kernel void @constant_zextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <32 x i1>, <32 x i1> addrspace(2)* %in %load = load <32 x i1>, <32 x i1> addrspace(4)* %in
%ext = zext <32 x i1> %load to <32 x i64> %ext = zext <32 x i1> %load to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i64: ; FUNC-LABEL: {{^}}constant_sextload_v32i1_to_v32i64:
define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v32i1_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <32 x i1>, <32 x i1> addrspace(2)* %in %load = load <32 x i1>, <32 x i1> addrspace(4)* %in
%ext = sext <32 x i1> %load to <32 x i64> %ext = sext <32 x i1> %load to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i64: ; FUNC-LABEL: {{^}}constant_zextload_v64i1_to_v64i64:
define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_zextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <64 x i1>, <64 x i1> addrspace(2)* %in %load = load <64 x i1>, <64 x i1> addrspace(4)* %in
%ext = zext <64 x i1> %load to <64 x i64> %ext = zext <64 x i1> %load to <64 x i64>
store <64 x i64> %ext, <64 x i64> addrspace(1)* %out store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i64: ; FUNC-LABEL: {{^}}constant_sextload_v64i1_to_v64i64:
define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(2)* nocapture %in) #0 { define amdgpu_kernel void @constant_sextload_v64i1_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i1> addrspace(4)* nocapture %in) #0 {
%load = load <64 x i1>, <64 x i1> addrspace(2)* %in %load = load <64 x i1>, <64 x i1> addrspace(4)* %in
%ext = sext <64 x i1> %load to <64 x i64> %ext = sext <64 x i1> %load to <64 x i64>
store <64 x i64> %ext, <64 x i64> addrspace(1)* %out store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-constant-i16.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-SI,FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-NOHSA,GCN-NOHSA-VI,FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i16: ; FUNC-LABEL: {{^}}constant_load_i16:
; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}} ; GCN-NOHSA: buffer_load_ushort v{{[0-9]+}}
; GCN-HSA: flat_load_ushort ; GCN-HSA: flat_load_ushort
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_i16(i16 addrspace(1)* %out, i16 addrspace(2)* %in) { define amdgpu_kernel void @constant_load_i16(i16 addrspace(1)* %out, i16 addrspace(4)* %in) {
entry: entry:
%ld = load i16, i16 addrspace(2)* %in %ld = load i16, i16 addrspace(4)* %in
store i16 %ld, i16 addrspace(1)* %out store i16 %ld, i16 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v2i16: ; FUNC-LABEL: {{^}}constant_load_v2i16:
; GCN: s_load_dword s ; GCN: s_load_dword s
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) { define amdgpu_kernel void @constant_load_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in) {
entry: entry:
%ld = load <2 x i16>, <2 x i16> addrspace(2)* %in %ld = load <2 x i16>, <2 x i16> addrspace(4)* %in
store <2 x i16> %ld, <2 x i16> addrspace(1)* %out store <2 x i16> %ld, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v3i16: ; FUNC-LABEL: {{^}}constant_load_v3i16:
; GCN: s_load_dwordx2 s ; GCN: s_load_dwordx2 s
; EG-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4, #1 ; EG-DAG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4, #1
define amdgpu_kernel void @constant_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { define amdgpu_kernel void @constant_load_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
entry: entry:
%ld = load <3 x i16>, <3 x i16> addrspace(2)* %in %ld = load <3 x i16>, <3 x i16> addrspace(4)* %in
store <3 x i16> %ld, <3 x i16> addrspace(1)* %out store <3 x i16> %ld, <3 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v4i16: ; FUNC-LABEL: {{^}}constant_load_v4i16:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) { define amdgpu_kernel void @constant_load_v4i16(<4 x i16> addrspace(1)* %out, <4 x i16> addrspace(4)* %in) {
entry: entry:
%ld = load <4 x i16>, <4 x i16> addrspace(2)* %in %ld = load <4 x i16>, <4 x i16> addrspace(4)* %in
store <4 x i16> %ld, <4 x i16> addrspace(1)* %out store <4 x i16> %ld, <4 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v8i16: ; FUNC-LABEL: {{^}}constant_load_v8i16:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) { define amdgpu_kernel void @constant_load_v8i16(<8 x i16> addrspace(1)* %out, <8 x i16> addrspace(4)* %in) {
entry: entry:
%ld = load <8 x i16>, <8 x i16> addrspace(2)* %in %ld = load <8 x i16>, <8 x i16> addrspace(4)* %in
store <8 x i16> %ld, <8 x i16> addrspace(1)* %out store <8 x i16> %ld, <8 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v16i16: ; FUNC-LABEL: {{^}}constant_load_v16i16:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_load_v16i16(<16 x i16> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) { define amdgpu_kernel void @constant_load_v16i16(<16 x i16> addrspace(1)* %out, <16 x i16> addrspace(4)* %in) {
entry: entry:
%ld = load <16 x i16>, <16 x i16> addrspace(2)* %in %ld = load <16 x i16>, <16 x i16> addrspace(4)* %in
store <16 x i16> %ld, <16 x i16> addrspace(1)* %out store <16 x i16> %ld, <16 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i16_to_i32: ; FUNC-LABEL: {{^}}constant_zextload_i16_to_i32:
; GCN-NOHSA: buffer_load_ushort ; GCN-NOHSA: buffer_load_ushort
; GCN-NOHSA: buffer_store_dword ; GCN-NOHSA: buffer_store_dword
; GCN-HSA: flat_load_ushort ; GCN-HSA: flat_load_ushort
; GCN-HSA: flat_store_dword ; GCN-HSA: flat_store_dword
; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}, 0, #1
define amdgpu_kernel void @constant_zextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
%a = load i16, i16 addrspace(2)* %in %a = load i16, i16 addrspace(4)* %in
%ext = zext i16 %a to i32 %ext = zext i16 %a to i32
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i16_to_i32: ; FUNC-LABEL: {{^}}constant_sextload_i16_to_i32:
; GCN-NOHSA: buffer_load_sshort ; GCN-NOHSA: buffer_load_sshort
; GCN-NOHSA: buffer_store_dword ; GCN-NOHSA: buffer_store_dword
; GCN-HSA: flat_load_sshort ; GCN-HSA: flat_load_sshort
; GCN-HSA: flat_store_dword ; GCN-HSA: flat_store_dword
; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 ; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1
; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal ; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
; EG: 16 ; EG: 16
define amdgpu_kernel void @constant_sextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_i16_to_i32(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
%a = load i16, i16 addrspace(2)* %in %a = load i16, i16 addrspace(4)* %in
%ext = sext i16 %a to i32 %ext = sext i16 %a to i32
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i32: ; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i32:
; GCN-NOHSA: buffer_load_ushort ; GCN-NOHSA: buffer_load_ushort
; GCN-HSA: flat_load_ushort ; GCN-HSA: flat_load_ushort
; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+\.X, T[0-9]+\.X}}, 0, #1
define amdgpu_kernel void @constant_zextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(4)* %in) #0 {
%load = load <1 x i16>, <1 x i16> addrspace(2)* %in %load = load <1 x i16>, <1 x i16> addrspace(4)* %in
%ext = zext <1 x i16> %load to <1 x i32> %ext = zext <1 x i16> %load to <1 x i32>
store <1 x i32> %ext, <1 x i32> addrspace(1)* %out store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i32: ; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i32:
; GCN-NOHSA: buffer_load_sshort ; GCN-NOHSA: buffer_load_sshort
; GCN-HSA: flat_load_sshort ; GCN-HSA: flat_load_sshort
; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 ; EG: VTX_READ_16 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1
; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal ; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
; EG: 16 ; EG: 16
define amdgpu_kernel void @constant_sextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v1i16_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i16> addrspace(4)* %in) #0 {
%load = load <1 x i16>, <1 x i16> addrspace(2)* %in %load = load <1 x i16>, <1 x i16> addrspace(4)* %in
%ext = sext <1 x i16> %load to <1 x i32> %ext = sext <1 x i16> %load to <1 x i32>
store <1 x i32> %ext, <1 x i32> addrspace(1)* %out store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i32: ; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i32:
; GCN: s_load_dword s ; GCN: s_load_dword s
; GCN-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0xffff{{$}} ; GCN-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0xffff{{$}}
; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 ; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
; v2i16 is naturally 4 byte aligned ; v2i16 is naturally 4 byte aligned
; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 ; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1
; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], literal ; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], literal
; EG: 16 ; EG: 16
; EG: 16 ; EG: 16
define amdgpu_kernel void @constant_zextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(4)* %in) #0 {
%load = load <2 x i16>, <2 x i16> addrspace(2)* %in %load = load <2 x i16>, <2 x i16> addrspace(4)* %in
%ext = zext <2 x i16> %load to <2 x i32> %ext = zext <2 x i16> %load to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i32: ; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i32:
; GCN: s_load_dword s ; GCN: s_load_dword s
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; GCN-DAG: s_sext_i32_i16 ; GCN-DAG: s_sext_i32_i16
; v2i16 is naturally 4 byte aligned ; v2i16 is naturally 4 byte aligned
; EG: MEM_RAT_CACHELESS STORE_RAW [[ST:T[0-9]]].XY, {{T[0-9].[XYZW]}}, ; EG: MEM_RAT_CACHELESS STORE_RAW [[ST:T[0-9]]].XY, {{T[0-9].[XYZW]}},
; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1 ; EG: VTX_READ_32 [[DST:T[0-9]\.[XYZW]]], [[DST]], 0, #1
; EG-DAG: BFE_INT {{[* ]*}}[[ST]].X, [[DST]], 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST]].X, [[DST]], 0.0, literal
; TODO: We should use ASHR instead of LSHR + BFE ; TODO: We should use ASHR instead of LSHR + BFE
; EG-DAG: BFE_INT {{[* ]*}}[[ST]].Y, {{PV\.[XYZW]}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST]].Y, {{PV\.[XYZW]}}, 0.0, literal
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
define amdgpu_kernel void @constant_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v2i16_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i16> addrspace(4)* %in) #0 {
%load = load <2 x i16>, <2 x i16> addrspace(2)* %in %load = load <2 x i16>, <2 x i16> addrspace(4)* %in
%ext = sext <2 x i16> %load to <2 x i32> %ext = sext <2 x i16> %load to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v3i16_to_v3i32: ; FUNC-LABEL: {{^}}constant_zextload_v3i16_to_v3i32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; v3i16 is naturally 8 byte aligned ; v3i16 is naturally 8 byte aligned
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9].[XYZW]}}, ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9].[XYZW]}},
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9].[XYZW]}}, ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9].[XYZW]}},
; EG: CF_END ; EG: CF_END
; EG-DAG: VTX_READ_32 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 0, #1 ; EG-DAG: VTX_READ_32 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 0, #1
; EG-DAG: VTX_READ_16 [[DST_HI:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 4, #1 ; EG-DAG: VTX_READ_16 [[DST_HI:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 4, #1
; TODO: This should use DST, but for some there are redundant MOVs ; TODO: This should use DST, but for some there are redundant MOVs
; EG-DAG: LSHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal ; EG-DAG: LSHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: AND_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, literal ; EG-DAG: AND_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, literal
; EG-DAG: AND_INT {{[* ]*}}[[ST_HI]].X, {{T[0-9]\.[XYZW]}}, literal ; EG-DAG: AND_INT {{[* ]*}}[[ST_HI]].X, {{T[0-9]\.[XYZW]}}, literal
; EG-DAG: 65535 ; EG-DAG: 65535
; EG-DAG: 65535 ; EG-DAG: 65535
define amdgpu_kernel void @constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { define amdgpu_kernel void @constant_zextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
entry: entry:
%ld = load <3 x i16>, <3 x i16> addrspace(2)* %in %ld = load <3 x i16>, <3 x i16> addrspace(4)* %in
%ext = zext <3 x i16> %ld to <3 x i32> %ext = zext <3 x i16> %ld to <3 x i32>
store <3 x i32> %ext, <3 x i32> addrspace(1)* %out store <3 x i32> %ext, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v3i16_to_v3i32: ; FUNC-LABEL: {{^}}constant_sextload_v3i16_to_v3i32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9].[XYZW]}}, ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_LO:T[0-9]]].XY, {{T[0-9].[XYZW]}},
; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9].[XYZW]}}, ; EG-DAG: MEM_RAT_CACHELESS STORE_RAW [[ST_HI:T[0-9]]].X, {{T[0-9].[XYZW]}},
; v3i16 is naturally 8 byte aligned ; v3i16 is naturally 8 byte aligned
; EG-DAG: VTX_READ_32 [[DST_HI:T[0-9]\.[XYZW]]], [[PTR:T[0-9]\.[XYZW]]], 0, #1 ; EG-DAG: VTX_READ_32 [[DST_HI:T[0-9]\.[XYZW]]], [[PTR:T[0-9]\.[XYZW]]], 0, #1
; EG-DAG: VTX_READ_16 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 4, #1 ; EG-DAG: VTX_READ_16 [[DST_LO:T[0-9]\.[XYZW]]], {{T[0-9]\.[XYZW]}}, 4, #1
; EG-DAG: ASHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal ; EG-DAG: ASHR {{[* ]*}}[[ST_LO]].Y, {{T[0-9]\.[XYZW]}}, literal
; EG-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST_LO]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}[[ST_HI]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST_HI]].X, {{T[0-9]\.[XYZW]}}, 0.0, literal
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
define amdgpu_kernel void @constant_sextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(2)* %in) { define amdgpu_kernel void @constant_sextload_v3i16_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i16> addrspace(4)* %in) {
entry: entry:
%ld = load <3 x i16>, <3 x i16> addrspace(2)* %in %ld = load <3 x i16>, <3 x i16> addrspace(4)* %in
%ext = sext <3 x i16> %ld to <3 x i32> %ext = sext <3 x i16> %ld to <3 x i32>
store <3 x i32> %ext, <3 x i32> addrspace(1)* %out store <3 x i32> %ext, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i16_to_v4i32: ; FUNC-LABEL: {{^}}constant_zextload_v4i16_to_v4i32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN-DAG: s_and_b32 ; GCN-DAG: s_and_b32
; GCN-DAG: s_lshr_b32 ; GCN-DAG: s_lshr_b32
; v4i16 is naturally 8 byte aligned ; v4i16 is naturally 8 byte aligned
; EG: MEM_RAT_CACHELESS STORE_RAW [[ST:T[0-9]]].XYZW, {{T[0-9].[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[ST:T[0-9]]].XYZW, {{T[0-9].[XYZW]}}
; EG: VTX_READ_64 [[LD:T[0-9]]].XY, {{T[0-9].[XYZW]}}, 0, #1 ; EG: VTX_READ_64 [[LD:T[0-9]]].XY, {{T[0-9].[XYZW]}}, 0, #1
; TODO: This should use LD, but for some there are redundant MOVs ; TODO: This should use LD, but for some there are redundant MOVs
; EG-DAG: BFE_UINT {{[* ]*}}[[ST]].Y, {{.*\.[XYZW]}}, literal ; EG-DAG: BFE_UINT {{[* ]*}}[[ST]].Y, {{.*\.[XYZW]}}, literal
; EG-DAG: BFE_UINT {{[* ]*}}[[ST]].W, {{.*\.[XYZW]}}, literal ; EG-DAG: BFE_UINT {{[* ]*}}[[ST]].W, {{.*\.[XYZW]}}, literal
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: AND_INT {{[* ]*}}[[ST]].X, {{T[0-9]\.[XYZW]}}, literal ; EG-DAG: AND_INT {{[* ]*}}[[ST]].X, {{T[0-9]\.[XYZW]}}, literal
; EG-DAG: AND_INT {{[* ]*}}[[ST]].Z, {{T[0-9]\.[XYZW]}}, literal ; EG-DAG: AND_INT {{[* ]*}}[[ST]].Z, {{T[0-9]\.[XYZW]}}, literal
; EG-DAG: 65535 ; EG-DAG: 65535
; EG-DAG: 65535 ; EG-DAG: 65535
define amdgpu_kernel void @constant_zextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(4)* %in) #0 {
%load = load <4 x i16>, <4 x i16> addrspace(2)* %in %load = load <4 x i16>, <4 x i16> addrspace(4)* %in
%ext = zext <4 x i16> %load to <4 x i32> %ext = zext <4 x i16> %load to <4 x i32>
store <4 x i32> %ext, <4 x i32> addrspace(1)* %out store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i32: ; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; GCN-DAG: s_sext_i32_i16 ; GCN-DAG: s_sext_i32_i16
; v4i16 is naturally 8 byte aligned ; v4i16 is naturally 8 byte aligned
; EG: MEM_RAT_CACHELESS STORE_RAW [[ST:T[0-9]]].XYZW, {{T[0-9]\.[XYZW]}}, ; EG: MEM_RAT_CACHELESS STORE_RAW [[ST:T[0-9]]].XYZW, {{T[0-9]\.[XYZW]}},
; EG: VTX_READ_64 [[DST:T[0-9]]].XY, {{T[0-9].[XYZW]}}, 0, #1 ; EG: VTX_READ_64 [[DST:T[0-9]]].XY, {{T[0-9].[XYZW]}}, 0, #1
; TODO: This should use LD, but for some there are redundant MOVs ; TODO: This should use LD, but for some there are redundant MOVs
; EG-DAG: BFE_INT {{[* ]*}}[[ST]].X, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST]].X, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}[[ST]].Z, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST]].Z, {{.*}}, 0.0, literal
; TODO: We should use ASHR instead of LSHR + BFE ; TODO: We should use ASHR instead of LSHR + BFE
; EG-DAG: BFE_INT {{[* ]*}}[[ST]].Y, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST]].Y, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}[[ST]].W, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}[[ST]].W, {{.*}}, 0.0, literal
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
define amdgpu_kernel void @constant_sextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v4i16_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i16> addrspace(4)* %in) #0 {
%load = load <4 x i16>, <4 x i16> addrspace(2)* %in %load = load <4 x i16>, <4 x i16> addrspace(4)* %in
%ext = sext <4 x i16> %load to <4 x i32> %ext = sext <4 x i16> %load to <4 x i32>
store <4 x i32> %ext, <4 x i32> addrspace(1)* %out store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i32: ; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i32:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; GCN-DAG: s_and_b32 ; GCN-DAG: s_and_b32
Show All 16 Lines
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 65535 ; EG-DAG: 65535
; EG-DAG: 65535 ; EG-DAG: 65535
; EG-DAG: 65535 ; EG-DAG: 65535
; EG-DAG: 65535 ; EG-DAG: 65535
define amdgpu_kernel void @constant_zextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(4)* %in) #0 {
%load = load <8 x i16>, <8 x i16> addrspace(2)* %in %load = load <8 x i16>, <8 x i16> addrspace(4)* %in
%ext = zext <8 x i16> %load to <8 x i32> %ext = zext <8 x i16> %load to <8 x i32>
store <8 x i32> %ext, <8 x i32> addrspace(1)* %out store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i32: ; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i32:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
Show All 16 Lines
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
; EG-DAG: 16 ; EG-DAG: 16
define amdgpu_kernel void @constant_sextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v8i16_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i16> addrspace(4)* %in) #0 {
%load = load <8 x i16>, <8 x i16> addrspace(2)* %in %load = load <8 x i16>, <8 x i16> addrspace(4)* %in
%ext = sext <8 x i16> %load to <8 x i32> %ext = sext <8 x i16> %load to <8 x i32>
store <8 x i32> %ext, <8 x i32> addrspace(1)* %out store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i32: ; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i32:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; GCN-DAG: s_and_b32 ; GCN-DAG: s_and_b32
; GCN-DAG: s_lshr_b32 ; GCN-DAG: s_lshr_b32
; v16i16 is naturally 32 byte aligned ; v16i16 is naturally 32 byte aligned
; EG-DAG: VTX_READ_128 [[DST_HI:T[0-9]+\.XYZW]], {{T[0-9]+.[XYZW]}}, 0, #1 ; EG-DAG: VTX_READ_128 [[DST_HI:T[0-9]+\.XYZW]], {{T[0-9]+.[XYZW]}}, 0, #1
; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], {{T[0-9]+.[XYZW]}}, 16, #1 ; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], {{T[0-9]+.[XYZW]}}, 16, #1
define amdgpu_kernel void @constant_zextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(4)* %in) #0 {
%load = load <16 x i16>, <16 x i16> addrspace(2)* %in %load = load <16 x i16>, <16 x i16> addrspace(4)* %in
%ext = zext <16 x i16> %load to <16 x i32> %ext = zext <16 x i16> %load to <16 x i32>
store <16 x i32> %ext, <16 x i32> addrspace(1)* %out store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i32: ; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i32:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; GCN-DAG: s_sext_i32_i16 ; GCN-DAG: s_sext_i32_i16
; v16i16 is naturally 32 byte aligned ; v16i16 is naturally 32 byte aligned
; EG-DAG: VTX_READ_128 [[DST_HI:T[0-9]+\.XYZW]], {{T[0-9]+\.[XYZW]}}, 0, #1 ; EG-DAG: VTX_READ_128 [[DST_HI:T[0-9]+\.XYZW]], {{T[0-9]+\.[XYZW]}}, 0, #1
; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], {{T[0-9]+\.[XYZW]}}, 16, #1 ; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], {{T[0-9]+\.[XYZW]}}, 16, #1
define amdgpu_kernel void @constant_sextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v16i16_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i16> addrspace(4)* %in) #0 {
%load = load <16 x i16>, <16 x i16> addrspace(2)* %in %load = load <16 x i16>, <16 x i16> addrspace(4)* %in
%ext = sext <16 x i16> %load to <16 x i32> %ext = sext <16 x i16> %load to <16 x i32>
store <16 x i32> %ext, <16 x i32> addrspace(1)* %out store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i32: ; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i32:
; GCN-DAG: s_load_dwordx16 ; GCN-DAG: s_load_dwordx16
; GCN-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}} ; GCN-DAG: s_mov_b32 [[K:s[0-9]+]], 0xffff{{$}}
; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 ; GCN-DAG: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
; GCN-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[K]] ; GCN-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, [[K]]
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1
define amdgpu_kernel void @constant_zextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(4)* %in) #0 {
%load = load <32 x i16>, <32 x i16> addrspace(2)* %in %load = load <32 x i16>, <32 x i16> addrspace(4)* %in
%ext = zext <32 x i16> %load to <32 x i32> %ext = zext <32 x i16> %load to <32 x i32>
store <32 x i32> %ext, <32 x i32> addrspace(1)* %out store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i32: ; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i32:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; GCN-DAG: s_sext_i32_i16 ; GCN-DAG: s_sext_i32_i16
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1
define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v32i16_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i16> addrspace(4)* %in) #0 {
%load = load <32 x i16>, <32 x i16> addrspace(2)* %in %load = load <32 x i16>, <32 x i16> addrspace(4)* %in
%ext = sext <32 x i16> %load to <32 x i32> %ext = sext <32 x i16> %load to <32 x i32>
store <32 x i32> %ext, <32 x i32> addrspace(1)* %out store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i32: ; FUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i32:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 64, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 64, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 80, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 80, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 96, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 96, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 112, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 112, #1
define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(4)* %in) #0 {
%load = load <64 x i16>, <64 x i16> addrspace(2)* %in %load = load <64 x i16>, <64 x i16> addrspace(4)* %in
%ext = zext <64 x i16> %load to <64 x i32> %ext = zext <64 x i16> %load to <64 x i32>
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i32: ; FUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i32:
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 0, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 16, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 32, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 48, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 64, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 64, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 80, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 80, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 96, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 96, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 112, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, {{T[0-9]+\.[XYZW]}}, 112, #1
define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v64i16_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i16> addrspace(4)* %in) #0 {
%load = load <64 x i16>, <64 x i16> addrspace(2)* %in %load = load <64 x i16>, <64 x i16> addrspace(4)* %in
%ext = sext <64 x i16> %load to <64 x i32> %ext = sext <64 x i16> %load to <64 x i32>
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i16_to_i64: ; FUNC-LABEL: {{^}}constant_zextload_i16_to_i64:
; GCN-NOHSA-DAG: buffer_load_ushort v[[LO:[0-9]+]], ; GCN-NOHSA-DAG: buffer_load_ushort v[[LO:[0-9]+]],
; GCN-HSA-DAG: flat_load_ushort v[[LO:[0-9]+]], ; GCN-HSA-DAG: flat_load_ushort v[[LO:[0-9]+]],
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: MOV {{.*}}, 0.0 ; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @constant_zextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
%a = load i16, i16 addrspace(2)* %in %a = load i16, i16 addrspace(4)* %in
%ext = zext i16 %a to i64 %ext = zext i16 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i16_to_i64: ; FUNC-LABEL: {{^}}constant_sextload_i16_to_i64:
; FIXME: Need to optimize this sequence to avoid extra bfe: ; FIXME: Need to optimize this sequence to avoid extra bfe:
; t28: i32,ch = load<LD2[%in(addrspace=1)], anyext from i16> t12, t27, undef:i64 ; t28: i32,ch = load<LD2[%in(addrspace=1)], anyext from i16> t12, t27, undef:i64
; t31: i64 = any_extend t28 ; t31: i64 = any_extend t28
; t33: i64 = sign_extend_inreg t31, ValueType:ch:i16 ; t33: i64 = sign_extend_inreg t31, ValueType:ch:i16
; GCN-NOHSA-SI-DAG: buffer_load_sshort v[[LO:[0-9]+]], ; GCN-NOHSA-SI-DAG: buffer_load_sshort v[[LO:[0-9]+]],
; GCN-HSA-DAG: flat_load_sshort v[[LO:[0-9]+]], ; GCN-HSA-DAG: flat_load_sshort v[[LO:[0-9]+]],
; GCN-NOHSA-VI-DAG: buffer_load_ushort v[[ULO:[0-9]+]], ; GCN-NOHSA-VI-DAG: buffer_load_ushort v[[ULO:[0-9]+]],
; GCN-NOHSA-VI-DAG: v_bfe_i32 v[[LO:[0-9]+]], v[[ULO]], 0, 16 ; GCN-NOHSA-VI-DAG: v_bfe_i32 v[[LO:[0-9]+]], v[[ULO]], 0, 16
; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN-DAG: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal ; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: These could be expanded earlier using ASHR 15 ; TODO: These could be expanded earlier using ASHR 15
; EG: 31 ; EG: 31
define amdgpu_kernel void @constant_sextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_i16_to_i64(i64 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
%a = load i16, i16 addrspace(2)* %in %a = load i16, i16 addrspace(4)* %in
%ext = sext i16 %a to i64 %ext = sext i16 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i64: ; FUNC-LABEL: {{^}}constant_zextload_v1i16_to_v1i64:
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: MOV {{.*}}, 0.0 ; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @constant_zextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(4)* %in) #0 {
%load = load <1 x i16>, <1 x i16> addrspace(2)* %in %load = load <1 x i16>, <1 x i16> addrspace(4)* %in
%ext = zext <1 x i16> %load to <1 x i64> %ext = zext <1 x i16> %load to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i64: ; FUNC-LABEL: {{^}}constant_sextload_v1i16_to_v1i64:
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal ; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: These could be expanded earlier using ASHR 15 ; TODO: These could be expanded earlier using ASHR 15
; EG: 31 ; EG: 31
define amdgpu_kernel void @constant_sextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v1i16_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i16> addrspace(4)* %in) #0 {
%load = load <1 x i16>, <1 x i16> addrspace(2)* %in %load = load <1 x i16>, <1 x i16> addrspace(4)* %in
%ext = sext <1 x i16> %load to <1 x i64> %ext = sext <1 x i16> %load to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i64: ; FUNC-LABEL: {{^}}constant_zextload_v2i16_to_v2i64:
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(4)* %in) #0 {
%load = load <2 x i16>, <2 x i16> addrspace(2)* %in %load = load <2 x i16>, <2 x i16> addrspace(4)* %in
%ext = zext <2 x i16> %load to <2 x i64> %ext = zext <2 x i16> %load to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i64: ; FUNC-LABEL: {{^}}constant_sextload_v2i16_to_v2i64:
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v2i16_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i16> addrspace(4)* %in) #0 {
%load = load <2 x i16>, <2 x i16> addrspace(2)* %in %load = load <2 x i16>, <2 x i16> addrspace(4)* %in
%ext = sext <2 x i16> %load to <2 x i64> %ext = sext <2 x i16> %load to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i16_to_v4i64: ; FUNC-LABEL: {{^}}constant_zextload_v4i16_to_v4i64:
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(4)* %in) #0 {
%load = load <4 x i16>, <4 x i16> addrspace(2)* %in %load = load <4 x i16>, <4 x i16> addrspace(4)* %in
%ext = zext <4 x i16> %load to <4 x i64> %ext = zext <4 x i16> %load to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i64: ; FUNC-LABEL: {{^}}constant_sextload_v4i16_to_v4i64:
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v4i16_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i16> addrspace(4)* %in) #0 {
%load = load <4 x i16>, <4 x i16> addrspace(2)* %in %load = load <4 x i16>, <4 x i16> addrspace(4)* %in
%ext = sext <4 x i16> %load to <4 x i64> %ext = sext <4 x i16> %load to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i64: ; FUNC-LABEL: {{^}}constant_zextload_v8i16_to_v8i64:
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(4)* %in) #0 {
%load = load <8 x i16>, <8 x i16> addrspace(2)* %in %load = load <8 x i16>, <8 x i16> addrspace(4)* %in
%ext = zext <8 x i16> %load to <8 x i64> %ext = zext <8 x i16> %load to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i64: ; FUNC-LABEL: {{^}}constant_sextload_v8i16_to_v8i64:
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v8i16_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i16> addrspace(4)* %in) #0 {
%load = load <8 x i16>, <8 x i16> addrspace(2)* %in %load = load <8 x i16>, <8 x i16> addrspace(4)* %in
%ext = sext <8 x i16> %load to <8 x i64> %ext = sext <8 x i16> %load to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i64: ; FUNC-LABEL: {{^}}constant_zextload_v16i16_to_v16i64:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_zextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(4)* %in) #0 {
%load = load <16 x i16>, <16 x i16> addrspace(2)* %in %load = load <16 x i16>, <16 x i16> addrspace(4)* %in
%ext = zext <16 x i16> %load to <16 x i64> %ext = zext <16 x i16> %load to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i64: ; FUNC-LABEL: {{^}}constant_sextload_v16i16_to_v16i64:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v16i16_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i16> addrspace(4)* %in) #0 {
%load = load <16 x i16>, <16 x i16> addrspace(2)* %in %load = load <16 x i16>, <16 x i16> addrspace(4)* %in
%ext = sext <16 x i16> %load to <16 x i64> %ext = sext <16 x i16> %load to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i64: ; FUNC-LABEL: {{^}}constant_zextload_v32i16_to_v32i64:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 32, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 32, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 48, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 48, #1
define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(4)* %in) #0 {
%load = load <32 x i16>, <32 x i16> addrspace(2)* %in %load = load <32 x i16>, <32 x i16> addrspace(4)* %in
%ext = zext <32 x i16> %load to <32 x i64> %ext = zext <32 x i16> %load to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i64: ; FUNC-LABEL: {{^}}constant_sextload_v32i16_to_v32i64:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 32, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 32, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 48, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 48, #1
define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v32i16_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i16> addrspace(4)* %in) #0 {
%load = load <32 x i16>, <32 x i16> addrspace(2)* %in %load = load <32 x i16>, <32 x i16> addrspace(4)* %in
%ext = sext <32 x i16> %load to <32 x i64> %ext = sext <32 x i16> %load to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; These trigger undefined register machine verifier errors ; These trigger undefined register machine verifier errors
; ; XFUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i64: ; ; XFUNC-LABEL: {{^}}constant_zextload_v64i16_to_v64i64:
; define amdgpu_kernel void @constant_zextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { ; define amdgpu_kernel void @constant_zextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(4)* %in) #0 {
; %load = load <64 x i16>, <64 x i16> addrspace(2)* %in ; %load = load <64 x i16>, <64 x i16> addrspace(4)* %in
; %ext = zext <64 x i16> %load to <64 x i64> ; %ext = zext <64 x i16> %load to <64 x i64>
; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out ; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
; ret void ; ret void
; } ; }
; ; XFUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i64: ; ; XFUNC-LABEL: {{^}}constant_sextload_v64i16_to_v64i64:
; define amdgpu_kernel void @constant_sextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(2)* %in) #0 { ; define amdgpu_kernel void @constant_sextload_v64i16_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i16> addrspace(4)* %in) #0 {
; %load = load <64 x i16>, <64 x i16> addrspace(2)* %in ; %load = load <64 x i16>, <64 x i16> addrspace(4)* %in
; %ext = sext <64 x i16> %load to <64 x i64> ; %ext = sext <64 x i16> %load to <64 x i64>
; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out ; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
; ret void ; ret void
; } ; }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-constant-i32.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i32: ; FUNC-LABEL: {{^}}constant_load_i32:
; GCN: s_load_dword s{{[0-9]+}} ; GCN: s_load_dword s{{[0-9]+}}
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0
define amdgpu_kernel void @constant_load_i32(i32 addrspace(1)* %out, i32 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i32(i32 addrspace(1)* %out, i32 addrspace(4)* %in) #0 {
entry: entry:
%ld = load i32, i32 addrspace(2)* %in %ld = load i32, i32 addrspace(4)* %in
store i32 %ld, i32 addrspace(1)* %out store i32 %ld, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v2i32: ; FUNC-LABEL: {{^}}constant_load_v2i32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; EG: VTX_READ_64 ; EG: VTX_READ_64
define amdgpu_kernel void @constant_load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <2 x i32>, <2 x i32> addrspace(2)* %in %ld = load <2 x i32>, <2 x i32> addrspace(4)* %in
store <2 x i32> %ld, <2 x i32> addrspace(1)* %out store <2 x i32> %ld, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v3i32: ; FUNC-LABEL: {{^}}constant_load_v3i32:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <3 x i32>, <3 x i32> addrspace(2)* %in %ld = load <3 x i32>, <3 x i32> addrspace(4)* %in
store <3 x i32> %ld, <3 x i32> addrspace(1)* %out store <3 x i32> %ld, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v4i32: ; FUNC-LABEL: {{^}}constant_load_v4i32:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <4 x i32>, <4 x i32> addrspace(2)* %in %ld = load <4 x i32>, <4 x i32> addrspace(4)* %in
store <4 x i32> %ld, <4 x i32> addrspace(1)* %out store <4 x i32> %ld, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v8i32: ; FUNC-LABEL: {{^}}constant_load_v8i32:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v8i32(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <8 x i32>, <8 x i32> addrspace(2)* %in %ld = load <8 x i32>, <8 x i32> addrspace(4)* %in
store <8 x i32> %ld, <8 x i32> addrspace(1)* %out store <8 x i32> %ld, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v16i32: ; FUNC-LABEL: {{^}}constant_load_v16i32:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v16i32(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <16 x i32>, <16 x i32> addrspace(2)* %in %ld = load <16 x i32>, <16 x i32> addrspace(4)* %in
store <16 x i32> %ld, <16 x i32> addrspace(1)* %out store <16 x i32> %ld, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i32_to_i64: ; FUNC-LABEL: {{^}}constant_zextload_i32_to_i64:
; GCN-DAG: s_load_dword s[[SLO:[0-9]+]], ; GCN-DAG: s_load_dword s[[SLO:[0-9]+]],
; GCN-DAG: v_mov_b32_e32 v[[SHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[SHI:[0-9]+]], 0{{$}}
; GCN: store_dwordx2 ; GCN: store_dwordx2
; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
; EG: CF_END ; EG: CF_END
; EG: VTX_READ_32 ; EG: VTX_READ_32
define amdgpu_kernel void @constant_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(4)* %in) #0 {
%ld = load i32, i32 addrspace(2)* %in %ld = load i32, i32 addrspace(4)* %in
%ext = zext i32 %ld to i64 %ext = zext i32 %ld to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i32_to_i64: ; FUNC-LABEL: {{^}}constant_sextload_i32_to_i64:
; GCN: s_load_dword s[[SLO:[0-9]+]] ; GCN: s_load_dword s[[SLO:[0-9]+]]
; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[SLO]], 31
; GCN: store_dwordx2 ; GCN: store_dwordx2
; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY
; EG: CF_END ; EG: CF_END
; EG: VTX_READ_32 ; EG: VTX_READ_32
; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal. ; EG: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.
; EG: 31 ; EG: 31
define amdgpu_kernel void @constant_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_i32_to_i64(i64 addrspace(1)* %out, i32 addrspace(4)* %in) #0 {
%ld = load i32, i32 addrspace(2)* %in %ld = load i32, i32 addrspace(4)* %in
%ext = sext i32 %ld to i64 %ext = sext i32 %ld to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i32_to_v1i64: ; FUNC-LABEL: {{^}}constant_zextload_v1i32_to_v1i64:
; GCN: s_load_dword ; GCN: s_load_dword
; GCN: store_dwordx2 ; GCN: store_dwordx2
define amdgpu_kernel void @constant_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(4)* %in) #0 {
%ld = load <1 x i32>, <1 x i32> addrspace(2)* %in %ld = load <1 x i32>, <1 x i32> addrspace(4)* %in
%ext = zext <1 x i32> %ld to <1 x i64> %ext = zext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i32_to_v1i64: ; FUNC-LABEL: {{^}}constant_sextload_v1i32_to_v1i64:
; GCN: s_load_dword s[[LO:[0-9]+]] ; GCN: s_load_dword s[[LO:[0-9]+]]
; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31 ; GCN: s_ashr_i32 s[[HI:[0-9]+]], s[[LO]], 31
; GCN: store_dwordx2 ; GCN: store_dwordx2
define amdgpu_kernel void @constant_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v1i32_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i32> addrspace(4)* %in) #0 {
%ld = load <1 x i32>, <1 x i32> addrspace(2)* %in %ld = load <1 x i32>, <1 x i32> addrspace(4)* %in
%ext = sext <1 x i32> %ld to <1 x i64> %ext = sext <1 x i32> %ld to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i32_to_v2i64: ; FUNC-LABEL: {{^}}constant_zextload_v2i32_to_v2i64:
; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; GCN: store_dwordx4 ; GCN: store_dwordx4
define amdgpu_kernel void @constant_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(4)* %in) #0 {
%ld = load <2 x i32>, <2 x i32> addrspace(2)* %in %ld = load <2 x i32>, <2 x i32> addrspace(4)* %in
%ext = zext <2 x i32> %ld to <2 x i64> %ext = zext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i32_to_v2i64: ; FUNC-LABEL: {{^}}constant_sextload_v2i32_to_v2i64:
; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; GCN: store_dwordx4 ; GCN: store_dwordx4
define amdgpu_kernel void @constant_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v2i32_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i32> addrspace(4)* %in) #0 {
%ld = load <2 x i32>, <2 x i32> addrspace(2)* %in %ld = load <2 x i32>, <2 x i32> addrspace(4)* %in
%ext = sext <2 x i32> %ld to <2 x i64> %ext = sext <2 x i32> %ld to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i32_to_v4i64: ; FUNC-LABEL: {{^}}constant_zextload_v4i32_to_v4i64:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
define amdgpu_kernel void @constant_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(4)* %in) #0 {
%ld = load <4 x i32>, <4 x i32> addrspace(2)* %in %ld = load <4 x i32>, <4 x i32> addrspace(4)* %in
%ext = zext <4 x i32> %ld to <4 x i64> %ext = zext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i32_to_v4i64: ; FUNC-LABEL: {{^}}constant_sextload_v4i32_to_v4i64:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: s_ashr_i32 ; GCN: s_ashr_i32
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
define amdgpu_kernel void @constant_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v4i32_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i32> addrspace(4)* %in) #0 {
%ld = load <4 x i32>, <4 x i32> addrspace(2)* %in %ld = load <4 x i32>, <4 x i32> addrspace(4)* %in
%ext = sext <4 x i32> %ld to <4 x i64> %ext = sext <4 x i32> %ld to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i32_to_v8i64: ; FUNC-LABEL: {{^}}constant_zextload_v8i32_to_v8i64:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-SA-DAG: flat_store_dwordx4 ; GCN-SA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
define amdgpu_kernel void @constant_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(4)* %in) #0 {
%ld = load <8 x i32>, <8 x i32> addrspace(2)* %in %ld = load <8 x i32>, <8 x i32> addrspace(4)* %in
%ext = zext <8 x i32> %ld to <8 x i64> %ext = zext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i32_to_v8i64: ; FUNC-LABEL: {{^}}constant_sextload_v8i32_to_v8i64:
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
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; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-NOHSA-DAG: buffer_store_dwordx4 ; GCN-NOHSA-DAG: buffer_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v8i32_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i32> addrspace(4)* %in) #0 {
%ld = load <8 x i32>, <8 x i32> addrspace(2)* %in %ld = load <8 x i32>, <8 x i32> addrspace(4)* %in
%ext = sext <8 x i32> %ld to <8 x i64> %ext = sext <8 x i32> %ld to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i32_to_v16i64: ; FUNC-LABEL: {{^}}constant_sextload_v16i32_to_v16i64:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
; GCN: store_dwordx4 ; GCN: store_dwordx4
define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(4)* %in) #0 {
%ld = load <16 x i32>, <16 x i32> addrspace(2)* %in %ld = load <16 x i32>, <16 x i32> addrspace(4)* %in
%ext = sext <16 x i32> %ld to <16 x i64> %ext = sext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i32_to_v16i64 ; FUNC-LABEL: {{^}}constant_zextload_v16i32_to_v16i64
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
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; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
; GCN-HSA: flat_store_dwordx4 ; GCN-HSA: flat_store_dwordx4
define amdgpu_kernel void @constant_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v16i32_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i32> addrspace(4)* %in) #0 {
%ld = load <16 x i32>, <16 x i32> addrspace(2)* %in %ld = load <16 x i32>, <16 x i32> addrspace(4)* %in
%ext = zext <16 x i32> %ld to <16 x i64> %ext = zext <16 x i32> %ld to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i32_to_v32i64: ; FUNC-LABEL: {{^}}constant_sextload_v32i32_to_v32i64:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
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; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(4)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(2)* %in %ld = load <32 x i32>, <32 x i32> addrspace(4)* %in
%ext = sext <32 x i32> %ld to <32 x i64> %ext = sext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i32_to_v32i64: ; FUNC-LABEL: {{^}}constant_zextload_v32i32_to_v32i64:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
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; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
; GCN-HSA-DAG: flat_store_dwordx4 ; GCN-HSA-DAG: flat_store_dwordx4
define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v32i32_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i32> addrspace(4)* %in) #0 {
%ld = load <32 x i32>, <32 x i32> addrspace(2)* %in %ld = load <32 x i32>, <32 x i32> addrspace(4)* %in
%ext = zext <32 x i32> %ld to <32 x i64> %ext = zext <32 x i32> %ld to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-constant-i64.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=VI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=VI -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i64: ; FUNC-LABEL: {{^}}constant_load_i64:
; GCN: s_load_dwordx2 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN: s_load_dwordx2 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; EG: VTX_READ_64 ; EG: VTX_READ_64
define amdgpu_kernel void @constant_load_i64(i64 addrspace(1)* %out, i64 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i64(i64 addrspace(1)* %out, i64 addrspace(4)* %in) #0 {
%ld = load i64, i64 addrspace(2)* %in %ld = load i64, i64 addrspace(4)* %in
store i64 %ld, i64 addrspace(1)* %out store i64 %ld, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v2i64: ; FUNC-LABEL: {{^}}constant_load_v2i64:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <2 x i64>, <2 x i64> addrspace(2)* %in %ld = load <2 x i64>, <2 x i64> addrspace(4)* %in
store <2 x i64> %ld, <2 x i64> addrspace(1)* %out store <2 x i64> %ld, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v3i64: ; FUNC-LABEL: {{^}}constant_load_v3i64:
; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; GCN: s_load_dwordx8 {{s\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; EG-DAG: VTX_READ_128 ; EG-DAG: VTX_READ_128
; EG-DAG: VTX_READ_128 ; EG-DAG: VTX_READ_128
define amdgpu_kernel void @constant_load_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <3 x i64>, <3 x i64> addrspace(2)* %in %ld = load <3 x i64>, <3 x i64> addrspace(4)* %in
store <3 x i64> %ld, <3 x i64> addrspace(1)* %out store <3 x i64> %ld, <3 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v4i64 ; FUNC-LABEL: {{^}}constant_load_v4i64
; GCN: s_load_dwordx8 ; GCN: s_load_dwordx8
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <4 x i64>, <4 x i64> addrspace(2)* %in %ld = load <4 x i64>, <4 x i64> addrspace(4)* %in
store <4 x i64> %ld, <4 x i64> addrspace(1)* %out store <4 x i64> %ld, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v8i64: ; FUNC-LABEL: {{^}}constant_load_v8i64:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v8i64(<8 x i64> addrspace(1)* %out, <8 x i64> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v8i64(<8 x i64> addrspace(1)* %out, <8 x i64> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <8 x i64>, <8 x i64> addrspace(2)* %in %ld = load <8 x i64>, <8 x i64> addrspace(4)* %in
store <8 x i64> %ld, <8 x i64> addrspace(1)* %out store <8 x i64> %ld, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v16i64: ; FUNC-LABEL: {{^}}constant_load_v16i64:
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; GCN: s_load_dwordx16 ; GCN: s_load_dwordx16
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
; EG: VTX_READ_128 ; EG: VTX_READ_128
define amdgpu_kernel void @constant_load_v16i64(<16 x i64> addrspace(1)* %out, <16 x i64> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v16i64(<16 x i64> addrspace(1)* %out, <16 x i64> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <16 x i64>, <16 x i64> addrspace(2)* %in %ld = load <16 x i64>, <16 x i64> addrspace(4)* %in
store <16 x i64> %ld, <16 x i64> addrspace(1)* %out store <16 x i64> %ld, <16 x i64> addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-constant-i8.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-HSA -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-NOHSA -check-prefix=FUNC %s
; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=redwood -verify-machineinstrs < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}constant_load_i8: ; FUNC-LABEL: {{^}}constant_load_i8:
; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}} ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}
; GCN-HSA: flat_load_ubyte ; GCN-HSA: flat_load_ubyte
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: NOT AND ; TODO: NOT AND
define amdgpu_kernel void @constant_load_i8(i8 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i8(i8 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
entry: entry:
%ld = load i8, i8 addrspace(2)* %in %ld = load i8, i8 addrspace(4)* %in
store i8 %ld, i8 addrspace(1)* %out store i8 %ld, i8 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v2i8: ; FUNC-LABEL: {{^}}constant_load_v2i8:
; GCN-NOHSA: buffer_load_ushort v ; GCN-NOHSA: buffer_load_ushort v
; GCN-HSA: flat_load_ushort v ; GCN-HSA: flat_load_ushort v
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <2 x i8>, <2 x i8> addrspace(2)* %in %ld = load <2 x i8>, <2 x i8> addrspace(4)* %in
store <2 x i8> %ld, <2 x i8> addrspace(1)* %out store <2 x i8> %ld, <2 x i8> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v3i8: ; FUNC-LABEL: {{^}}constant_load_v3i8:
; GCN: s_load_dword s ; GCN: s_load_dword s
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <3 x i8>, <3 x i8> addrspace(2)* %in %ld = load <3 x i8>, <3 x i8> addrspace(4)* %in
store <3 x i8> %ld, <3 x i8> addrspace(1)* %out store <3 x i8> %ld, <3 x i8> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v4i8: ; FUNC-LABEL: {{^}}constant_load_v4i8:
; GCN: s_load_dword s ; GCN: s_load_dword s
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v4i8(<4 x i8> addrspace(1)* %out, <4 x i8> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <4 x i8>, <4 x i8> addrspace(2)* %in %ld = load <4 x i8>, <4 x i8> addrspace(4)* %in
store <4 x i8> %ld, <4 x i8> addrspace(1)* %out store <4 x i8> %ld, <4 x i8> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v8i8: ; FUNC-LABEL: {{^}}constant_load_v8i8:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v8i8(<8 x i8> addrspace(1)* %out, <8 x i8> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <8 x i8>, <8 x i8> addrspace(2)* %in %ld = load <8 x i8>, <8 x i8> addrspace(4)* %in
store <8 x i8> %ld, <8 x i8> addrspace(1)* %out store <8 x i8> %ld, <8 x i8> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_load_v16i8: ; FUNC-LABEL: {{^}}constant_load_v16i8:
; GCN: s_load_dwordx4 ; GCN: s_load_dwordx4
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_load_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v16i8(<16 x i8> addrspace(1)* %out, <16 x i8> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <16 x i8>, <16 x i8> addrspace(2)* %in %ld = load <16 x i8>, <16 x i8> addrspace(4)* %in
store <16 x i8> %ld, <16 x i8> addrspace(1)* %out store <16 x i8> %ld, <16 x i8> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i8_to_i32: ; FUNC-LABEL: {{^}}constant_zextload_i8_to_i32:
; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}}, ; GCN-NOHSA: buffer_load_ubyte v{{[0-9]+}},
; GCN-HSA: flat_load_ubyte ; GCN-HSA: flat_load_ubyte
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%a = load i8, i8 addrspace(2)* %in %a = load i8, i8 addrspace(4)* %in
%ext = zext i8 %a to i32 %ext = zext i8 %a to i32
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i8_to_i32: ; FUNC-LABEL: {{^}}constant_sextload_i8_to_i32:
; GCN-NOHSA: buffer_load_sbyte ; GCN-NOHSA: buffer_load_sbyte
; GCN-HSA: flat_load_sbyte ; GCN-HSA: flat_load_sbyte
; EG: VTX_READ_8 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal ; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
; EG: 8 ; EG: 8
define amdgpu_kernel void @constant_sextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_i8_to_i32(i32 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%ld = load i8, i8 addrspace(2)* %in %ld = load i8, i8 addrspace(4)* %in
%ext = sext i8 %ld to i32 %ext = sext i8 %ld to i32
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i32: ; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i32:
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(4)* %in) #0 {
%load = load <1 x i8>, <1 x i8> addrspace(2)* %in %load = load <1 x i8>, <1 x i8> addrspace(4)* %in
%ext = zext <1 x i8> %load to <1 x i32> %ext = zext <1 x i8> %load to <1 x i32>
store <1 x i32> %ext, <1 x i32> addrspace(1)* %out store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i32: ; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i32:
; EG: VTX_READ_8 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal ; EG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, [[DST]], 0.0, literal
; EG: 8 ; EG: 8
define amdgpu_kernel void @constant_sextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v1i8_to_v1i32(<1 x i32> addrspace(1)* %out, <1 x i8> addrspace(4)* %in) #0 {
%load = load <1 x i8>, <1 x i8> addrspace(2)* %in %load = load <1 x i8>, <1 x i8> addrspace(4)* %in
%ext = sext <1 x i8> %load to <1 x i32> %ext = sext <1 x i8> %load to <1 x i32>
store <1 x i32> %ext, <1 x i32> addrspace(1)* %out store <1 x i32> %ext, <1 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i32: ; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i32:
; GCN-NOHSA: buffer_load_ushort ; GCN-NOHSA: buffer_load_ushort
; GCN-HSA: flat_load_ushort ; GCN-HSA: flat_load_ushort
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: This should use DST, but for some there are redundant MOVs ; TODO: This should use DST, but for some there are redundant MOVs
; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal ; EG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
; EG: 8 ; EG: 8
define amdgpu_kernel void @constant_zextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%load = load <2 x i8>, <2 x i8> addrspace(2)* %in %load = load <2 x i8>, <2 x i8> addrspace(4)* %in
%ext = zext <2 x i8> %load to <2 x i32> %ext = zext <2 x i8> %load to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i32: ; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i32:
; GCN-NOHSA: buffer_load_ushort ; GCN-NOHSA: buffer_load_ushort
; GCN-HSA: flat_load_ushort ; GCN-HSA: flat_load_ushort
; GCN: v_bfe_i32 ; GCN: v_bfe_i32
; GCN: v_bfe_i32 ; GCN: v_bfe_i32
; EG: VTX_READ_16 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs ; TODO: These should use DST, but for some there are redundant MOVs
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v2i8_to_v2i32(<2 x i32> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%load = load <2 x i8>, <2 x i8> addrspace(2)* %in %load = load <2 x i8>, <2 x i8> addrspace(4)* %in
%ext = sext <2 x i8> %load to <2 x i32> %ext = sext <2 x i8> %load to <2 x i32>
store <2 x i32> %ext, <2 x i32> addrspace(1)* %out store <2 x i32> %ext, <2 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v3i8_to_v3i32: ; FUNC-LABEL: {{^}}constant_zextload_v3i8_to_v3i32:
; GCN: s_load_dword s ; GCN: s_load_dword s
; GCN-DAG: s_bfe_u32 ; GCN-DAG: s_bfe_u32
; GCN-DAG: s_bfe_u32 ; GCN-DAG: s_bfe_u32
; GCN-DAG: s_and_b32 ; GCN-DAG: s_and_b32
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs ; TODO: These should use DST, but for some there are redundant MOVs
; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal ; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal ; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <3 x i8>, <3 x i8> addrspace(2)* %in %ld = load <3 x i8>, <3 x i8> addrspace(4)* %in
%ext = zext <3 x i8> %ld to <3 x i32> %ext = zext <3 x i8> %ld to <3 x i32>
store <3 x i32> %ext, <3 x i32> addrspace(1)* %out store <3 x i32> %ext, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v3i8_to_v3i32: ; FUNC-LABEL: {{^}}constant_sextload_v3i8_to_v3i32:
; GCN: s_load_dword s ; GCN: s_load_dword s
; GCN-DAG: s_bfe_i32 ; GCN-DAG: s_bfe_i32
; GCN-DAG: s_bfe_i32 ; GCN-DAG: s_bfe_i32
; GCN-DAG: s_bfe_i32 ; GCN-DAG: s_bfe_i32
; EG: VTX_READ_32 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs ; TODO: These should use DST, but for some there are redundant MOVs
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v3i8_to_v3i32(<3 x i32> addrspace(1)* %out, <3 x i8> addrspace(4)* %in) #0 {
entry: entry:
%ld = load <3 x i8>, <3 x i8> addrspace(2)* %in %ld = load <3 x i8>, <3 x i8> addrspace(4)* %in
%ext = sext <3 x i8> %ld to <3 x i32> %ext = sext <3 x i8> %ld to <3 x i32>
store <3 x i32> %ext, <3 x i32> addrspace(1)* %out store <3 x i32> %ext, <3 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i32: ; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i32:
; GCN: s_load_dword s ; GCN: s_load_dword s
; GCN-DAG: s_and_b32 ; GCN-DAG: s_and_b32
; GCN-DAG: s_lshr_b32 ; GCN-DAG: s_lshr_b32
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs ; TODO: These should use DST, but for some there are redundant MOVs
; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal ; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal ; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal ; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(4)* %in) #0 {
%load = load <4 x i8>, <4 x i8> addrspace(2)* %in %load = load <4 x i8>, <4 x i8> addrspace(4)* %in
%ext = zext <4 x i8> %load to <4 x i32> %ext = zext <4 x i8> %load to <4 x i32>
store <4 x i32> %ext, <4 x i32> addrspace(1)* %out store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i32: ; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i32:
; GCN: s_load_dword s ; GCN: s_load_dword s
; GCN-DAG: s_sext_i32_i8 ; GCN-DAG: s_sext_i32_i8
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
; EG: VTX_READ_32 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 [[DST:T[0-9]+\.X]], T{{[0-9]+}}.X, 0, #1
; TODO: These should use DST, but for some there are redundant MOVs ; TODO: These should use DST, but for some there are redundant MOVs
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v4i8_to_v4i32(<4 x i32> addrspace(1)* %out, <4 x i8> addrspace(4)* %in) #0 {
%load = load <4 x i8>, <4 x i8> addrspace(2)* %in %load = load <4 x i8>, <4 x i8> addrspace(4)* %in
%ext = sext <4 x i8> %load to <4 x i32> %ext = sext <4 x i8> %load to <4 x i32>
store <4 x i32> %ext, <4 x i32> addrspace(1)* %out store <4 x i32> %ext, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i32: ; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN-DAG: s_and_b32 ; GCN-DAG: s_and_b32
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; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal ; EG-DAG: BFE_UINT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, {{.*}}literal
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(4)* %in) #0 {
%load = load <8 x i8>, <8 x i8> addrspace(2)* %in %load = load <8 x i8>, <8 x i8> addrspace(4)* %in
%ext = zext <8 x i8> %load to <8 x i32> %ext = zext <8 x i8> %load to <8 x i32>
store <8 x i32> %ext, <8 x i32> addrspace(1)* %out store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i32: ; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i32:
; GCN: s_load_dwordx2 ; GCN: s_load_dwordx2
; GCN-DAG: s_ashr_i32 ; GCN-DAG: s_ashr_i32
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; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v8i8_to_v8i32(<8 x i32> addrspace(1)* %out, <8 x i8> addrspace(4)* %in) #0 {
%load = load <8 x i8>, <8 x i8> addrspace(2)* %in %load = load <8 x i8>, <8 x i8> addrspace(4)* %in
%ext = sext <8 x i8> %load to <8 x i32> %ext = sext <8 x i8> %load to <8 x i32>
store <8 x i32> %ext, <8 x i32> addrspace(1)* %out store <8 x i32> %ext, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i32: ; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i32:
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
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; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(4)* %in) #0 {
%load = load <16 x i8>, <16 x i8> addrspace(2)* %in %load = load <16 x i8>, <16 x i8> addrspace(4)* %in
%ext = zext <16 x i8> %load to <16 x i32> %ext = zext <16 x i8> %load to <16 x i32>
store <16 x i32> %ext, <16 x i32> addrspace(1)* %out store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i32: ; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i32:
; EG: VTX_READ_128 [[DST:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 [[DST:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 0, #1
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; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v16i8_to_v16i32(<16 x i32> addrspace(1)* %out, <16 x i8> addrspace(4)* %in) #0 {
%load = load <16 x i8>, <16 x i8> addrspace(2)* %in %load = load <16 x i8>, <16 x i8> addrspace(4)* %in
%ext = sext <16 x i8> %load to <16 x i32> %ext = sext <16 x i8> %load to <16 x i32>
store <16 x i32> %ext, <16 x i32> addrspace(1)* %out store <16 x i32> %ext, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i32: ; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i32:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
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; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_zextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(4)* %in) #0 {
%load = load <32 x i8>, <32 x i8> addrspace(2)* %in %load = load <32 x i8>, <32 x i8> addrspace(4)* %in
%ext = zext <32 x i8> %load to <32 x i32> %ext = zext <32 x i8> %load to <32 x i32>
store <32 x i32> %ext, <32 x i32> addrspace(1)* %out store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i32: ; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i32:
; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 [[DST_LO:T[0-9]+\.XYZW]], T{{[0-9]+}}.X, 0, #1
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; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
; EG-DAG: 8 ; EG-DAG: 8
define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v32i8_to_v32i32(<32 x i32> addrspace(1)* %out, <32 x i8> addrspace(4)* %in) #0 {
%load = load <32 x i8>, <32 x i8> addrspace(2)* %in %load = load <32 x i8>, <32 x i8> addrspace(4)* %in
%ext = sext <32 x i8> %load to <32 x i32> %ext = sext <32 x i8> %load to <32 x i32>
store <32 x i32> %ext, <32 x i32> addrspace(1)* %out store <32 x i32> %ext, <32 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i32: ; FUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i32:
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 16, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 32, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 32, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 48, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 48, #1
define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(4)* %in) #0 {
%load = load <64 x i8>, <64 x i8> addrspace(2)* %in %load = load <64 x i8>, <64 x i8> addrspace(4)* %in
%ext = zext <64 x i8> %load to <64 x i32> %ext = zext <64 x i8> %load to <64 x i32>
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i32: ; FUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i32:
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 16, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 32, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 32, #1
; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 48, #1 ; EG-DAG: VTX_READ_128 {{T[0-9]+\.XYZW}}, T{{[0-9]+}}.X, 48, #1
define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v64i8_to_v64i32(<64 x i32> addrspace(1)* %out, <64 x i8> addrspace(4)* %in) #0 {
%load = load <64 x i8>, <64 x i8> addrspace(2)* %in %load = load <64 x i8>, <64 x i8> addrspace(4)* %in
%ext = sext <64 x i8> %load to <64 x i32> %ext = sext <64 x i8> %load to <64 x i32>
store <64 x i32> %ext, <64 x i32> addrspace(1)* %out store <64 x i32> %ext, <64 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_i8_to_i64: ; FUNC-LABEL: {{^}}constant_zextload_i8_to_i64:
; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]], ; GCN-NOHSA-DAG: buffer_load_ubyte v[[LO:[0-9]+]],
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]] ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]]
; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]], ; GCN-HSA-DAG: flat_load_ubyte v[[LO:[0-9]+]],
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]] ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]]
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: MOV {{.*}}, 0.0 ; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @constant_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%a = load i8, i8 addrspace(2)* %in %a = load i8, i8 addrspace(4)* %in
%ext = zext i8 %a to i64 %ext = zext i8 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i8_to_i64: ; FUNC-LABEL: {{^}}constant_sextload_i8_to_i64:
; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]], ; GCN-NOHSA: buffer_load_sbyte v[[LO:[0-9]+]],
; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]], ; GCN-HSA: flat_load_sbyte v[[LO:[0-9]+]],
; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]] ; GCN: v_ashrrev_i32_e32 v[[HI:[0-9]+]], 31, v[[LO]]
; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-NOHSA: buffer_store_dwordx2 v{{\[}}[[LO]]:[[HI]]{{\]}}
; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}} ; GCN-HSA: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[LO]]:[[HI]]{{\]}}
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal ; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: Why not 7 ? ; TODO: Why not 7 ?
; EG: 31 ; EG: 31
define amdgpu_kernel void @constant_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_i8_to_i64(i64 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%a = load i8, i8 addrspace(2)* %in %a = load i8, i8 addrspace(4)* %in
%ext = sext i8 %a to i64 %ext = sext i8 %a to i64
store i64 %ext, i64 addrspace(1)* %out store i64 %ext, i64 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i64: ; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i64:
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: MOV {{.*}}, 0.0 ; EG: MOV {{.*}}, 0.0
define amdgpu_kernel void @constant_zextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(4)* %in) #0 {
%load = load <1 x i8>, <1 x i8> addrspace(2)* %in %load = load <1 x i8>, <1 x i8> addrspace(4)* %in
%ext = zext <1 x i8> %load to <1 x i64> %ext = zext <1 x i8> %load to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i64: ; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i64:
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal ; EG: ASHR {{\**}} {{T[0-9]\.[XYZW]}}, {{.*}}, literal
; TODO: Why not 7 ? ; TODO: Why not 7 ?
; EG: 31 ; EG: 31
define amdgpu_kernel void @constant_sextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v1i8_to_v1i64(<1 x i64> addrspace(1)* %out, <1 x i8> addrspace(4)* %in) #0 {
%load = load <1 x i8>, <1 x i8> addrspace(2)* %in %load = load <1 x i8>, <1 x i8> addrspace(4)* %in
%ext = sext <1 x i8> %load to <1 x i64> %ext = sext <1 x i8> %load to <1 x i64>
store <1 x i64> %ext, <1 x i64> addrspace(1)* %out store <1 x i64> %ext, <1 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i64: ; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i64:
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%load = load <2 x i8>, <2 x i8> addrspace(2)* %in %load = load <2 x i8>, <2 x i8> addrspace(4)* %in
%ext = zext <2 x i8> %load to <2 x i64> %ext = zext <2 x i8> %load to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i64: ; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i64:
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v2i8_to_v2i64(<2 x i64> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%load = load <2 x i8>, <2 x i8> addrspace(2)* %in %load = load <2 x i8>, <2 x i8> addrspace(4)* %in
%ext = sext <2 x i8> %load to <2 x i64> %ext = sext <2 x i8> %load to <2 x i64>
store <2 x i64> %ext, <2 x i64> addrspace(1)* %out store <2 x i64> %ext, <2 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i64: ; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i64:
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(4)* %in) #0 {
%load = load <4 x i8>, <4 x i8> addrspace(2)* %in %load = load <4 x i8>, <4 x i8> addrspace(4)* %in
%ext = zext <4 x i8> %load to <4 x i64> %ext = zext <4 x i8> %load to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i64: ; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i64:
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v4i8_to_v4i64(<4 x i64> addrspace(1)* %out, <4 x i8> addrspace(4)* %in) #0 {
%load = load <4 x i8>, <4 x i8> addrspace(2)* %in %load = load <4 x i8>, <4 x i8> addrspace(4)* %in
%ext = sext <4 x i8> %load to <4 x i64> %ext = sext <4 x i8> %load to <4 x i64>
store <4 x i64> %ext, <4 x i64> addrspace(1)* %out store <4 x i64> %ext, <4 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i64: ; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i64:
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(4)* %in) #0 {
%load = load <8 x i8>, <8 x i8> addrspace(2)* %in %load = load <8 x i8>, <8 x i8> addrspace(4)* %in
%ext = zext <8 x i8> %load to <8 x i64> %ext = zext <8 x i8> %load to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i64: ; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i64:
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v8i8_to_v8i64(<8 x i64> addrspace(1)* %out, <8 x i8> addrspace(4)* %in) #0 {
%load = load <8 x i8>, <8 x i8> addrspace(2)* %in %load = load <8 x i8>, <8 x i8> addrspace(4)* %in
%ext = sext <8 x i8> %load to <8 x i64> %ext = sext <8 x i8> %load to <8 x i64>
store <8 x i64> %ext, <8 x i64> addrspace(1)* %out store <8 x i64> %ext, <8 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i64: ; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i64:
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(4)* %in) #0 {
%load = load <16 x i8>, <16 x i8> addrspace(2)* %in %load = load <16 x i8>, <16 x i8> addrspace(4)* %in
%ext = zext <16 x i8> %load to <16 x i64> %ext = zext <16 x i8> %load to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i64: ; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i64:
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v16i8_to_v16i64(<16 x i64> addrspace(1)* %out, <16 x i8> addrspace(4)* %in) #0 {
%load = load <16 x i8>, <16 x i8> addrspace(2)* %in %load = load <16 x i8>, <16 x i8> addrspace(4)* %in
%ext = sext <16 x i8> %load to <16 x i64> %ext = sext <16 x i8> %load to <16 x i64>
store <16 x i64> %ext, <16 x i64> addrspace(1)* %out store <16 x i64> %ext, <16 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i64: ; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i64:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(4)* %in) #0 {
%load = load <32 x i8>, <32 x i8> addrspace(2)* %in %load = load <32 x i8>, <32 x i8> addrspace(4)* %in
%ext = zext <32 x i8> %load to <32 x i64> %ext = zext <32 x i8> %load to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i64: ; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i64:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v32i8_to_v32i64(<32 x i64> addrspace(1)* %out, <32 x i8> addrspace(4)* %in) #0 {
%load = load <32 x i8>, <32 x i8> addrspace(2)* %in %load = load <32 x i8>, <32 x i8> addrspace(4)* %in
%ext = sext <32 x i8> %load to <32 x i64> %ext = sext <32 x i8> %load to <32 x i64>
store <32 x i64> %ext, <32 x i64> addrspace(1)* %out store <32 x i64> %ext, <32 x i64> addrspace(1)* %out
ret void ret void
} }
; XFUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i64: ; XFUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i64:
; define amdgpu_kernel void @constant_zextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { ; define amdgpu_kernel void @constant_zextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(4)* %in) #0 {
; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in ; %load = load <64 x i8>, <64 x i8> addrspace(4)* %in
; %ext = zext <64 x i8> %load to <64 x i64> ; %ext = zext <64 x i8> %load to <64 x i64>
; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out ; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
; ret void ; ret void
; } ; }
; XFUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i64: ; XFUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i64:
; define amdgpu_kernel void @constant_sextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { ; define amdgpu_kernel void @constant_sextload_v64i8_to_v64i64(<64 x i64> addrspace(1)* %out, <64 x i8> addrspace(4)* %in) #0 {
; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in ; %load = load <64 x i8>, <64 x i8> addrspace(4)* %in
; %ext = sext <64 x i8> %load to <64 x i64> ; %ext = sext <64 x i8> %load to <64 x i64>
; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out ; store <64 x i64> %ext, <64 x i64> addrspace(1)* %out
; ret void ; ret void
; } ; }
; FUNC-LABEL: {{^}}constant_zextload_i8_to_i16: ; FUNC-LABEL: {{^}}constant_zextload_i8_to_i16:
; GCN-NOHSA: buffer_load_ubyte v[[VAL:[0-9]+]], ; GCN-NOHSA: buffer_load_ubyte v[[VAL:[0-9]+]],
; GCN-NOHSA: buffer_store_short v[[VAL]] ; GCN-NOHSA: buffer_store_short v[[VAL]]
; GCN-HSA: flat_load_ubyte v[[VAL:[0-9]+]], ; GCN-HSA: flat_load_ubyte v[[VAL:[0-9]+]],
; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]] ; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]]
define amdgpu_kernel void @constant_zextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%a = load i8, i8 addrspace(2)* %in %a = load i8, i8 addrspace(4)* %in
%ext = zext i8 %a to i16 %ext = zext i8 %a to i16
store i16 %ext, i16 addrspace(1)* %out store i16 %ext, i16 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_i8_to_i16: ; FUNC-LABEL: {{^}}constant_sextload_i8_to_i16:
; GCN-NOHSA: buffer_load_sbyte v[[VAL:[0-9]+]], ; GCN-NOHSA: buffer_load_sbyte v[[VAL:[0-9]+]],
; GCN-HSA: flat_load_sbyte v[[VAL:[0-9]+]], ; GCN-HSA: flat_load_sbyte v[[VAL:[0-9]+]],
; GCN-NOHSA: buffer_store_short v[[VAL]] ; GCN-NOHSA: buffer_store_short v[[VAL]]
; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]] ; GCN-HSA: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, v[[VAL]]
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_sextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_i8_to_i16(i16 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%a = load i8, i8 addrspace(2)* %in %a = load i8, i8 addrspace(4)* %in
%ext = sext i8 %a to i16 %ext = sext i8 %a to i16
store i16 %ext, i16 addrspace(1)* %out store i16 %ext, i16 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i16: ; FUNC-LABEL: {{^}}constant_zextload_v1i8_to_v1i16:
define amdgpu_kernel void @constant_zextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(4)* %in) #0 {
%load = load <1 x i8>, <1 x i8> addrspace(2)* %in %load = load <1 x i8>, <1 x i8> addrspace(4)* %in
%ext = zext <1 x i8> %load to <1 x i16> %ext = zext <1 x i8> %load to <1 x i16>
store <1 x i16> %ext, <1 x i16> addrspace(1)* %out store <1 x i16> %ext, <1 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i16: ; FUNC-LABEL: {{^}}constant_sextload_v1i8_to_v1i16:
; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_8 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v1i8_to_v1i16(<1 x i16> addrspace(1)* %out, <1 x i8> addrspace(4)* %in) #0 {
%load = load <1 x i8>, <1 x i8> addrspace(2)* %in %load = load <1 x i8>, <1 x i8> addrspace(4)* %in
%ext = sext <1 x i8> %load to <1 x i16> %ext = sext <1 x i8> %load to <1 x i16>
store <1 x i16> %ext, <1 x i16> addrspace(1)* %out store <1 x i16> %ext, <1 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i16: ; FUNC-LABEL: {{^}}constant_zextload_v2i8_to_v2i16:
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%load = load <2 x i8>, <2 x i8> addrspace(2)* %in %load = load <2 x i8>, <2 x i8> addrspace(4)* %in
%ext = zext <2 x i8> %load to <2 x i16> %ext = zext <2 x i8> %load to <2 x i16>
store <2 x i16> %ext, <2 x i16> addrspace(1)* %out store <2 x i16> %ext, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i16: ; FUNC-LABEL: {{^}}constant_sextload_v2i8_to_v2i16:
; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_16 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v2i8_to_v2i16(<2 x i16> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%load = load <2 x i8>, <2 x i8> addrspace(2)* %in %load = load <2 x i8>, <2 x i8> addrspace(4)* %in
%ext = sext <2 x i8> %load to <2 x i16> %ext = sext <2 x i8> %load to <2 x i16>
store <2 x i16> %ext, <2 x i16> addrspace(1)* %out store <2 x i16> %ext, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i16: ; FUNC-LABEL: {{^}}constant_zextload_v4i8_to_v4i16:
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(4)* %in) #0 {
%load = load <4 x i8>, <4 x i8> addrspace(2)* %in %load = load <4 x i8>, <4 x i8> addrspace(4)* %in
%ext = zext <4 x i8> %load to <4 x i16> %ext = zext <4 x i8> %load to <4 x i16>
store <4 x i16> %ext, <4 x i16> addrspace(1)* %out store <4 x i16> %ext, <4 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i16: ; FUNC-LABEL: {{^}}constant_sextload_v4i8_to_v4i16:
; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0, #1
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v4i8_to_v4i16(<4 x i16> addrspace(1)* %out, <4 x i8> addrspace(4)* %in) #0 {
%load = load <4 x i8>, <4 x i8> addrspace(2)* %in %load = load <4 x i8>, <4 x i8> addrspace(4)* %in
%ext = sext <4 x i8> %load to <4 x i16> %ext = sext <4 x i8> %load to <4 x i16>
store <4 x i16> %ext, <4 x i16> addrspace(1)* %out store <4 x i16> %ext, <4 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i16: ; FUNC-LABEL: {{^}}constant_zextload_v8i8_to_v8i16:
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(4)* %in) #0 {
%load = load <8 x i8>, <8 x i8> addrspace(2)* %in %load = load <8 x i8>, <8 x i8> addrspace(4)* %in
%ext = zext <8 x i8> %load to <8 x i16> %ext = zext <8 x i8> %load to <8 x i16>
store <8 x i16> %ext, <8 x i16> addrspace(1)* %out store <8 x i16> %ext, <8 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i16: ; FUNC-LABEL: {{^}}constant_sextload_v8i8_to_v8i16:
; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0, #1
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v8i8_to_v8i16(<8 x i16> addrspace(1)* %out, <8 x i8> addrspace(4)* %in) #0 {
%load = load <8 x i8>, <8 x i8> addrspace(2)* %in %load = load <8 x i8>, <8 x i8> addrspace(4)* %in
%ext = sext <8 x i8> %load to <8 x i16> %ext = sext <8 x i8> %load to <8 x i16>
store <8 x i16> %ext, <8 x i16> addrspace(1)* %out store <8 x i16> %ext, <8 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i16: ; FUNC-LABEL: {{^}}constant_zextload_v16i8_to_v16i16:
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(4)* %in) #0 {
%load = load <16 x i8>, <16 x i8> addrspace(2)* %in %load = load <16 x i8>, <16 x i8> addrspace(4)* %in
%ext = zext <16 x i8> %load to <16 x i16> %ext = zext <16 x i8> %load to <16 x i16>
store <16 x i16> %ext, <16 x i16> addrspace(1)* %out store <16 x i16> %ext, <16 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i16: ; FUNC-LABEL: {{^}}constant_sextload_v16i8_to_v16i16:
; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v16i8_to_v16i16(<16 x i16> addrspace(1)* %out, <16 x i8> addrspace(4)* %in) #0 {
%load = load <16 x i8>, <16 x i8> addrspace(2)* %in %load = load <16 x i8>, <16 x i8> addrspace(4)* %in
%ext = sext <16 x i8> %load to <16 x i16> %ext = sext <16 x i8> %load to <16 x i16>
store <16 x i16> %ext, <16 x i16> addrspace(1)* %out store <16 x i16> %ext, <16 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i16: ; FUNC-LABEL: {{^}}constant_zextload_v32i8_to_v32i16:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 16, #1
define amdgpu_kernel void @constant_zextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_zextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(4)* %in) #0 {
%load = load <32 x i8>, <32 x i8> addrspace(2)* %in %load = load <32 x i8>, <32 x i8> addrspace(4)* %in
%ext = zext <32 x i8> %load to <32 x i16> %ext = zext <32 x i8> %load to <32 x i16>
store <32 x i16> %ext, <32 x i16> addrspace(1)* %out store <32 x i16> %ext, <32 x i16> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i16: ; FUNC-LABEL: {{^}}constant_sextload_v32i8_to_v32i16:
; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1 ; EG-DAG: VTX_READ_128 T{{[0-9]+}}.XYZW, T{{[0-9]+}}.X, 0, #1
Show All 25 Lines
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal ; EG-DAG: BFE_INT {{[* ]*}}T{{[0-9].[XYZW]}}, {{.*}}, 0.0, literal
define amdgpu_kernel void @constant_sextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_sextload_v32i8_to_v32i16(<32 x i16> addrspace(1)* %out, <32 x i8> addrspace(4)* %in) #0 {
%load = load <32 x i8>, <32 x i8> addrspace(2)* %in %load = load <32 x i8>, <32 x i8> addrspace(4)* %in
%ext = sext <32 x i8> %load to <32 x i16> %ext = sext <32 x i8> %load to <32 x i16>
store <32 x i16> %ext, <32 x i16> addrspace(1)* %out store <32 x i16> %ext, <32 x i16> addrspace(1)* %out
ret void ret void
} }
; XFUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i16: ; XFUNC-LABEL: {{^}}constant_zextload_v64i8_to_v64i16:
; define amdgpu_kernel void @constant_zextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { ; define amdgpu_kernel void @constant_zextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(4)* %in) #0 {
; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in ; %load = load <64 x i8>, <64 x i8> addrspace(4)* %in
; %ext = zext <64 x i8> %load to <64 x i16> ; %ext = zext <64 x i8> %load to <64 x i16>
; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out ; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out
; ret void ; ret void
; } ; }
; XFUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i16: ; XFUNC-LABEL: {{^}}constant_sextload_v64i8_to_v64i16:
; define amdgpu_kernel void @constant_sextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(2)* %in) #0 { ; define amdgpu_kernel void @constant_sextload_v64i8_to_v64i16(<64 x i16> addrspace(1)* %out, <64 x i8> addrspace(4)* %in) #0 {
; %load = load <64 x i8>, <64 x i8> addrspace(2)* %in ; %load = load <64 x i8>, <64 x i8> addrspace(4)* %in
; %ext = sext <64 x i8> %load to <64 x i16> ; %ext = sext <64 x i8> %load to <64 x i16>
; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out ; store <64 x i16> %ext, <64 x i16> addrspace(1)* %out
; ret void ; ret void
; } ; }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-hi16.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094 ; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword ; GFX9-NEXT: global_store_dword
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort ; VI: flat_load_ushort
define void @load_constant_hi_v2i16_reglo_vreg(i16 addrspace(2)* %in, i16 %reg) #0 { define void @load_constant_hi_v2i16_reglo_vreg(i16 addrspace(4)* %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16 addrspace(2)* %in, i64 -2047 %gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 -2047
%load = load i16, i16 addrspace(2)* %gep %load = load i16, i16 addrspace(4)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: load_constant_hi_v2f16_reglo_vreg ; GCN-LABEL: load_constant_hi_v2f16_reglo_vreg
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094 ; GFX9-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:-4094
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword ; GFX9-NEXT: global_store_dword
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort ; VI: flat_load_ushort
define void @load_constant_hi_v2f16_reglo_vreg(half addrspace(2)* %in, half %reg) #0 { define void @load_constant_hi_v2f16_reglo_vreg(half addrspace(4)* %in, half %reg) #0 {
entry: entry:
%gep = getelementptr inbounds half, half addrspace(2)* %in, i64 -2047 %gep = getelementptr inbounds half, half addrspace(4)* %in, i64 -2047
%load = load half, half addrspace(2)* %gep %load = load half, half addrspace(4)* %gep
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; Local object gives known offset, so requires converting from offen ; Local object gives known offset, so requires converting from offen
; to offset variant. ; to offset variant.
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; GCN-LABEL: {{^}}load_constant_v2i16_split: ; GCN-LABEL: {{^}}load_constant_v2i16_split:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: global_load_ushort v2 ; GFX9-NEXT: global_load_ushort v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_load_short_d16_hi v2 ; GFX9-NEXT: global_load_short_d16_hi v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define <2 x i16> @load_constant_v2i16_split(i16 addrspace(2)* %in) #0 { define <2 x i16> @load_constant_v2i16_split(i16 addrspace(4)* %in) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16 addrspace(2)* %in, i64 1 %gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 1
%load0 = load volatile i16, i16 addrspace(2)* %in %load0 = load volatile i16, i16 addrspace(4)* %in
%load1 = load volatile i16, i16 addrspace(2)* %gep %load1 = load volatile i16, i16 addrspace(4)* %gep
%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1 ret <2 x i16> %build1
} }
; FIXME: Remove m0 init and waitcnt between reads ; FIXME: Remove m0 init and waitcnt between reads
; FIXME: Is there a cost to using the extload over not? ; FIXME: Is there a cost to using the extload over not?
; GCN-LABEL: {{^}}load_private_v2i16_split: ; GCN-LABEL: {{^}}load_private_v2i16_split:
Show All 17 Lines

test/CodeGen/AMDGPU/load-lo16.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094 ; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword ; GFX9-NEXT: global_store_dword
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort ; VI: flat_load_ushort
define void @load_constant_lo_v2i16_reglo_vreg(i16 addrspace(2)* %in, i32 %reg) #0 { define void @load_constant_lo_v2i16_reglo_vreg(i16 addrspace(4)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i16, i16 addrspace(2)* %in, i64 -2047 %gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 -2047
%load = load i16, i16 addrspace(2)* %gep %load = load i16, i16 addrspace(4)* %gep
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: load_constant_lo_v2f16_reglo_vreg ; GCN-LABEL: load_constant_lo_v2f16_reglo_vreg
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094 ; GFX9-NEXT: global_load_short_d16 v2, v[0:1], off offset:-4094
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword ; GFX9-NEXT: global_store_dword
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort ; VI: flat_load_ushort
define void @load_constant_lo_v2f16_reglo_vreg(half addrspace(2)* %in, i32 %reg) #0 { define void @load_constant_lo_v2f16_reglo_vreg(half addrspace(4)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds half, half addrspace(2)* %in, i64 -2047 %gep = getelementptr inbounds half, half addrspace(4)* %in, i64 -2047
%load = load half, half addrspace(2)* %gep %load = load half, half addrspace(4)* %gep
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0 %build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_to_offset: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_to_offset:
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094 ; GFX9-NEXT: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094
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test/CodeGen/AMDGPU/mad24-get-global-id.ll

; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; If the workgroup id range is restricted, we should be able to use ; If the workgroup id range is restricted, we should be able to use
; mad24 for the usual indexing pattern. ; mad24 for the usual indexing pattern.
declare i32 @llvm.amdgcn.workgroup.id.x() #0 declare i32 @llvm.amdgcn.workgroup.id.x() #0
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
; GCN-LABEL: {{^}}get_global_id_0: ; GCN-LABEL: {{^}}get_global_id_0:
; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff ; GCN: s_and_b32 [[WGSIZEX:s[0-9]+]], {{s[0-9]+}}, 0xffff
; GCN: v_mov_b32_e32 [[VWGSIZEX:v[0-9]+]], [[WGSIZEX]] ; GCN: v_mov_b32_e32 [[VWGSIZEX:v[0-9]+]], [[WGSIZEX]]
; GCN: v_mad_u32_u24 v{{[0-9]+}}, s8, [[VWGSIZEX]], v0 ; GCN: v_mad_u32_u24 v{{[0-9]+}}, s8, [[VWGSIZEX]], v0
define amdgpu_kernel void @get_global_id_0(i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @get_global_id_0(i32 addrspace(1)* %out) #1 {
%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%cast.dispatch.ptr = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* %cast.dispatch.ptr = bitcast i8 addrspace(4)* %dispatch.ptr to i32 addrspace(4)*
%gep = getelementptr inbounds i32, i32 addrspace(2)* %cast.dispatch.ptr, i64 1 %gep = getelementptr inbounds i32, i32 addrspace(4)* %cast.dispatch.ptr, i64 1
%workgroup.size.xy = load i32, i32 addrspace(2)* %gep, align 4, !invariant.load !0 %workgroup.size.xy = load i32, i32 addrspace(4)* %gep, align 4, !invariant.load !0
%workgroup.size.x = and i32 %workgroup.size.xy, 65535 %workgroup.size.x = and i32 %workgroup.size.xy, 65535
%workitem.id.x = call i32 @llvm.amdgcn.workitem.id.x(), !range !1 %workitem.id.x = call i32 @llvm.amdgcn.workitem.id.x(), !range !1
%workgroup.id.x = call i32 @llvm.amdgcn.workgroup.id.x(), !range !2 %workgroup.id.x = call i32 @llvm.amdgcn.workgroup.id.x(), !range !2
%mul = mul i32 %workgroup.id.x, %workgroup.size.x %mul = mul i32 %workgroup.id.x, %workgroup.size.x
%add = add i32 %mul, %workitem.id.x %add = add i32 %mul, %workitem.id.x
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test/CodeGen/AMDGPU/missing-store.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
@ptr_load = addrspace(3) global i32 addrspace(2)* undef, align 8 @ptr_load = addrspace(3) global i32 addrspace(4)* undef, align 8
; Make sure when the load from %ptr2 is folded the chain isn't lost, ; Make sure when the load from %ptr2 is folded the chain isn't lost,
; resulting in losing the store to gptr ; resulting in losing the store to gptr
; FUNC-LABEL: {{^}}missing_store_reduced: ; FUNC-LABEL: {{^}}missing_store_reduced:
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: ds_read_b64 ; SI: ds_read_b64
; SI-DAG: buffer_store_dword ; SI-DAG: buffer_store_dword
; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; SI-DAG: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; SI: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; SI: s_nop 3 ; SI: s_nop 3
; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}} ; SI: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: s_endpgm ; SI: s_endpgm
define amdgpu_kernel void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { define amdgpu_kernel void @missing_store_reduced(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
%ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @ptr_load, align 8 %ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @ptr_load, align 8
%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2 %ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 2
store i32 99, i32 addrspace(1)* %gptr, align 4 store i32 99, i32 addrspace(1)* %gptr, align 4
%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4 %tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/mubuf-shader-vgpr.ll

; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ; RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
; Test that buffer_load_format with VGPR resource descriptor is properly ; Test that buffer_load_format with VGPR resource descriptor is properly
; legalized. ; legalized.
; CHECK-LABEL: {{^}}test_none: ; CHECK-LABEL: {{^}}test_none:
; CHECK: buffer_load_format_x v0, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}} ; CHECK: buffer_load_format_x v0, off, {{s\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_vs float @test_none(<4 x i32> addrspace(2)* inreg %base, i32 %i) { define amdgpu_vs float @test_none(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
main_body: main_body:
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32 %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 0, i1 0, i1 0) %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 0, i1 0, i1 0)
ret float %tmp7 ret float %tmp7
} }
; CHECK-LABEL: {{^}}test_idxen: ; CHECK-LABEL: {{^}}test_idxen:
; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen{{$}} ; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen{{$}}
define amdgpu_vs float @test_idxen(<4 x i32> addrspace(2)* inreg %base, i32 %i) { define amdgpu_vs float @test_idxen(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
main_body: main_body:
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32 %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i1 0, i1 0) %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 0, i1 0, i1 0)
ret float %tmp7 ret float %tmp7
} }
; CHECK-LABEL: {{^}}test_offen: ; CHECK-LABEL: {{^}}test_offen:
; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}} ; CHECK: buffer_load_format_x v0, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, 0 offen{{$}}
define amdgpu_vs float @test_offen(<4 x i32> addrspace(2)* inreg %base, i32 %i) { define amdgpu_vs float @test_offen(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
main_body: main_body:
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32 %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 undef, i1 0, i1 0) %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 0, i32 undef, i1 0, i1 0)
ret float %tmp7 ret float %tmp7
} }
; CHECK-LABEL: {{^}}test_both: ; CHECK-LABEL: {{^}}test_both:
; CHECK: buffer_load_format_x v0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen{{$}} ; CHECK: buffer_load_format_x v0, {{v\[[0-9]+:[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0 idxen offen{{$}}
define amdgpu_vs float @test_both(<4 x i32> addrspace(2)* inreg %base, i32 %i) { define amdgpu_vs float @test_both(<4 x i32> addrspace(4)* inreg %base, i32 %i) {
main_body: main_body:
%ptr = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %base, i32 %i %ptr = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %base, i32 %i
%tmp2 = load <4 x i32>, <4 x i32> addrspace(2)* %ptr, align 32 %tmp2 = load <4 x i32>, <4 x i32> addrspace(4)* %ptr, align 32
%tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i1 0, i1 0) %tmp7 = call float @llvm.amdgcn.buffer.load.format.f32(<4 x i32> %tmp2, i32 undef, i32 undef, i1 0, i1 0)
ret float %tmp7 ret float %tmp7
} }
declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) nounwind readonly declare float @llvm.amdgcn.buffer.load.format.f32(<4 x i32>, i32, i32, i1, i1) nounwind readonly
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

test/CodeGen/AMDGPU/mubuf.ll

Show First 20 Lines • Show All 49 Lines • ▼ Show 20 Linesentry:
%1 = getelementptr i32, i32 addrspace(1)* %0, i64 1 %1 = getelementptr i32, i32 addrspace(1)* %0, i64 1
%2 = load i32, i32 addrspace(1)* %1 %2 = load i32, i32 addrspace(1)* %1
store i32 %2, i32 addrspace(1)* %out store i32 %2, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: {{^}}soffset_max_imm: ; CHECK-LABEL: {{^}}soffset_max_imm:
; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc ; CHECK: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 64 offen glc
define amdgpu_gs void @soffset_max_imm([6 x <4 x i32>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) { define amdgpu_gs void @soffset_max_imm([6 x <4 x i32>] addrspace(4)* byval, [17 x <4 x i32>] addrspace(4)* byval, [16 x <4 x i32>] addrspace(4)* byval, [32 x <8 x i32>] addrspace(4)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) {
main_body: main_body:
%tmp0 = getelementptr [6 x <4 x i32>], [6 x <4 x i32>] addrspace(2)* %0, i32 0, i32 0 %tmp0 = getelementptr [6 x <4 x i32>], [6 x <4 x i32>] addrspace(4)* %0, i32 0, i32 0
%tmp1 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp0 %tmp1 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp0
%tmp2 = shl i32 %6, 2 %tmp2 = shl i32 %6, 2
%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp1, i32 %tmp2, i32 64, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
%tmp4 = add i32 %6, 16 %tmp4 = add i32 %6, 16
%tmp1.4xi32 = bitcast <4 x i32> %tmp1 to <4 x i32> %tmp1.4xi32 = bitcast <4 x i32> %tmp1 to <4 x i32>
call void @llvm.amdgcn.tbuffer.store.i32(i32 %tmp3, <4 x i32> %tmp1.4xi32, i32 0, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i1 1, i1 1) call void @llvm.amdgcn.tbuffer.store.i32(i32 %tmp3, <4 x i32> %tmp1.4xi32, i32 0, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i1 1, i1 1)
ret void ret void
} }
; Make sure immediates that aren't inline constants don't get folded into ; Make sure immediates that aren't inline constants don't get folded into
; the soffset operand. ; the soffset operand.
; FIXME: for this test we should be smart enough to shift the immediate into ; FIXME: for this test we should be smart enough to shift the immediate into
; the offset field. ; the offset field.
; CHECK-LABEL: {{^}}soffset_no_fold: ; CHECK-LABEL: {{^}}soffset_no_fold:
; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x41 ; CHECK: s_movk_i32 [[SOFFSET:s[0-9]+]], 0x41
; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc ; CHECK: buffer_load_dword v{{[0-9+]}}, v{{[0-9+]}}, s[{{[0-9]+}}:{{[0-9]+}}], [[SOFFSET]] offen glc
define amdgpu_gs void @soffset_no_fold([6 x <4 x i32>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [16 x <4 x i32>] addrspace(2)* byval, [32 x <8 x i32>] addrspace(2)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) { define amdgpu_gs void @soffset_no_fold([6 x <4 x i32>] addrspace(4)* byval, [17 x <4 x i32>] addrspace(4)* byval, [16 x <4 x i32>] addrspace(4)* byval, [32 x <8 x i32>] addrspace(4)* byval, i32 inreg, i32 inreg, i32, i32, i32, i32, i32, i32, i32, i32) {
main_body: main_body:
%tmp0 = getelementptr [6 x <4 x i32>], [6 x <4 x i32>] addrspace(2)* %0, i32 0, i32 0 %tmp0 = getelementptr [6 x <4 x i32>], [6 x <4 x i32>] addrspace(4)* %0, i32 0, i32 0
%tmp1 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp0 %tmp1 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp0
%tmp2 = shl i32 %6, 2 %tmp2 = shl i32 %6, 2
%tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0) %tmp3 = call i32 @llvm.SI.buffer.load.dword.i32.i32(<4 x i32> %tmp1, i32 %tmp2, i32 65, i32 0, i32 1, i32 0, i32 1, i32 0, i32 0)
%tmp4 = add i32 %6, 16 %tmp4 = add i32 %6, 16
%tmp1.4xi32 = bitcast <4 x i32> %tmp1 to <4 x i32> %tmp1.4xi32 = bitcast <4 x i32> %tmp1 to <4 x i32>
call void @llvm.amdgcn.tbuffer.store.i32(i32 %tmp3, <4 x i32> %tmp1.4xi32, i32 0, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i1 1, i1 1) call void @llvm.amdgcn.tbuffer.store.i32(i32 %tmp3, <4 x i32> %tmp1.4xi32, i32 0, i32 %tmp4, i32 %4, i32 0, i32 4, i32 4, i1 1, i1 1)
ret void ret void
} }
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test/CodeGen/AMDGPU/multi-divergent-exit-region.ll

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%divergent.cond0 = icmp eq i32 %id.x, 0 %divergent.cond0 = icmp eq i32 %id.x, 0
br i1 %divergent.cond0, label %uniform.multi.exit.region, label %divergent.ret br i1 %divergent.cond0, label %uniform.multi.exit.region, label %divergent.ret
uniform.multi.exit.region: uniform.multi.exit.region:
%uniform.cond0 = icmp eq i32 %arg0, 4 %uniform.cond0 = icmp eq i32 %arg0, 4
br i1 %uniform.cond0, label %uniform.if, label %uniform.ret1 br i1 %uniform.cond0, label %uniform.if, label %uniform.ret1
uniform.if: uniform.if:
%sgpr0 = load volatile i32, i32 addrspace(2)* undef %sgpr0 = load volatile i32, i32 addrspace(4)* undef
%uniform.cond1 = icmp slt i32 %sgpr0, 1 %uniform.cond1 = icmp slt i32 %sgpr0, 1
br i1 %uniform.cond1, label %uniform.then, label %uniform.endif br i1 %uniform.cond1, label %uniform.then, label %uniform.endif
uniform.then: uniform.then:
%sgpr1 = load volatile i32, i32 addrspace(2)* undef %sgpr1 = load volatile i32, i32 addrspace(4)* undef
%uniform.cond2 = icmp sge i32 %sgpr1, 4 %uniform.cond2 = icmp sge i32 %sgpr1, 4
store volatile i32 33, i32 addrspace(1)* undef store volatile i32 33, i32 addrspace(1)* undef
br i1 %uniform.cond2, label %uniform.ret0, label %uniform.endif br i1 %uniform.cond2, label %uniform.ret0, label %uniform.endif
uniform.endif: uniform.endif:
store volatile i32 38, i32 addrspace(1)* undef store volatile i32 38, i32 addrspace(1)* undef
br label %uniform.ret0 br label %uniform.ret0
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test/CodeGen/AMDGPU/no-initializer-constant-addrspace.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN ; RUN: llc -march=amdgcn -mcpu=tahiti -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN
; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN ; RUN: llc -march=amdgcn -mcpu=tonga -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=GCN
; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=EG ; RUN: llc -march=r600 -mcpu=cypress -filetype=obj < %s | llvm-readobj -relocations -symbols | FileCheck %s -check-prefix=EG
; GCN: R_AMDGPU_REL32 extern_const_addrspace ; GCN: R_AMDGPU_REL32 extern_const_addrspace
; EG: R_AMDGPU_ABS32 extern_const_addrspace ; EG: R_AMDGPU_ABS32 extern_const_addrspace
; CHECK-DAG: Name: extern_const_addrspace ; CHECK-DAG: Name: extern_const_addrspace
@extern_const_addrspace = external unnamed_addr addrspace(2) constant [5 x i32], align 4 @extern_const_addrspace = external unnamed_addr addrspace(4) constant [5 x i32], align 4
; CHECK-DAG: Name: load_extern_const_init ; CHECK-DAG: Name: load_extern_const_init
define amdgpu_kernel void @load_extern_const_init(i32 addrspace(1)* %out) nounwind { define amdgpu_kernel void @load_extern_const_init(i32 addrspace(1)* %out) nounwind {
%val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @extern_const_addrspace, i64 0, i64 3), align 4 %val = load i32, i32 addrspace(4)* getelementptr ([5 x i32], [5 x i32] addrspace(4)* @extern_const_addrspace, i64 0, i64 3), align 4
store i32 %val, i32 addrspace(1)* %out, align 4 store i32 %val, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; CHECK-DAG: Name: undef_const_addrspace ; CHECK-DAG: Name: undef_const_addrspace
@undef_const_addrspace = unnamed_addr addrspace(2) constant [5 x i32] undef, align 4 @undef_const_addrspace = unnamed_addr addrspace(4) constant [5 x i32] undef, align 4
; CHECK-DAG: Name: undef_const_addrspace ; CHECK-DAG: Name: undef_const_addrspace
define amdgpu_kernel void @load_undef_const_init(i32 addrspace(1)* %out) nounwind { define amdgpu_kernel void @load_undef_const_init(i32 addrspace(1)* %out) nounwind {
%val = load i32, i32 addrspace(2)* getelementptr ([5 x i32], [5 x i32] addrspace(2)* @undef_const_addrspace, i64 0, i64 3), align 4 %val = load i32, i32 addrspace(4)* getelementptr ([5 x i32], [5 x i32] addrspace(4)* @undef_const_addrspace, i64 0, i64 3), align 4
store i32 %val, i32 addrspace(1)* %out, align 4 store i32 %val, i32 addrspace(1)* %out, align 4
ret void ret void
} }

test/CodeGen/AMDGPU/no-shrink-extloads.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
store i8 %trunc, i8 addrspace(1)* %gep.out store i8 %trunc, i8 addrspace(1)* %gep.out
ret void ret void
} }
; FUNC-LABEL: {{^}}smrd_mask_i32_to_i16 ; FUNC-LABEL: {{^}}smrd_mask_i32_to_i16
; SI: s_load_dword [[LOAD:s[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0x0 ; SI: s_load_dword [[LOAD:s[0-9]+]], s[{{[0-9]+}}:{{[0-9]+}}], 0x0
; SI: s_waitcnt lgkmcnt(0) ; SI: s_waitcnt lgkmcnt(0)
; SI: s_and_b32 s{{[0-9]+}}, [[LOAD]], 0xffff ; SI: s_and_b32 s{{[0-9]+}}, [[LOAD]], 0xffff
define amdgpu_kernel void @smrd_mask_i32_to_i16(i32 addrspace(1)* %out, i32 addrspace(2)* %in) { define amdgpu_kernel void @smrd_mask_i32_to_i16(i32 addrspace(1)* %out, i32 addrspace(4)* %in) {
entry: entry:
%val = load i32, i32 addrspace(2)* %in %val = load i32, i32 addrspace(4)* %in
%mask = and i32 %val, 65535 %mask = and i32 %val, 65535
store i32 %mask, i32 addrspace(1)* %out store i32 %mask, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}extract_hi_i64_bitcast_v2i32: ; FUNC-LABEL: {{^}}extract_hi_i64_bitcast_v2i32:
; SI: buffer_load_dword v ; SI: buffer_load_dword v
; SI: buffer_store_dword v ; SI: buffer_store_dword v
define amdgpu_kernel void @extract_hi_i64_bitcast_v2i32(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind { define amdgpu_kernel void @extract_hi_i64_bitcast_v2i32(i32 addrspace(1)* %out, <2 x i32> addrspace(1)* %in) nounwind {
%ld = load <2 x i32>, <2 x i32> addrspace(1)* %in %ld = load <2 x i32>, <2 x i32> addrspace(1)* %in
%bc = bitcast <2 x i32> %ld to i64 %bc = bitcast <2 x i32> %ld to i64
%hi = lshr i64 %bc, 32 %hi = lshr i64 %bc, 32
%trunc = trunc i64 %hi to i32 %trunc = trunc i64 %hi to i32
store i32 %trunc, i32 addrspace(1)* %out store i32 %trunc, i32 addrspace(1)* %out
ret void ret void
} }
Context not available.

test/CodeGen/AMDGPU/nullptr.ll

;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s ;RUN: llc < %s -march=amdgcn -mtriple=amdgcn---amdgiz -verify-machineinstrs | FileCheck -check-prefixes=CHECK,GCN %s
;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s ;RUN: llc < %s -march=r600 -mtriple=r600---amdgiz -verify-machineinstrs | FileCheck -check-prefixes=CHECK,R600 %s
%struct.S = type { i32 addrspace(5)*, i32 addrspace(1)*, i32 addrspace(2)*, i32 addrspace(3)*, i32*, i32 addrspace(4)*} %struct.S = type { i32 addrspace(5)*, i32 addrspace(1)*, i32 addrspace(4)*, i32 addrspace(3)*, i32*, i32 addrspace(2)*}
; CHECK-LABEL: nullptr_priv: ; CHECK-LABEL: nullptr_priv:
; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 0
@nullptr_priv = global i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*) @nullptr_priv = global i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*)
; CHECK-LABEL: nullptr_glob: ; CHECK-LABEL: nullptr_glob:
; GCN-NEXT: .quad 0 ; GCN-NEXT: .quad 0
; R600-NEXT: .long 0 ; R600-NEXT: .long 0
@nullptr_glob = global i32 addrspace(1)* addrspacecast (i32* null to i32 addrspace(1)*) @nullptr_glob = global i32 addrspace(1)* addrspacecast (i32* null to i32 addrspace(1)*)
; CHECK-LABEL: nullptr_const: ; CHECK-LABEL: nullptr_const:
; GCN-NEXT: .quad 0 ; GCN-NEXT: .quad 0
; R600-NEXT: .long 0 ; R600-NEXT: .long 0
@nullptr_const = global i32 addrspace(2)* addrspacecast (i32* null to i32 addrspace(2)*) @nullptr_const = global i32 addrspace(4)* addrspacecast (i32* null to i32 addrspace(4)*)
; CHECK-LABEL: nullptr_local: ; CHECK-LABEL: nullptr_local:
; CHECK-NEXT: .long -1 ; CHECK-NEXT: .long -1
@nullptr_local = global i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*) @nullptr_local = global i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*)
; CHECK-LABEL: nullptr_region: ; CHECK-LABEL: nullptr_region:
; CHECK-NEXT: .long -1 ; CHECK-NEXT: .long -1
@nullptr_region = global i32 addrspace(4)* addrspacecast (i32* null to i32 addrspace(4)*) @nullptr_region = global i32 addrspace(2)* addrspacecast (i32* null to i32 addrspace(2)*)
; CHECK-LABEL: nullptr6: ; CHECK-LABEL: nullptr6:
; R600-NEXT: .long 0 ; R600-NEXT: .long 0
@nullptr6 = global i32 addrspace(6)* addrspacecast (i32* null to i32 addrspace(6)*) @nullptr6 = global i32 addrspace(6)* addrspacecast (i32* null to i32 addrspace(6)*)
; CHECK-LABEL: nullptr7: ; CHECK-LABEL: nullptr7:
; R600-NEXT: .long 0 ; R600-NEXT: .long 0
@nullptr7 = global i32 addrspace(7)* addrspacecast (i32* null to i32 addrspace(7)*) @nullptr7 = global i32 addrspace(7)* addrspacecast (i32* null to i32 addrspace(7)*)
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; GCN-NEXT: .zero 4 ; GCN-NEXT: .zero 4
; GCN-NEXT: .quad 0 ; GCN-NEXT: .quad 0
; R600-NEXT: .long 0 ; R600-NEXT: .long 0
; CHECK-NEXT: .long -1 ; CHECK-NEXT: .long -1
; GCN-NEXT: .zero 4 ; GCN-NEXT: .zero 4
@structWithPointers = addrspace(1) global %struct.S { @structWithPointers = addrspace(1) global %struct.S {
i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*), i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*),
i32 addrspace(1)* addrspacecast (i32* null to i32 addrspace(1)*), i32 addrspace(1)* addrspacecast (i32* null to i32 addrspace(1)*),
i32 addrspace(2)* addrspacecast (i32* null to i32 addrspace(2)*), i32 addrspace(4)* addrspacecast (i32* null to i32 addrspace(4)*),
i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*), i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*),
i32* null, i32* null,
i32 addrspace(4)* addrspacecast (i32* null to i32 addrspace(4)*)}, align 4 i32 addrspace(2)* addrspacecast (i32* null to i32 addrspace(2)*)}, align 4

test/CodeGen/AMDGPU/pack.v2f16.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=CI %s
; GCN-LABEL: {{^}}s_pack_v2f16: ; GCN-LABEL: {{^}}s_pack_v2f16:
; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]] ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
; GFX9: ; use [[PACKED]] ; GFX9: ; use [[PACKED]]
define amdgpu_kernel void @s_pack_v2f16(i32 addrspace(2)* %in0, i32 addrspace(2)* %in1) #0 { define amdgpu_kernel void @s_pack_v2f16(i32 addrspace(4)* %in0, i32 addrspace(4)* %in1) #0 {
%val0 = load volatile i32, i32 addrspace(2)* %in0 %val0 = load volatile i32, i32 addrspace(4)* %in0
%val1 = load volatile i32, i32 addrspace(2)* %in1 %val1 = load volatile i32, i32 addrspace(4)* %in1
%lo.i = trunc i32 %val0 to i16 %lo.i = trunc i32 %val0 to i16
%hi.i = trunc i32 %val1 to i16 %hi.i = trunc i32 %val1 to i16
%lo = bitcast i16 %lo.i to half %lo = bitcast i16 %lo.i to half
%hi = bitcast i16 %hi.i to half %hi = bitcast i16 %hi.i to half
%vec.0 = insertelement <2 x half> undef, half %lo, i32 0 %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1 %vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32 %vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0 call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
ret void ret void
} }
; GCN-LABEL: {{^}}s_pack_v2f16_imm_lo: ; GCN-LABEL: {{^}}s_pack_v2f16_imm_lo:
; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1234, [[VAL1]] ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1234, [[VAL1]]
; GFX9: ; use [[PACKED]] ; GFX9: ; use [[PACKED]]
define amdgpu_kernel void @s_pack_v2f16_imm_lo(i32 addrspace(2)* %in1) #0 { define amdgpu_kernel void @s_pack_v2f16_imm_lo(i32 addrspace(4)* %in1) #0 {
%val1 = load i32, i32 addrspace(2)* %in1 %val1 = load i32, i32 addrspace(4)* %in1
%hi.i = trunc i32 %val1 to i16 %hi.i = trunc i32 %val1 to i16
%hi = bitcast i16 %hi.i to half %hi = bitcast i16 %hi.i to half
%vec.0 = insertelement <2 x half> undef, half 0xH1234, i32 0 %vec.0 = insertelement <2 x half> undef, half 0xH1234, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1 %vec.1 = insertelement <2 x half> %vec.0, half %hi, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32 %vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0 call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
ret void ret void
} }
; GCN-LABEL: {{^}}s_pack_v2f16_imm_hi: ; GCN-LABEL: {{^}}s_pack_v2f16_imm_hi:
; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1234 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1234
; GFX9: ; use [[PACKED]] ; GFX9: ; use [[PACKED]]
define amdgpu_kernel void @s_pack_v2f16_imm_hi(i32 addrspace(2)* %in0) #0 { define amdgpu_kernel void @s_pack_v2f16_imm_hi(i32 addrspace(4)* %in0) #0 {
%val0 = load i32, i32 addrspace(2)* %in0 %val0 = load i32, i32 addrspace(4)* %in0
%lo.i = trunc i32 %val0 to i16 %lo.i = trunc i32 %val0 to i16
%lo = bitcast i16 %lo.i to half %lo = bitcast i16 %lo.i to half
%vec.0 = insertelement <2 x half> undef, half %lo, i32 0 %vec.0 = insertelement <2 x half> undef, half %lo, i32 0
%vec.1 = insertelement <2 x half> %vec.0, half 0xH1234, i32 1 %vec.1 = insertelement <2 x half> %vec.0, half 0xH1234, i32 1
%vec.i32 = bitcast <2 x half> %vec.1 to i32 %vec.i32 = bitcast <2 x half> %vec.1 to i32
call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0 call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
ret void ret void
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test/CodeGen/AMDGPU/pack.v2i16.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 -mattr=-flat-for-global,-fp64-fp16-denormals -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=CI %s
; GCN-LABEL: {{^}}s_pack_v2i16: ; GCN-LABEL: {{^}}s_pack_v2i16:
; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]] ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], [[VAL1]]
; GFX9: ; use [[PACKED]] ; GFX9: ; use [[PACKED]]
define amdgpu_kernel void @s_pack_v2i16(i32 addrspace(2)* %in0, i32 addrspace(2)* %in1) #0 { define amdgpu_kernel void @s_pack_v2i16(i32 addrspace(4)* %in0, i32 addrspace(4)* %in1) #0 {
%val0 = load volatile i32, i32 addrspace(2)* %in0 %val0 = load volatile i32, i32 addrspace(4)* %in0
%val1 = load volatile i32, i32 addrspace(2)* %in1 %val1 = load volatile i32, i32 addrspace(4)* %in1
%lo = trunc i32 %val0 to i16 %lo = trunc i32 %val0 to i16
%hi = trunc i32 %val1 to i16 %hi = trunc i32 %val1 to i16
%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0 %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1 %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32 %vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0 call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
ret void ret void
} }
; GCN-LABEL: {{^}}s_pack_v2i16_imm_lo: ; GCN-LABEL: {{^}}s_pack_v2i16_imm_lo:
; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1c8, [[VAL1]] ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], 0x1c8, [[VAL1]]
; GFX9: ; use [[PACKED]] ; GFX9: ; use [[PACKED]]
define amdgpu_kernel void @s_pack_v2i16_imm_lo(i32 addrspace(2)* %in1) #0 { define amdgpu_kernel void @s_pack_v2i16_imm_lo(i32 addrspace(4)* %in1) #0 {
%val1 = load i32, i32 addrspace(2)* %in1 %val1 = load i32, i32 addrspace(4)* %in1
%hi = trunc i32 %val1 to i16 %hi = trunc i32 %val1 to i16
%vec.0 = insertelement <2 x i16> undef, i16 456, i32 0 %vec.0 = insertelement <2 x i16> undef, i16 456, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1 %vec.1 = insertelement <2 x i16> %vec.0, i16 %hi, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32 %vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0 call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
ret void ret void
} }
; GCN-LABEL: {{^}}s_pack_v2i16_imm_hi: ; GCN-LABEL: {{^}}s_pack_v2i16_imm_hi:
; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1c8 ; GFX9: s_pack_ll_b32_b16 [[PACKED:s[0-9]+]], [[VAL0]], 0x1c8
; GFX9: ; use [[PACKED]] ; GFX9: ; use [[PACKED]]
define amdgpu_kernel void @s_pack_v2i16_imm_hi(i32 addrspace(2)* %in0) #0 { define amdgpu_kernel void @s_pack_v2i16_imm_hi(i32 addrspace(4)* %in0) #0 {
%val0 = load i32, i32 addrspace(2)* %in0 %val0 = load i32, i32 addrspace(4)* %in0
%lo = trunc i32 %val0 to i16 %lo = trunc i32 %val0 to i16
%vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0 %vec.0 = insertelement <2 x i16> undef, i16 %lo, i32 0
%vec.1 = insertelement <2 x i16> %vec.0, i16 456, i32 1 %vec.1 = insertelement <2 x i16> %vec.0, i16 456, i32 1
%vec.i32 = bitcast <2 x i16> %vec.1 to i32 %vec.i32 = bitcast <2 x i16> %vec.1 to i32
call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0 call void asm sideeffect "; use $0", "s"(i32 %vec.i32) #0
ret void ret void
} }
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test/CodeGen/AMDGPU/r600-constant-array-fixup.ll

; RUN: llc -filetype=obj -march=r600 -mcpu=cypress -verify-machineinstrs < %s | llvm-readobj -relocations -symbols | FileCheck %s ; RUN: llc -filetype=obj -march=r600 -mcpu=cypress -verify-machineinstrs < %s | llvm-readobj -relocations -symbols | FileCheck %s
@arr = internal unnamed_addr addrspace(2) constant [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 4 @arr = internal unnamed_addr addrspace(4) constant [4 x i32] [i32 4, i32 5, i32 6, i32 7], align 4
; CHECK: Relocations [ ; CHECK: Relocations [
; CHECK: Section (3) .rel.text { ; CHECK: Section (3) .rel.text {
; CHECK: 0x58 R_AMDGPU_ABS32 .text 0x0 ; CHECK: 0x58 R_AMDGPU_ABS32 .text 0x0
; CHECK: } ; CHECK: }
; CHECK: ] ; CHECK: ]
; CHECK: Symbol { ; CHECK: Symbol {
; CHECK: Name: arr (11) ; CHECK: Name: arr (11)
; CHECK: Value: 0x70 ; CHECK: Value: 0x70
; CHECK: Size: 16 ; CHECK: Size: 16
; CHECK: Binding: Local (0x0) ; CHECK: Binding: Local (0x0)
; CHECK: Type: Object (0x1) ; CHECK: Type: Object (0x1)
; CHECK: Other: 0 ; CHECK: Other: 0
; CHECK: Section: .text (0x2) ; CHECK: Section: .text (0x2)
; CHECK: } ; CHECK: }
define amdgpu_kernel void @test_constant_array_fixup(i32 addrspace(1)* nocapture %out, i32 %idx) #0 { define amdgpu_kernel void @test_constant_array_fixup(i32 addrspace(1)* nocapture %out, i32 %idx) #0 {
entry: entry:
%arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(2)* @arr, i32 0, i32 %idx %arrayidx = getelementptr inbounds [4 x i32], [4 x i32] addrspace(4)* @arr, i32 0, i32 %idx
%val = load i32, i32 addrspace(2)* %arrayidx %val = load i32, i32 addrspace(4)* %arrayidx
store i32 %val, i32 addrspace(1)* %out, align 4 store i32 %val, i32 addrspace(1)* %out, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/readcyclecounter.ll

Show All 22 Lines
} }
; This test used to crash in ScheduleDAG. ; This test used to crash in ScheduleDAG.
; ;
; GCN-LABEL: {{^}}test_readcyclecounter_smem: ; GCN-LABEL: {{^}}test_readcyclecounter_smem:
; SI-DAG: s_memtime ; SI-DAG: s_memtime
; VI-DAG: s_memrealtime ; VI-DAG: s_memrealtime
; GCN-DAG: s_load_dword ; GCN-DAG: s_load_dword
define amdgpu_cs i32 @test_readcyclecounter_smem(i64 addrspace(2)* inreg %in) #0 { define amdgpu_cs i32 @test_readcyclecounter_smem(i64 addrspace(4)* inreg %in) #0 {
%cycle0 = call i64 @llvm.readcyclecounter() %cycle0 = call i64 @llvm.readcyclecounter()
%in.v = load i64, i64 addrspace(2)* %in %in.v = load i64, i64 addrspace(4)* %in
%r.64 = add i64 %cycle0, %in.v %r.64 = add i64 %cycle0, %in.v
%r.32 = trunc i64 %r.64 to i32 %r.32 = trunc i64 %r.64 to i32
ret i32 %r.32 ret i32 %r.32
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/ret.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}vgpr: ; GCN-LABEL: {{^}}vgpr:
; GCN-DAG: v_mov_b32_e32 v1, v0 ; GCN-DAG: v_mov_b32_e32 v1, v0
; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm ; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm
; GCN: s_waitcnt expcnt(0) ; GCN: s_waitcnt expcnt(0)
; GCN: v_add_f32_e32 v0, 1.0, v0 ; GCN: v_add_f32_e32 v0, 1.0, v0
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_vs { float, float } @vgpr([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 { define amdgpu_vs { float, float } @vgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: bb:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
%x = fadd float %arg3, 1.000000e+00 %x = fadd float %arg3, 1.000000e+00
%a = insertvalue { float, float } undef, float %x, 0 %a = insertvalue { float, float } undef, float %x, 0
%b = insertvalue { float, float } %a, float %arg3, 1 %b = insertvalue { float, float } %a, float %arg3, 1
ret { float, float } %b ret { float, float } %b
} }
; GCN-LABEL: {{^}}vgpr_literal: ; GCN-LABEL: {{^}}vgpr_literal:
; GCN: v_mov_b32_e32 v4, v0 ; GCN: v_mov_b32_e32 v4, v0
; GCN: exp mrt0 v4, v4, v4, v4 done vm ; GCN: exp mrt0 v4, v4, v4, v4 done vm
; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
; GCN-DAG: v_mov_b32_e32 v2, 4.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
; GCN-DAG: v_mov_b32_e32 v3, -1.0 ; GCN-DAG: v_mov_b32_e32 v3, -1.0
; GCN: s_waitcnt expcnt(0) ; GCN: s_waitcnt expcnt(0)
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_vs { float, float, float, float } @vgpr_literal([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 { define amdgpu_vs { float, float, float, float } @vgpr_literal([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: bb:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
ret { float, float, float, float } { float 1.000000e+00, float 2.000000e+00, float 4.000000e+00, float -1.000000e+00 } ret { float, float, float, float } { float 1.000000e+00, float 2.000000e+00, float 4.000000e+00, float -1.000000e+00 }
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 562 ; GCN-NEXT: .long 562
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 562 ; GCN-NEXT: .long 562
; GCN-LABEL: {{^}}vgpr_ps_addr0: ; GCN-LABEL: {{^}}vgpr_ps_addr0:
; GCN-NOT: v_mov_b32_e32 v0 ; GCN-NOT: v_mov_b32_e32 v0
; GCN-NOT: v_mov_b32_e32 v1 ; GCN-NOT: v_mov_b32_e32 v1
; GCN-NOT: v_mov_b32_e32 v2 ; GCN-NOT: v_mov_b32_e32 v2
; GCN: v_mov_b32_e32 v3, v4 ; GCN: v_mov_b32_e32 v3, v4
; GCN: v_mov_b32_e32 v4, v6 ; GCN: v_mov_b32_e32 v4, v6
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr0([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 { define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr0([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {
bb: bb:
%i0 = extractelement <2 x i32> %arg4, i32 0 %i0 = extractelement <2 x i32> %arg4, i32 0
%i1 = extractelement <2 x i32> %arg4, i32 1 %i1 = extractelement <2 x i32> %arg4, i32 1
%i2 = extractelement <2 x i32> %arg7, i32 0 %i2 = extractelement <2 x i32> %arg7, i32 0
%i3 = extractelement <2 x i32> %arg8, i32 0 %i3 = extractelement <2 x i32> %arg8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float %f3 = bitcast i32 %i3 to float
%r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0 %r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
%r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
%r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
%r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
%r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4
ret { float, float, float, float, float } %r4 ret { float, float, float, float, float } %r4
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 1 ; GCN-NEXT: .long 1
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 1 ; GCN-NEXT: .long 1
; GCN-LABEL: {{^}}ps_input_ena_no_inputs: ; GCN-LABEL: {{^}}ps_input_ena_no_inputs:
; GCN: v_mov_b32_e32 v0, 1.0 ; GCN: v_mov_b32_e32 v0, 1.0
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_ps float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 { define amdgpu_ps float @ps_input_ena_no_inputs([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {
bb: bb:
ret float 1.000000e+00 ret float 1.000000e+00
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 2081 ; GCN-NEXT: .long 2081
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 2081 ; GCN-NEXT: .long 2081
; GCN-LABEL: {{^}}ps_input_ena_pos_w: ; GCN-LABEL: {{^}}ps_input_ena_pos_w:
; GCN-DAG: v_mov_b32_e32 v0, v4 ; GCN-DAG: v_mov_b32_e32 v0, v4
; GCN-DAG: v_mov_b32_e32 v1, v2 ; GCN-DAG: v_mov_b32_e32 v1, v2
; GCN: v_mov_b32_e32 v2, v3 ; GCN: v_mov_b32_e32 v2, v3
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_ps { float, <2 x float> } @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 { define amdgpu_ps { float, <2 x float> } @ps_input_ena_pos_w([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #1 {
bb: bb:
%f = bitcast <2 x i32> %arg8 to <2 x float> %f = bitcast <2 x i32> %arg8 to <2 x float>
%s = insertvalue { float, <2 x float> } undef, float %arg14, 0 %s = insertvalue { float, <2 x float> } undef, float %arg14, 0
%s1 = insertvalue { float, <2 x float> } %s, <2 x float> %f, 1 %s1 = insertvalue { float, <2 x float> } %s, <2 x float> %f, 1
ret { float, <2 x float> } %s1 ret { float, <2 x float> } %s1
} }
; GCN: .long 165580 ; GCN: .long 165580
; GCN-NEXT: .long 562 ; GCN-NEXT: .long 562
; GCN-NEXT: .long 165584 ; GCN-NEXT: .long 165584
; GCN-NEXT: .long 563 ; GCN-NEXT: .long 563
; GCN-LABEL: {{^}}vgpr_ps_addr1: ; GCN-LABEL: {{^}}vgpr_ps_addr1:
; GCN-DAG: v_mov_b32_e32 v0, v2 ; GCN-DAG: v_mov_b32_e32 v0, v2
; GCN-DAG: v_mov_b32_e32 v1, v3 ; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mov_b32_e32 v2, v4 ; GCN: v_mov_b32_e32 v2, v4
; GCN-DAG: v_mov_b32_e32 v3, v6 ; GCN-DAG: v_mov_b32_e32 v3, v6
; GCN-DAG: v_mov_b32_e32 v4, v8 ; GCN-DAG: v_mov_b32_e32 v4, v8
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr1([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #2 { define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr1([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #2 {
bb: bb:
%i0 = extractelement <2 x i32> %arg4, i32 0 %i0 = extractelement <2 x i32> %arg4, i32 0
%i1 = extractelement <2 x i32> %arg4, i32 1 %i1 = extractelement <2 x i32> %arg4, i32 1
%i2 = extractelement <2 x i32> %arg7, i32 0 %i2 = extractelement <2 x i32> %arg7, i32 0
%i3 = extractelement <2 x i32> %arg8, i32 0 %i3 = extractelement <2 x i32> %arg8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
Show All 12 Lines
; GCN-NEXT: .long 631 ; GCN-NEXT: .long 631
; GCN-LABEL: {{^}}vgpr_ps_addr119: ; GCN-LABEL: {{^}}vgpr_ps_addr119:
; GCN-DAG: v_mov_b32_e32 v0, v2 ; GCN-DAG: v_mov_b32_e32 v0, v2
; GCN-DAG: v_mov_b32_e32 v1, v3 ; GCN-DAG: v_mov_b32_e32 v1, v3
; GCN: v_mov_b32_e32 v2, v6 ; GCN: v_mov_b32_e32 v2, v6
; GCN: v_mov_b32_e32 v3, v8 ; GCN: v_mov_b32_e32 v3, v8
; GCN: v_mov_b32_e32 v4, v12 ; GCN: v_mov_b32_e32 v4, v12
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr119([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #3 { define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr119([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #3 {
bb: bb:
%i0 = extractelement <2 x i32> %arg4, i32 0 %i0 = extractelement <2 x i32> %arg4, i32 0
%i1 = extractelement <2 x i32> %arg4, i32 1 %i1 = extractelement <2 x i32> %arg4, i32 1
%i2 = extractelement <2 x i32> %arg7, i32 0 %i2 = extractelement <2 x i32> %arg7, i32 0
%i3 = extractelement <2 x i32> %arg8, i32 0 %i3 = extractelement <2 x i32> %arg8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
Show All 12 Lines
; GCN-NEXT: .long 946 ; GCN-NEXT: .long 946
; GCN-LABEL: {{^}}vgpr_ps_addr418: ; GCN-LABEL: {{^}}vgpr_ps_addr418:
; GCN-NOT: v_mov_b32_e32 v0 ; GCN-NOT: v_mov_b32_e32 v0
; GCN-NOT: v_mov_b32_e32 v1 ; GCN-NOT: v_mov_b32_e32 v1
; GCN-NOT: v_mov_b32_e32 v2 ; GCN-NOT: v_mov_b32_e32 v2
; GCN: v_mov_b32_e32 v3, v4 ; GCN: v_mov_b32_e32 v3, v4
; GCN: v_mov_b32_e32 v4, v8 ; GCN: v_mov_b32_e32 v4, v8
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr418([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #4 { define amdgpu_ps { float, float, float, float, float } @vgpr_ps_addr418([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, <2 x i32> %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <3 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, float %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18) #4 {
bb: bb:
%i0 = extractelement <2 x i32> %arg4, i32 0 %i0 = extractelement <2 x i32> %arg4, i32 0
%i1 = extractelement <2 x i32> %arg4, i32 1 %i1 = extractelement <2 x i32> %arg4, i32 1
%i2 = extractelement <2 x i32> %arg7, i32 0 %i2 = extractelement <2 x i32> %arg7, i32 0
%i3 = extractelement <2 x i32> %arg8, i32 0 %i3 = extractelement <2 x i32> %arg8, i32 0
%f0 = bitcast i32 %i0 to float %f0 = bitcast i32 %i0 to float
%f1 = bitcast i32 %i1 to float %f1 = bitcast i32 %i1 to float
%f2 = bitcast i32 %i2 to float %f2 = bitcast i32 %i2 to float
%f3 = bitcast i32 %i3 to float %f3 = bitcast i32 %i3 to float
%r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0 %r0 = insertvalue { float, float, float, float, float } undef, float %f0, 0
%r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1 %r1 = insertvalue { float, float, float, float, float } %r0, float %f1, 1
%r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2 %r2 = insertvalue { float, float, float, float, float } %r1, float %f2, 2
%r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3 %r3 = insertvalue { float, float, float, float, float } %r2, float %f3, 3
%r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4 %r4 = insertvalue { float, float, float, float, float } %r3, float %arg12, 4
ret { float, float, float, float, float } %r4 ret { float, float, float, float, float } %r4
} }
; GCN-LABEL: {{^}}sgpr: ; GCN-LABEL: {{^}}sgpr:
; GCN: s_add_i32 s0, s3, 2 ; GCN: s_add_i32 s0, s3, 2
; GCN: s_mov_b32 s2, s3 ; GCN: s_mov_b32 s2, s3
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_vs { i32, i32, i32 } @sgpr([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 { define amdgpu_vs { i32, i32, i32 } @sgpr([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: bb:
%x = add i32 %arg2, 2 %x = add i32 %arg2, 2
%a = insertvalue { i32, i32, i32 } undef, i32 %x, 0 %a = insertvalue { i32, i32, i32 } undef, i32 %x, 0
%b = insertvalue { i32, i32, i32 } %a, i32 %arg1, 1 %b = insertvalue { i32, i32, i32 } %a, i32 %arg1, 1
%c = insertvalue { i32, i32, i32 } %a, i32 %arg2, 2 %c = insertvalue { i32, i32, i32 } %a, i32 %arg2, 2
ret { i32, i32, i32 } %c ret { i32, i32, i32 } %c
} }
; GCN-LABEL: {{^}}sgpr_literal: ; GCN-LABEL: {{^}}sgpr_literal:
; GCN: s_mov_b32 s0, 5 ; GCN: s_mov_b32 s0, 5
; GCN-NOT: s_mov_b32 s0, s0 ; GCN-NOT: s_mov_b32 s0, s0
; GCN-DAG: s_mov_b32 s1, 6 ; GCN-DAG: s_mov_b32 s1, 6
; GCN-DAG: s_mov_b32 s2, 7 ; GCN-DAG: s_mov_b32 s2, 7
; GCN-DAG: s_mov_b32 s3, 8 ; GCN-DAG: s_mov_b32 s3, 8
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_vs { i32, i32, i32, i32 } @sgpr_literal([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 { define amdgpu_vs { i32, i32, i32, i32 } @sgpr_literal([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: bb:
%x = add i32 %arg2, 2 %x = add i32 %arg2, 2
ret { i32, i32, i32, i32 } { i32 5, i32 6, i32 7, i32 8 } ret { i32, i32, i32, i32 } { i32 5, i32 6, i32 7, i32 8 }
} }
; GCN-LABEL: {{^}}both: ; GCN-LABEL: {{^}}both:
; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm ; GCN-DAG: exp mrt0 v0, v0, v0, v0 done vm
; GCN-DAG: v_mov_b32_e32 v1, v0 ; GCN-DAG: v_mov_b32_e32 v1, v0
; GCN-DAG: s_mov_b32 s1, s2 ; GCN-DAG: s_mov_b32 s1, s2
; GCN: s_waitcnt expcnt(0) ; GCN: s_waitcnt expcnt(0)
; GCN: v_add_f32_e32 v0, 1.0, v0 ; GCN: v_add_f32_e32 v0, 1.0, v0
; GCN-DAG: s_add_i32 s0, s3, 2 ; GCN-DAG: s_add_i32 s0, s3, 2
; GCN-DAG: s_mov_b32 s2, s3 ; GCN-DAG: s_mov_b32 s2, s3
; GCN-NOT: s_endpgm ; GCN-NOT: s_endpgm
define amdgpu_vs { float, i32, float, i32, i32 } @both([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 { define amdgpu_vs { float, i32, float, i32, i32 } @both([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: bb:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
%v = fadd float %arg3, 1.000000e+00 %v = fadd float %arg3, 1.000000e+00
%s = add i32 %arg2, 2 %s = add i32 %arg2, 2
%a0 = insertvalue { float, i32, float, i32, i32 } undef, float %v, 0 %a0 = insertvalue { float, i32, float, i32, i32 } undef, float %v, 0
%a1 = insertvalue { float, i32, float, i32, i32 } %a0, i32 %s, 1 %a1 = insertvalue { float, i32, float, i32, i32 } %a0, i32 %s, 1
%a2 = insertvalue { float, i32, float, i32, i32 } %a1, float %arg3, 2 %a2 = insertvalue { float, i32, float, i32, i32 } %a1, float %arg3, 2
%a3 = insertvalue { float, i32, float, i32, i32 } %a2, i32 %arg1, 3 %a3 = insertvalue { float, i32, float, i32, i32 } %a2, i32 %arg1, 3
%a4 = insertvalue { float, i32, float, i32, i32 } %a3, i32 %arg2, 4 %a4 = insertvalue { float, i32, float, i32, i32 } %a3, i32 %arg2, 4
ret { float, i32, float, i32, i32 } %a4 ret { float, i32, float, i32, i32 } %a4
} }
; GCN-LABEL: {{^}}structure_literal: ; GCN-LABEL: {{^}}structure_literal:
; GCN: v_mov_b32_e32 v3, v0 ; GCN: v_mov_b32_e32 v3, v0
; GCN: exp mrt0 v3, v3, v3, v3 done vm ; GCN: exp mrt0 v3, v3, v3, v3 done vm
; GCN-DAG: v_mov_b32_e32 v0, 1.0 ; GCN-DAG: v_mov_b32_e32 v0, 1.0
; GCN-DAG: s_mov_b32 s0, 2 ; GCN-DAG: s_mov_b32 s0, 2
; GCN-DAG: s_mov_b32 s1, 3 ; GCN-DAG: s_mov_b32 s1, 3
; GCN-DAG: v_mov_b32_e32 v1, 2.0 ; GCN-DAG: v_mov_b32_e32 v1, 2.0
; GCN-DAG: v_mov_b32_e32 v2, 4.0 ; GCN-DAG: v_mov_b32_e32 v2, 4.0
; GCN: s_waitcnt expcnt(0) ; GCN: s_waitcnt expcnt(0)
define amdgpu_vs { { float, i32 }, { i32, <2 x float> } } @structure_literal([9 x <16 x i8>] addrspace(2)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 { define amdgpu_vs { { float, i32 }, { i32, <2 x float> } } @structure_literal([9 x <16 x i8>] addrspace(4)* byval %arg, i32 inreg %arg1, i32 inreg %arg2, float %arg3) #0 {
bb: bb:
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %arg3, float %arg3, float %arg3, float %arg3, i1 true, i1 true) #0
ret { { float, i32 }, { i32, <2 x float> } } { { float, i32 } { float 1.000000e+00, i32 2 }, { i32, <2 x float> } { i32 3, <2 x float> <float 2.000000e+00, float 4.000000e+00> } } ret { { float, i32 }, { i32, <2 x float> } } { { float, i32 } { float 1.000000e+00, i32 2 }, { i32, <2 x float> } { i32 3, <2 x float> <float 2.000000e+00, float 4.000000e+00> } }
} }
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0 declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind "InitialPSInputAddr"="0" } attributes #1 = { nounwind "InitialPSInputAddr"="0" }
attributes #2 = { nounwind "InitialPSInputAddr"="1" } attributes #2 = { nounwind "InitialPSInputAddr"="1" }
attributes #3 = { nounwind "InitialPSInputAddr"="119" } attributes #3 = { nounwind "InitialPSInputAddr"="119" }
attributes #4 = { nounwind "InitialPSInputAddr"="418" } attributes #4 = { nounwind "InitialPSInputAddr"="418" }

test/CodeGen/AMDGPU/salu-to-valu.ll

Show First 20 Lines • Show All 59 Lines • ▼ Show 20 Lines
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; SI: s_nop 3 ; SI: s_nop 3
; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]] ; SI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, [[OFFSET]]
; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8 ; CI: s_load_dword [[OUT:s[0-9]+]], s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xbb8
; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]] ; GCN: v_mov_b32_e32 [[V_OUT:v[0-9]+]], [[OUT]]
; GCN-NOHSA: buffer_store_dword [[V_OUT]] ; GCN-NOHSA: buffer_store_dword [[V_OUT]]
; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]] ; GCN-HSA: flat_store_dword {{.*}}, [[V_OUT]]
define amdgpu_kernel void @smrd_valu(i32 addrspace(2)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 { define amdgpu_kernel void @smrd_valu(i32 addrspace(4)* addrspace(1)* %in, i32 %a, i32 %b, i32 addrspace(1)* %out) #1 {
entry: entry:
%tmp = icmp ne i32 %a, 0 %tmp = icmp ne i32 %a, 0
br i1 %tmp, label %if, label %else br i1 %tmp, label %if, label %else
if: ; preds = %entry if: ; preds = %entry
%tmp1 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in %tmp1 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %in
br label %endif br label %endif
else: ; preds = %entry else: ; preds = %entry
%tmp2 = getelementptr i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %in %tmp2 = getelementptr i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %in
%tmp3 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(1)* %tmp2 %tmp3 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(1)* %tmp2
br label %endif br label %endif
endif: ; preds = %else, %if endif: ; preds = %else, %if
%tmp4 = phi i32 addrspace(2)* [ %tmp1, %if ], [ %tmp3, %else ] %tmp4 = phi i32 addrspace(4)* [ %tmp1, %if ], [ %tmp3, %else ]
%tmp5 = getelementptr i32, i32 addrspace(2)* %tmp4, i32 3000 %tmp5 = getelementptr i32, i32 addrspace(4)* %tmp4, i32 3000
%tmp6 = load i32, i32 addrspace(2)* %tmp5 %tmp6 = load i32, i32 addrspace(4)* %tmp5
store i32 %tmp6, i32 addrspace(1)* %out store i32 %tmp6, i32 addrspace(1)* %out
ret void ret void
} }
; Test moving an SMRD with an immediate offset to the VALU ; Test moving an SMRD with an immediate offset to the VALU
; GCN-LABEL: {{^}}smrd_valu2: ; GCN-LABEL: {{^}}smrd_valu2:
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16{{$}} ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64 offset:16{{$}}
; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in) #1 { define amdgpu_kernel void @smrd_valu2(i32 addrspace(1)* %out, [8 x i32] addrspace(4)* %in) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = add i32 %tmp, 4 %tmp1 = add i32 %tmp, 4
%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(4)* %in, i32 %tmp, i32 4
%tmp3 = load i32, i32 addrspace(2)* %tmp2 %tmp3 = load i32, i32 addrspace(4)* %tmp2
store i32 %tmp3, i32 addrspace(1)* %out store i32 %tmp3, i32 addrspace(1)* %out
ret void ret void
} }
; Use a big offset that will use the SMRD literal offset on CI ; Use a big offset that will use the SMRD literal offset on CI
; GCN-LABEL: {{^}}smrd_valu_ci_offset: ; GCN-LABEL: {{^}}smrd_valu_ci_offset:
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4e20{{$}} ; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4e20{{$}}
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}} ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: buffer_store_dword ; GCN-NOHSA: buffer_store_dword
; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}] ; GCN-HSA: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}]
; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} ; GCN-HSA: flat_store_dword v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}}
define amdgpu_kernel void @smrd_valu_ci_offset(i32 addrspace(1)* %out, i32 addrspace(2)* %in, i32 %c) #1 { define amdgpu_kernel void @smrd_valu_ci_offset(i32 addrspace(1)* %out, i32 addrspace(4)* %in, i32 %c) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr i32, i32 addrspace(2)* %in, i32 %tmp %tmp2 = getelementptr i32, i32 addrspace(4)* %in, i32 %tmp
%tmp3 = getelementptr i32, i32 addrspace(2)* %tmp2, i32 5000 %tmp3 = getelementptr i32, i32 addrspace(4)* %tmp2, i32 5000
%tmp4 = load i32, i32 addrspace(2)* %tmp3 %tmp4 = load i32, i32 addrspace(4)* %tmp3
%tmp5 = add i32 %tmp4, %c %tmp5 = add i32 %tmp4, %c
store i32 %tmp5, i32 addrspace(1)* %out store i32 %tmp5, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x2: ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x2:
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: s_mov_b32 [[OFFSET:s[0-9]+]], 0x9c40{{$}} ; GCN-NOHSA: s_mov_b32 [[OFFSET:s[0-9]+]], 0x9c40{{$}}
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}} ; GCN-NOHSA: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: buffer_store_dwordx2 ; GCN-NOHSA: buffer_store_dwordx2
; GCN-HSA: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] ; GCN-HSA: flat_load_dwordx2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @smrd_valu_ci_offset_x2(i64 addrspace(1)* %out, i64 addrspace(2)* %in, i64 %c) #1 { define amdgpu_kernel void @smrd_valu_ci_offset_x2(i64 addrspace(1)* %out, i64 addrspace(4)* %in, i64 %c) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr i64, i64 addrspace(2)* %in, i32 %tmp %tmp2 = getelementptr i64, i64 addrspace(4)* %in, i32 %tmp
%tmp3 = getelementptr i64, i64 addrspace(2)* %tmp2, i32 5000 %tmp3 = getelementptr i64, i64 addrspace(4)* %tmp2, i32 5000
%tmp4 = load i64, i64 addrspace(2)* %tmp3 %tmp4 = load i64, i64 addrspace(4)* %tmp3
%tmp5 = or i64 %tmp4, %c %tmp5 = or i64 %tmp4, %c
store i64 %tmp5, i64 addrspace(1)* %out store i64 %tmp5, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x4: ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x4:
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4d20{{$}} ; GCN-NOHSA: s_movk_i32 [[OFFSET:s[0-9]+]], 0x4d20{{$}}
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}} ; GCN-NOHSA: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, s[{{[0-9]+:[0-9]+}}], [[OFFSET]] addr64{{$}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] ; GCN-HSA: flat_load_dwordx4 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @smrd_valu_ci_offset_x4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(2)* %in, <4 x i32> %c) #1 { define amdgpu_kernel void @smrd_valu_ci_offset_x4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(4)* %in, <4 x i32> %c) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %in, i32 %tmp %tmp2 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %in, i32 %tmp
%tmp3 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %tmp2, i32 1234 %tmp3 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %tmp2, i32 1234
%tmp4 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp3 %tmp4 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp3
%tmp5 = or <4 x i32> %tmp4, %c %tmp5 = or <4 x i32> %tmp4, %c
store <4 x i32> %tmp5, <4 x i32> addrspace(1)* %out store <4 x i32> %tmp5, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; Original scalar load uses SGPR offset on SI and 32-bit literal on ; Original scalar load uses SGPR offset on SI and 32-bit literal on
; CI. ; CI.
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; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}} ; GCN-NOHSA: v_or_b32_e32 {{v[0-9]+}}, {{s[0-9]+}}, {{v[0-9]+}}
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
define amdgpu_kernel void @smrd_valu_ci_offset_x8(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(2)* %in, <8 x i32> %c) #1 { define amdgpu_kernel void @smrd_valu_ci_offset_x8(<8 x i32> addrspace(1)* %out, <8 x i32> addrspace(4)* %in, <8 x i32> %c) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %in, i32 %tmp %tmp2 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %in, i32 %tmp
%tmp3 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %tmp2, i32 1234 %tmp3 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %tmp2, i32 1234
%tmp4 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp3 %tmp4 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp3
%tmp5 = or <8 x i32> %tmp4, %c %tmp5 = or <8 x i32> %tmp4, %c
store <8 x i32> %tmp5, <8 x i32> addrspace(1)* %out store <8 x i32> %tmp5, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16: ; GCN-LABEL: {{^}}smrd_valu_ci_offset_x16:
; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}} ; GCN-NOHSA-DAG: s_mov_b32 [[OFFSET0:s[0-9]+]], 0x13480{{$}}
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; GCN-NOHSA: buffer_store_dwordx4 ; GCN-NOHSA: buffer_store_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @smrd_valu_ci_offset_x16(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(2)* %in, <16 x i32> %c) #1 { define amdgpu_kernel void @smrd_valu_ci_offset_x16(<16 x i32> addrspace(1)* %out, <16 x i32> addrspace(4)* %in, <16 x i32> %c) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %in, i32 %tmp %tmp2 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %in, i32 %tmp
%tmp3 = getelementptr <16 x i32>, <16 x i32> addrspace(2)* %tmp2, i32 1234 %tmp3 = getelementptr <16 x i32>, <16 x i32> addrspace(4)* %tmp2, i32 1234
%tmp4 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp3 %tmp4 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp3
%tmp5 = or <16 x i32> %tmp4, %c %tmp5 = or <16 x i32> %tmp4, %c
store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_valu2_salu_user: ; GCN-LABEL: {{^}}smrd_valu2_salu_user:
; GCN-NOHSA: buffer_load_dword [[MOVED:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}} ; GCN-NOHSA: buffer_load_dword [[MOVED:v[0-9]+]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:16{{$}}
; GCN-HSA: flat_load_dword [[MOVED:v[0-9]+]], v[{{[0-9+:[0-9]+}}] ; GCN-HSA: flat_load_dword [[MOVED:v[0-9]+]], v[{{[0-9+:[0-9]+}}]
; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]] ; GCN: v_add_i32_e32 [[ADD:v[0-9]+]], vcc, s{{[0-9]+}}, [[MOVED]]
; GCN-NOHSA: buffer_store_dword [[ADD]] ; GCN-NOHSA: buffer_store_dword [[ADD]]
; GCN-HSA: flat_store_dword {{.*}}, [[ADD]] ; GCN-HSA: flat_store_dword {{.*}}, [[ADD]]
define amdgpu_kernel void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(2)* %in, i32 %a) #1 { define amdgpu_kernel void @smrd_valu2_salu_user(i32 addrspace(1)* %out, [8 x i32] addrspace(4)* %in, i32 %a) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = add i32 %tmp, 4 %tmp1 = add i32 %tmp, 4
%tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(2)* %in, i32 %tmp, i32 4 %tmp2 = getelementptr [8 x i32], [8 x i32] addrspace(4)* %in, i32 %tmp, i32 4
%tmp3 = load i32, i32 addrspace(2)* %tmp2 %tmp3 = load i32, i32 addrspace(4)* %tmp2
%tmp4 = add i32 %tmp3, %a %tmp4 = add i32 %tmp3, %a
store i32 %tmp4, i32 addrspace(1)* %out store i32 %tmp4, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset: ; GCN-LABEL: {{^}}smrd_valu2_max_smrd_offset:
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}} ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1020{{$}}
; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}} ; GCN-HSA flat_load_dword v{{[0-9]}}, v{{[0-9]+:[0-9]+}}
define amdgpu_kernel void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 { define amdgpu_kernel void @smrd_valu2_max_smrd_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = add i32 %tmp, 4 %tmp1 = add i32 %tmp, 4
%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 255 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(4)* %in, i32 %tmp, i32 255
%tmp3 = load i32, i32 addrspace(2)* %tmp2 %tmp3 = load i32, i32 addrspace(4)* %tmp2
store i32 %tmp3, i32 addrspace(1)* %out store i32 %tmp3, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset: ; GCN-LABEL: {{^}}smrd_valu2_mubuf_offset:
; GCN-NOHSA-NOT: v_add ; GCN-NOHSA-NOT: v_add
; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1024{{$}} ; GCN-NOHSA: buffer_load_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 offset:1024{{$}}
; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}] ; GCN-HSA: flat_load_dword v{{[0-9]}}, v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(2)* %in) #1 { define amdgpu_kernel void @smrd_valu2_mubuf_offset(i32 addrspace(1)* %out, [1024 x i32] addrspace(4)* %in) #1 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = add i32 %tmp, 4 %tmp1 = add i32 %tmp, 4
%tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(2)* %in, i32 %tmp, i32 256 %tmp2 = getelementptr [1024 x i32], [1024 x i32] addrspace(4)* %in, i32 %tmp, i32 256
%tmp3 = load i32, i32 addrspace(2)* %tmp2 %tmp3 = load i32, i32 addrspace(4)* %tmp2
store i32 %tmp3, i32 addrspace(1)* %out store i32 %tmp3, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_load_imm_v8i32: ; GCN-LABEL: {{^}}s_load_imm_v8i32:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
define amdgpu_kernel void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { define amdgpu_kernel void @s_load_imm_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
entry: entry:
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)* %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <8 x i32> addrspace(4)*
%tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4 %tmp3 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp2, align 4
store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32 store <8 x i32> %tmp3, <8 x i32> addrspace(1)* %out, align 32
ret void ret void
} }
; GCN-LABEL: {{^}}s_load_imm_v8i32_salu_user: ; GCN-LABEL: {{^}}s_load_imm_v8i32_salu_user:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: buffer_store_dword ; GCN-NOHSA: buffer_store_dword
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
define amdgpu_kernel void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { define amdgpu_kernel void @s_load_imm_v8i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
entry: entry:
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <8 x i32> addrspace(2)* %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <8 x i32> addrspace(4)*
%tmp3 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp2, align 4 %tmp3 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp2, align 4
%elt0 = extractelement <8 x i32> %tmp3, i32 0 %elt0 = extractelement <8 x i32> %tmp3, i32 0
%elt1 = extractelement <8 x i32> %tmp3, i32 1 %elt1 = extractelement <8 x i32> %tmp3, i32 1
%elt2 = extractelement <8 x i32> %tmp3, i32 2 %elt2 = extractelement <8 x i32> %tmp3, i32 2
%elt3 = extractelement <8 x i32> %tmp3, i32 3 %elt3 = extractelement <8 x i32> %tmp3, i32 3
%elt4 = extractelement <8 x i32> %tmp3, i32 4 %elt4 = extractelement <8 x i32> %tmp3, i32 4
%elt5 = extractelement <8 x i32> %tmp3, i32 5 %elt5 = extractelement <8 x i32> %tmp3, i32 5
%elt6 = extractelement <8 x i32> %tmp3, i32 6 %elt6 = extractelement <8 x i32> %tmp3, i32 6
Show All 15 Lines
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
define amdgpu_kernel void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { define amdgpu_kernel void @s_load_imm_v16i32(<16 x i32> addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
entry: entry:
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)* %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <16 x i32> addrspace(4)*
%tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4 %tmp3 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp2, align 4
store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32 store <16 x i32> %tmp3, <16 x i32> addrspace(1)* %out, align 32
ret void ret void
} }
; GCN-LABEL: {{^}}s_load_imm_v16i32_salu_user: ; GCN-LABEL: {{^}}s_load_imm_v16i32_salu_user:
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
; GCN-NOHSA: buffer_load_dwordx4 ; GCN-NOHSA: buffer_load_dwordx4
Show All 13 Lines
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: v_add_i32_e32 ; GCN-NOHSA: v_add_i32_e32
; GCN-NOHSA: buffer_store_dword ; GCN-NOHSA: buffer_store_dword
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
; GCN-HSA: flat_load_dwordx4 ; GCN-HSA: flat_load_dwordx4
define amdgpu_kernel void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(2)* nocapture readonly %in) #1 { define amdgpu_kernel void @s_load_imm_v16i32_salu_user(i32 addrspace(1)* %out, i32 addrspace(4)* nocapture readonly %in) #1 {
entry: entry:
%tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp0 = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = getelementptr inbounds i32, i32 addrspace(2)* %in, i32 %tmp0 %tmp1 = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tmp0
%tmp2 = bitcast i32 addrspace(2)* %tmp1 to <16 x i32> addrspace(2)* %tmp2 = bitcast i32 addrspace(4)* %tmp1 to <16 x i32> addrspace(4)*
%tmp3 = load <16 x i32>, <16 x i32> addrspace(2)* %tmp2, align 4 %tmp3 = load <16 x i32>, <16 x i32> addrspace(4)* %tmp2, align 4
%elt0 = extractelement <16 x i32> %tmp3, i32 0 %elt0 = extractelement <16 x i32> %tmp3, i32 0
%elt1 = extractelement <16 x i32> %tmp3, i32 1 %elt1 = extractelement <16 x i32> %tmp3, i32 1
%elt2 = extractelement <16 x i32> %tmp3, i32 2 %elt2 = extractelement <16 x i32> %tmp3, i32 2
%elt3 = extractelement <16 x i32> %tmp3, i32 3 %elt3 = extractelement <16 x i32> %tmp3, i32 3
%elt4 = extractelement <16 x i32> %tmp3, i32 4 %elt4 = extractelement <16 x i32> %tmp3, i32 4
%elt5 = extractelement <16 x i32> %tmp3, i32 5 %elt5 = extractelement <16 x i32> %tmp3, i32 5
%elt6 = extractelement <16 x i32> %tmp3, i32 6 %elt6 = extractelement <16 x i32> %tmp3, i32 6
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/sched-crash-dbg-value.mir

Show All 9 Lines--- |
%struct.wombat.1 = type { [4 x i32], [4 x i32], [4 x i32], [4 x i32], i32, i32, i32, i32 } %struct.wombat.1 = type { [4 x i32], [4 x i32], [4 x i32], [4 x i32], i32, i32, i32, i32 }
@sched_dbg_value_crash.tmp6 = internal unnamed_addr addrspace(3) global [256 x [16 x i8]] undef, align 16 @sched_dbg_value_crash.tmp6 = internal unnamed_addr addrspace(3) global [256 x [16 x i8]] undef, align 16
define amdgpu_kernel void @sched_dbg_value_crash(i8 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture readonly %arg1, %struct.widget.0 addrspace(1)* nocapture readonly %arg2, %struct.baz addrspace(1)* nocapture readonly %arg3, %struct.snork addrspace(1)* nocapture %arg4) local_unnamed_addr #2 { define amdgpu_kernel void @sched_dbg_value_crash(i8 addrspace(1)* nocapture readonly %arg, i32 addrspace(1)* nocapture readonly %arg1, %struct.widget.0 addrspace(1)* nocapture readonly %arg2, %struct.baz addrspace(1)* nocapture readonly %arg3, %struct.snork addrspace(1)* nocapture %arg4) local_unnamed_addr #2 {
bb: bb:
%0 = getelementptr i32, i32 addrspace(1)* %arg1, i64 0, !amdgpu.uniform !3, !amdgpu.noclobber !3 %0 = getelementptr i32, i32 addrspace(1)* %arg1, i64 0, !amdgpu.uniform !3, !amdgpu.noclobber !3
%tmp5 = alloca %struct.wombat, align 16, addrspace(5) %tmp5 = alloca %struct.wombat, align 16, addrspace(5)
%1 = call noalias nonnull dereferenceable(64) i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %1 = call noalias nonnull dereferenceable(64) i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%2 = bitcast i8 addrspace(2)* %1 to i32 addrspace(2)* %2 = bitcast i8 addrspace(4)* %1 to i32 addrspace(4)*
%3 = getelementptr inbounds i32, i32 addrspace(2)* %2, i64 1 %3 = getelementptr inbounds i32, i32 addrspace(4)* %2, i64 1
%4 = bitcast i32 addrspace(2)* %3 to <2 x i32> addrspace(2)*, !amdgpu.uniform !3, !amdgpu.noclobber !3 %4 = bitcast i32 addrspace(4)* %3 to <2 x i32> addrspace(4)*, !amdgpu.uniform !3, !amdgpu.noclobber !3
%5 = load <2 x i32>, <2 x i32> addrspace(2)* %4, align 4, !invariant.load !3 %5 = load <2 x i32>, <2 x i32> addrspace(4)* %4, align 4, !invariant.load !3
%6 = extractelement <2 x i32> %5, i32 0 %6 = extractelement <2 x i32> %5, i32 0
%7 = extractelement <2 x i32> %5, i32 1 %7 = extractelement <2 x i32> %5, i32 1
%8 = lshr i32 %6, 16 %8 = lshr i32 %6, 16
%9 = call i32 @llvm.amdgcn.workitem.id.x(), !range !4 %9 = call i32 @llvm.amdgcn.workitem.id.x(), !range !4
%10 = call i32 @llvm.amdgcn.workitem.id.y(), !range !4 %10 = call i32 @llvm.amdgcn.workitem.id.y(), !range !4
%11 = call i32 @llvm.amdgcn.workitem.id.z(), !range !4 %11 = call i32 @llvm.amdgcn.workitem.id.z(), !range !4
%12 = mul nuw nsw i32 %8, %7 %12 = mul nuw nsw i32 %8, %7
%13 = mul i32 %12, %9 %13 = mul i32 %12, %9
%14 = mul nuw nsw i32 %10, %7 %14 = mul nuw nsw i32 %10, %7
%15 = add i32 %13, %14 %15 = add i32 %13, %14
%16 = add i32 %15, %11 %16 = add i32 %15, %11
%17 = getelementptr inbounds [256 x [16 x i8]], [256 x [16 x i8]] addrspace(3)* @sched_dbg_value_crash.tmp6, i32 0, i32 %16 %17 = getelementptr inbounds [256 x [16 x i8]], [256 x [16 x i8]] addrspace(3)* @sched_dbg_value_crash.tmp6, i32 0, i32 %16
%tmp7 = load i64, i64 addrspace(2)* null, align 536870912 %tmp7 = load i64, i64 addrspace(4)* null, align 536870912
%tmp8 = tail call i32 @llvm.amdgcn.workitem.id.x() #3, !range !4 %tmp8 = tail call i32 @llvm.amdgcn.workitem.id.x() #3, !range !4
%tmp9 = zext i32 %tmp8 to i64 %tmp9 = zext i32 %tmp8 to i64
%tmp10 = add i64 %tmp7, %tmp9 %tmp10 = add i64 %tmp7, %tmp9
%tmp11 = shl i64 %tmp10, 32 %tmp11 = shl i64 %tmp10, 32
%tmp12 = ashr exact i64 %tmp11, 32 %tmp12 = ashr exact i64 %tmp11, 32
%tmp13 = getelementptr inbounds %struct.widget.0, %struct.widget.0 addrspace(1)* %arg2, i64 %tmp12, i32 1 %tmp13 = getelementptr inbounds %struct.widget.0, %struct.widget.0 addrspace(1)* %arg2, i64 %tmp12, i32 1
%tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4 %tmp14 = load i32, i32 addrspace(1)* %tmp13, align 4
%tmp15 = getelementptr inbounds %struct.baz, %struct.baz addrspace(1)* %arg3, i64 %tmp12, i32 1 %tmp15 = getelementptr inbounds %struct.baz, %struct.baz addrspace(1)* %arg3, i64 %tmp12, i32 1
▲ Show 20 Lines • Show All 92 Lines • ▼ Show 20 Lines--- |
declare void @func(float, i64, i16 addrspace(5)*) declare void @func(float, i64, i16 addrspace(5)*)
declare void @llvm.lifetime.start.p5i8(i64, i8 addrspace(5)* nocapture) #0 declare void @llvm.lifetime.start.p5i8(i64, i8 addrspace(5)* nocapture) #0
declare float @llvm.fmuladd.f32(float, float, float) #1 declare float @llvm.fmuladd.f32(float, float, float) #1
declare void @llvm.lifetime.end.p5i8(i64, i8 addrspace(5)* nocapture) #0 declare void @llvm.lifetime.end.p5i8(i64, i8 addrspace(5)* nocapture) #0
declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1 declare <2 x float> @llvm.fmuladd.v2f32(<2 x float>, <2 x float>, <2 x float>) #1
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare void @llvm.dbg.value(metadata, metadata, metadata) #1 declare void @llvm.dbg.value(metadata, metadata, metadata) #1
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #1
declare i32 @llvm.amdgcn.workitem.id.y() #1 declare i32 @llvm.amdgcn.workitem.id.y() #1
declare i32 @llvm.amdgcn.workitem.id.z() #1 declare i32 @llvm.amdgcn.workitem.id.z() #1
declare void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i32, i1) #0 declare void @llvm.memcpy.p1i8.p5i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(5)* nocapture readonly, i64, i32, i1) #0
declare void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(3)* nocapture readonly, i64, i32, i1) #0 declare void @llvm.memcpy.p1i8.p3i8.i64(i8 addrspace(1)* nocapture writeonly, i8 addrspace(3)* nocapture readonly, i64, i32, i1) #0
attributes #0 = { argmemonly nounwind } attributes #0 = { argmemonly nounwind }
attributes #1 = { nounwind readnone speculatable } attributes #1 = { nounwind readnone speculatable }
attributes #2 = { convergent nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-scratch" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="gfx900" "target-features"="+fp32-denormals" } attributes #2 = { convergent nounwind "amdgpu-dispatch-ptr" "amdgpu-flat-scratch" "amdgpu-work-item-id-y" "amdgpu-work-item-id-z" "target-cpu"="gfx900" "target-features"="+fp32-denormals" }
▲ Show 20 Lines • Show All 41 Lines • ▼ Show 20 Linesbody: |
bb.0.bb: bb.0.bb:
liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr32, $sgpr101 liveins: $vgpr0, $vgpr1, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr32, $sgpr101
%4:sgpr_64 = COPY $sgpr6_sgpr7 %4:sgpr_64 = COPY $sgpr6_sgpr7
%3:sgpr_64 = COPY $sgpr4_sgpr5 %3:sgpr_64 = COPY $sgpr4_sgpr5
%2:vgpr_32 = COPY $vgpr2 %2:vgpr_32 = COPY $vgpr2
%1:vgpr_32 = COPY $vgpr1 %1:vgpr_32 = COPY $vgpr1
%0:vgpr_32 = COPY $vgpr0 %0:vgpr_32 = COPY $vgpr0
%5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) %5:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 0, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%6:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) %6:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 8, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%7:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 16, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(2)* undef`) %7:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 16, 0 :: (non-temporal dereferenceable invariant load 8 from `i64 addrspace(4)* undef`)
%8:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 24, 0 %8:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 24, 0
%9:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 32, 0 %9:sreg_64_xexec = S_LOAD_DWORDX2_IMM %4, 32, 0
%10:sreg_64_xexec = S_LOAD_DWORDX2_IMM %3, 4, 0 %10:sreg_64_xexec = S_LOAD_DWORDX2_IMM %3, 4, 0
%11:sreg_32_xm0 = S_LSHR_B32 %10.sub0, 16, implicit-def dead $scc %11:sreg_32_xm0 = S_LSHR_B32 %10.sub0, 16, implicit-def dead $scc
%12:sreg_32_xm0 = S_MUL_I32 %11, %10.sub1 %12:sreg_32_xm0 = S_MUL_I32 %11, %10.sub1
%13:vgpr_32 = V_MUL_LO_I32 0, %0, implicit $exec %13:vgpr_32 = V_MUL_LO_I32 0, %0, implicit $exec
%14:vgpr_32 = V_MUL_LO_I32 %1, %10.sub1, implicit $exec %14:vgpr_32 = V_MUL_LO_I32 %1, %10.sub1, implicit $exec
%15:vgpr_32 = V_ADD_I32_e32 0, %13, implicit-def dead $vcc, implicit $exec %15:vgpr_32 = V_ADD_I32_e32 0, %13, implicit-def dead $vcc, implicit $exec
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/scripts/chaddr.sh

#!/bin/bash #!/bin/bash
# #
# script to convert a lit test from old address space mapping # script to convert a lit test from old address space mapping
# to new address space mapping for AMDGPU. # to new address space mapping for AMDGPU.
# #
# addr space change: # addr space change:
# 0 -> 5 # 2 -> 4
# 4 -> 0 # 4 -> 2
# #
if [[ $# -ne 2 ]]; then if [[ $# -ne 2 ]]; then
echo "Convert a lite test from old address space mapping to new address space mapping for AMDGPU" echo "Convert a lite test from old address space mapping to new address space mapping for AMDGPU"
echo "Usage: chaddr.sh file newfile" echo "Usage: chaddr.sh file newfile"
exit exit
fi fi
set -x set -x
file=$1 file=$1
newf=$2 newf=$2
if grep amdgiz $file >/dev/null; then
exit
fi
has_amdgcn=0
if grep 'triple *[= "]*amdgcn' $file >/dev/null; then
has_amdgcn=1
elif grep 'arch=amdgcn' $file >/dev/null; then
has_amdgcn=1
fi
has_r600=0
if grep 'triple *[= "]*r600' $file >/dev/null; then
has_r600=1
elif grep 'arch=r600' $file >/dev/null; then
has_r600=1
fi
if [[ $has_amdgcn == 0 && $has_r600 == 0 ]] ; then
exit
fi
cp $file $newf cp $file $newf
sed -i \ sed -i \
-e 's: addrspace(5) *\*: addrspace(x)*:g' \ -e 's: addrspace(4): addrspace(x):g' \
$newf $newf
sed -i \ sed -i \
-e 's:\([a-zA-Z0-9_>][a-zA-Z0-9_>]* *\)\*:\1 addrspace(5)*:g' \ -e 's: addrspace(2): addrspace(4):g' \
-e 's:\(\[[0-9][0-9]* x .*\]\)\*:\1 addrspace(5)*:g' \
-e 's:\({ [a-zA-Z0-9][a-zA-Z0-9, ]* }\)\*:\1 addrspace(5)*:g' \
-e 's: \(addrspace(.)\*\)\*: \1 addrspace(5)*:g' \
-e 's:\(([a-zA-Z0-9_, ]*) *\* *\)\*:\1 addrspace(5)*:g' \
-e 's: addrspace(4) *\*:*:g' \
-e 's: addrspace(0) *\*: addrspace(5)*:g' \
-e 's: = alloca \(.*\): = alloca \1, addrspace(5):g' \
-e 's:\(;.*alloca [^,]*, \)\(addrspace(5)\):\1align {{.*}}, \2:g' \
-e 's:\(target datalayout =.*[^5]\)":\1-A5":g' \
-e 's:\(llvm\..*\.\)p0i\([1-8][1-8]*\):\1p5i\2:g' \
-e 's:\(llvm\..*\.\)p4i\([1-8][1-8]*\):\1p0i\2:g' \
-e 's:\(@_Z[^P][^P]*\)P\([^U][^U]*\):\1PU3AS5\2:g' \
-e 's:\(@_Z[^P][^P]*\)PU3AS4:\1P:g' \
-e '/INT/s: addrspace(5)\*:*:g' \
-e '/SET/s: addrspace(5)\*:*:g' \
-e '/MOV/s: addrspace(5)\*:*:g' \
-e '/SH/s: addrspace(5)\*:*:g' \
-e '/MUL/s: addrspace(5)\*:*:g' \
-e '/LDS/s: addrspace(5)\*:*:g' \
-e '/IEEE/s: addrspace(5)\*:*:g' \
-e '/DOT/s: addrspace(5)\*:*:g' \
-e '/^ *;.*: *[A-Z][A-Z][A-Z]/s: addrspace(5)\*:*:g' \
$newf $newf
sed -i \ sed -i \
-e 's: addrspace(x) *\*: addrspace(4)*:g' \ -e 's: addrspace(x): addrspace(2):g' \
$newf $newf
## add missing datalayout
if [[ $file == *.ll ]] && grep '; *RUN: *opt ' $file >/dev/null && ! grep datalayout $file >/dev/null; then
sed -i 's:opt:opt -data-layout=A5:' $file
fi

test/CodeGen/AMDGPU/sext-in-reg.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x10000 ; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x10000
; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]] ; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
; SI: buffer_store_short [[VBFE]] ; SI: buffer_store_short [[VBFE]]
; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15 ; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15
; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}} ; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15 ; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 15
define amdgpu_kernel void @s_sext_in_reg_i1_i16(i16 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @s_sext_in_reg_i1_i16(i16 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
%ld = load i32, i32 addrspace(2)* %ptr %ld = load i32, i32 addrspace(4)* %ptr
%in = trunc i32 %ld to i16 %in = trunc i32 %ld to i16
%shl = shl i16 %in, 15 %shl = shl i16 %in, 15
%sext = ashr i16 %shl, 15 %sext = ashr i16 %shl, 15
store i16 %sext, i16 addrspace(1)* %out store i16 %sext, i16 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}s_sext_in_reg_i2_i16: ; FUNC-LABEL: {{^}}s_sext_in_reg_i2_i16:
; GCN: s_load_dword [[VAL:s[0-9]+]] ; GCN: s_load_dword [[VAL:s[0-9]+]]
; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000 ; SI: s_bfe_i32 [[BFE:s[0-9]+]], [[VAL]], 0x20000
; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]] ; SI: v_mov_b32_e32 [[VBFE:v[0-9]+]], [[BFE]]
; SI: buffer_store_short [[VBFE]] ; SI: buffer_store_short [[VBFE]]
; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14 ; GFX89: s_lshl_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14
; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}} ; GFX89: s_sext_i32_i16 s{{[0-9]+}}, s{{[0-9]+}}
; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14 ; GFX89: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 14
define amdgpu_kernel void @s_sext_in_reg_i2_i16(i16 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @s_sext_in_reg_i2_i16(i16 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
%ld = load i32, i32 addrspace(2)* %ptr %ld = load i32, i32 addrspace(4)* %ptr
%in = trunc i32 %ld to i16 %in = trunc i32 %ld to i16
%shl = shl i16 %in, 14 %shl = shl i16 %in, 14
%sext = ashr i16 %shl, 14 %sext = ashr i16 %shl, 14
store i16 %sext, i16 addrspace(1)* %out store i16 %sext, i16 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16: ; FUNC-LABEL: {{^}}v_sext_in_reg_i1_i16:
▲ Show 20 Lines • Show All 92 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/sgpr-copy.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}phi1: ; CHECK-LABEL: {{^}}phi1:
; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0 ; CHECK: s_buffer_load_dword [[DST:s[0-9]]], {{s\[[0-9]+:[0-9]+\]}}, 0x0
; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]] ; CHECK: v_mov_b32_e32 v{{[0-9]}}, [[DST]]
define amdgpu_ps void @phi1(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @phi1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0)
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16) %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16)
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32) %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32)
%tmp24 = fptosi float %tmp22 to i32 %tmp24 = fptosi float %tmp22 to i32
%tmp25 = icmp ne i32 %tmp24, 0 %tmp25 = icmp ne i32 %tmp24, 0
br i1 %tmp25, label %ENDIF, label %ELSE br i1 %tmp25, label %ENDIF, label %ELSE
ELSE: ; preds = %main_body ELSE: ; preds = %main_body
%tmp26 = fsub float -0.000000e+00, %tmp21 %tmp26 = fsub float -0.000000e+00, %tmp21
br label %ENDIF br label %ENDIF
ENDIF: ; preds = %ELSE, %main_body ENDIF: ; preds = %ELSE, %main_body
%temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ] %temp.0 = phi float [ %tmp26, %ELSE ], [ %tmp21, %main_body ]
%tmp27 = fadd float %temp.0, %tmp23 %tmp27 = fadd float %temp.0, %tmp23
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp27, float %tmp27, float 0.000000e+00, float 1.000000e+00, i1 true, i1 true) #0
ret void ret void
} }
; Make sure this program doesn't crash ; Make sure this program doesn't crash
; CHECK-LABEL: {{^}}phi2: ; CHECK-LABEL: {{^}}phi2:
define amdgpu_ps void @phi2(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 { define amdgpu_ps void @phi2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #1 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16)
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32) %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 32)
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 36) %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 36)
%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 40) %tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 40)
%tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 48) %tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 48)
%tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 52) %tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 52)
%tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 56) %tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 56)
%tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 64) %tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 64)
%tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 68) %tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 68)
%tmp30 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 72) %tmp30 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 72)
%tmp31 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 76) %tmp31 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 76)
%tmp32 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 80) %tmp32 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 80)
%tmp33 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 84) %tmp33 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 84)
%tmp34 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 88) %tmp34 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 88)
%tmp35 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 92) %tmp35 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 92)
%tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0 %tmp36 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %arg2, i32 0
%tmp37 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp36, !tbaa !0 %tmp37 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp36, !tbaa !0
%tmp38 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg1, i32 0 %tmp38 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg1, i32 0
%tmp39 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp38, !tbaa !0 %tmp39 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp38, !tbaa !0
%i.i = extractelement <2 x i32> %arg5, i32 0 %i.i = extractelement <2 x i32> %arg5, i32 0
%j.i = extractelement <2 x i32> %arg5, i32 1 %j.i = extractelement <2 x i32> %arg5, i32 1
%i.f.i = bitcast i32 %i.i to float %i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float %j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #1
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #1
%i.i19 = extractelement <2 x i32> %arg5, i32 0 %i.i19 = extractelement <2 x i32> %arg5, i32 0
%j.i20 = extractelement <2 x i32> %arg5, i32 1 %j.i20 = extractelement <2 x i32> %arg5, i32 1
▲ Show 20 Lines • Show All 106 Lines • ▼ Show 20 LinesENDIF24: ; preds = %IF25, %ENDIF
%tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110) %tmp113 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp108, float %tmp110)
%tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00) %tmp115 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp112, float 1.000000e+00)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp113, <2 x half> %tmp115, i1 true, i1 true) #0
ret void ret void
} }
; We just want ot make sure the program doesn't crash ; We just want ot make sure the program doesn't crash
; CHECK-LABEL: {{^}}loop: ; CHECK-LABEL: {{^}}loop:
define amdgpu_ps void @loop(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @loop(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 0)
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 4) %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 4)
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 8) %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 8)
%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 12) %tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 12)
%tmp25 = fptosi float %tmp24 to i32 %tmp25 = fptosi float %tmp24 to i32
%tmp26 = bitcast i32 %tmp25 to float %tmp26 = bitcast i32 %tmp25 to float
%tmp27 = bitcast float %tmp26 to i32 %tmp27 = bitcast float %tmp26 to i32
br label %LOOP br label %LOOP
Show All 33 Lines
; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_LO:[0-9]+]], 5
; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7 ; CHECK-DAG: v_mov_b32_e32 v[[SAMPLE_HI:[0-9]+]], 7
; CHECK: BB{{[0-9]+_[0-9]+}}: ; CHECK: BB{{[0-9]+_[0-9]+}}:
; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}} ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[SAMPLE_LO]]:[[SAMPLE_HI]]{{\]}}
; CHECK: exp ; CHECK: exp
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(2)* byval %arg, [32 x <4 x i32>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_ps void @sample_v3([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
entry: entry:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i64 0, i32 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0
%tmp21 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 16) %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 16)
%tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 %tmp23 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0
%tmp24 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp23, !tbaa !0 %tmp24 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp23, !tbaa !0
%tmp25 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 0 %tmp25 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0
%tmp26 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp25, !tbaa !0 %tmp26 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp25, !tbaa !0
%tmp27 = fcmp oeq float %tmp22, 0.000000e+00 %tmp27 = fcmp oeq float %tmp22, 0.000000e+00
%tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32> %tmp26.bc = bitcast <4 x i32> %tmp26 to <4 x i32>
br i1 %tmp27, label %if, label %else br i1 %tmp27, label %if, label %else
if: ; preds = %entry if: ; preds = %entry
%tmp1 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 0x36D6000000000000, float 0x36DA000000000000>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) %tmp1 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 0x36D6000000000000, float 0x36DA000000000000>, <8 x i32> %tmp24, <4 x i32> %tmp26.bc, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%val.if.0 = extractelement <4 x float> %tmp1, i32 0 %val.if.0 = extractelement <4 x float> %tmp1, i32 0
%val.if.1 = extractelement <4 x float> %tmp1, i32 1 %val.if.1 = extractelement <4 x float> %tmp1, i32 1
Show All 39 Linesendif: ; preds = %if1, %if0, %entry
%tmp6 = bitcast i32 %tmp5 to float %tmp6 = bitcast i32 %tmp5 to float
store float %tmp6, float addrspace(1)* %out store float %tmp6, float addrspace(1)* %out
ret void ret void
} }
; This test is just checking that we don't crash / assertion fail. ; This test is just checking that we don't crash / assertion fail.
; CHECK-LABEL: {{^}}copy2: ; CHECK-LABEL: {{^}}copy2:
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @copy2([17 x <4 x i32>] addrspace(2)* byval %arg, [32 x <4 x i32>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_ps void @copy2([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
entry: entry:
br label %LOOP68 br label %LOOP68
LOOP68: ; preds = %ENDIF69, %entry LOOP68: ; preds = %ENDIF69, %entry
%temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ] %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
%t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ] %t = phi i32 [ 20, %entry ], [ %x, %ENDIF69 ]
%g = icmp eq i32 0, %t %g = icmp eq i32 0, %t
%l = bitcast float %temp4.7 to i32 %l = bitcast float %temp4.7 to i32
Show All 19 Lines
; CHECK: s_cmp_eq_u32 ; CHECK: s_cmp_eq_u32
; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]] ; CHECK: s_cbranch_scc0 [[END:BB[0-9]+_[0-9]+]]
; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}} ; CHECK: v_add_{{[iu]}}32_e32 v[[ADD:[0-9]+]], vcc, 1, v{{[0-9]+}}
; [[END]]: ; [[END]]:
; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}} ; CHECK: image_sample v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+}}:[[ADD]]{{\]}}
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(2)* byval %arg, [17 x <4 x i32>] addrspace(2)* byval %arg1, [16 x <4 x i32>] addrspace(2)* byval %arg2, [32 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { define amdgpu_ps void @sample_rsrc([6 x <4 x i32>] addrspace(4)* byval %arg, [17 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <4 x i32>] addrspace(4)* byval %arg2, [32 x <8 x i32>] addrspace(4)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
bb: bb:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg1, i32 0, i32 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i32 0, i32 0
%tmp22 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !3 %tmp22 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !3
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp22, i32 16) %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp22, i32 16)
%tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(2)* %arg3, i32 0, i32 0 %tmp25 = getelementptr [32 x <8 x i32>], [32 x <8 x i32>] addrspace(4)* %arg3, i32 0, i32 0
%tmp26 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp25, !tbaa !3 %tmp26 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp25, !tbaa !3
%tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg2, i32 0, i32 0 %tmp27 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(4)* %arg2, i32 0, i32 0
%tmp28 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp27, !tbaa !3 %tmp28 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp27, !tbaa !3
%i.i = extractelement <2 x i32> %arg7, i32 0 %i.i = extractelement <2 x i32> %arg7, i32 0
%j.i = extractelement <2 x i32> %arg7, i32 1 %j.i = extractelement <2 x i32> %arg7, i32 1
%i.f.i = bitcast i32 %i.i to float %i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float %j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #0
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #0
%i.i1 = extractelement <2 x i32> %arg7, i32 0 %i.i1 = extractelement <2 x i32> %arg7, i32 0
%j.i2 = extractelement <2 x i32> %arg7, i32 1 %j.i2 = extractelement <2 x i32> %arg7, i32 1
Show All 31 Linesbb71: ; preds = %bb80, %bb38
%tmp88 = extractelement <4 x float> %tmp72, i32 0 %tmp88 = extractelement <4 x float> %tmp72, i32 0
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp88, float %tmp88, float %tmp88, float %tmp88, i1 true, i1 true) #0
ret void ret void
} }
; Check the resource descriptor is stored in an sgpr. ; Check the resource descriptor is stored in an sgpr.
; CHECK-LABEL: {{^}}mimg_srsrc_sgpr: ; CHECK-LABEL: {{^}}mimg_srsrc_sgpr:
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { define amdgpu_ps void @mimg_srsrc_sgpr([34 x <8 x i32>] addrspace(4)* byval %arg) #0 {
bb: bb:
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i32 0, i32 %tid %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(4)* %arg, i32 0, i32 %tid
%tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0 %tmp8 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp7, align 32, !tbaa !0
%tmp = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 7.500000e-01, float 2.500000e-01>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) %tmp = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 7.500000e-01, float 2.500000e-01>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp10 = extractelement <4 x float> %tmp, i32 0 %tmp10 = extractelement <4 x float> %tmp, i32 0
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10) %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float undef, float %tmp10)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
ret void ret void
} }
; Check the sampler is stored in an sgpr. ; Check the sampler is stored in an sgpr.
; CHECK-LABEL: {{^}}mimg_ssamp_sgpr: ; CHECK-LABEL: {{^}}mimg_ssamp_sgpr:
; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 ; CHECK: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(2)* byval %arg) #0 { define amdgpu_ps void @mimg_ssamp_sgpr([17 x <4 x i32>] addrspace(4)* byval %arg) #0 {
bb: bb:
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i32 0, i32 %tid %tmp7 = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i32 0, i32 %tid
%tmp8 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp7, align 16, !tbaa !0 %tmp8 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp7, align 16, !tbaa !0
%tmp = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 7.500000e-01, float 2.500000e-01>, <8 x i32> undef, <4 x i32> %tmp8, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) %tmp = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float 7.500000e-01, float 2.500000e-01>, <8 x i32> undef, <4 x i32> %tmp8, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp10 = extractelement <4 x float> %tmp, i32 0 %tmp10 = extractelement <4 x float> %tmp, i32 0
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
ret void ret void
} }
declare float @llvm.fabs.f32(float) #1 declare float @llvm.fabs.f32(float) #1
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test/CodeGen/AMDGPU/si-lod-bias.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; This shader has the potential to generated illegal VGPR to SGPR copies if ; This shader has the potential to generated illegal VGPR to SGPR copies if
; the wrong register class is used for the REG_SEQUENCE instructions. ; the wrong register class is used for the REG_SEQUENCE instructions.
; GCN-LABEL: {{^}}main: ; GCN-LABEL: {{^}}main:
; GCN: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf ; GCN: image_sample_b v{{\[[0-9]:[0-9]\]}}, v{{\[[0-9]:[0-9]\]}}, s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0xf
define amdgpu_ps void @main(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <8 x i32> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @main(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <8 x i32> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16)
%tmp22 = getelementptr <8 x i32>, <8 x i32> addrspace(2)* %arg2, i32 0 %tmp22 = getelementptr <8 x i32>, <8 x i32> addrspace(4)* %arg2, i32 0
%tmp23 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp22, !tbaa !0 %tmp23 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp22, !tbaa !0
%tmp24 = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg1, i32 0 %tmp24 = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg1, i32 0
%tmp25 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp24, !tbaa !0 %tmp25 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp24, !tbaa !0
%i.i = extractelement <2 x i32> %arg5, i32 0 %i.i = extractelement <2 x i32> %arg5, i32 0
%j.i = extractelement <2 x i32> %arg5, i32 1 %j.i = extractelement <2 x i32> %arg5, i32 1
%i.f.i = bitcast i32 %i.i to float %i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float %j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #0 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg3) #0
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #0 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg3) #0
%i.i1 = extractelement <2 x i32> %arg5, i32 0 %i.i1 = extractelement <2 x i32> %arg5, i32 0
%j.i2 = extractelement <2 x i32> %arg5, i32 1 %j.i2 = extractelement <2 x i32> %arg5, i32 1
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test/CodeGen/AMDGPU/si-scheduler.ll

Show All 10 Lines
; CHECK: s_wqm ; CHECK: s_wqm
; CHECK: s_load_dwordx4 ; CHECK: s_load_dwordx4
; CHECK: s_load_dwordx8 ; CHECK: s_load_dwordx8
; CHECK: s_waitcnt lgkmcnt(0) ; CHECK: s_waitcnt lgkmcnt(0)
; CHECK: image_sample ; CHECK: image_sample
; CHECK: s_waitcnt vmcnt(0) ; CHECK: s_waitcnt vmcnt(0)
; CHECK: exp ; CHECK: exp
; CHECK: s_endpgm ; CHECK: s_endpgm
define amdgpu_ps void @main([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 { define amdgpu_ps void @main([6 x <16 x i8>] addrspace(4)* byval %arg, [17 x <16 x i8>] addrspace(4)* byval %arg1, [17 x <4 x i32>] addrspace(4)* byval %arg2, [34 x <8 x i32>] addrspace(4)* byval %arg3, float inreg %arg4, i32 inreg %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <2 x i32> %arg8, <3 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, <2 x i32> %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, i32 %arg19, float %arg20, float %arg21) #0 {
main_body: main_body:
%tmp = bitcast [34 x <8 x i32>] addrspace(2)* %arg3 to <32 x i8> addrspace(2)* %tmp = bitcast [34 x <8 x i32>] addrspace(4)* %arg3 to <32 x i8> addrspace(4)*
%tmp22 = load <32 x i8>, <32 x i8> addrspace(2)* %tmp, align 32, !tbaa !0 %tmp22 = load <32 x i8>, <32 x i8> addrspace(4)* %tmp, align 32, !tbaa !0
%tmp23 = bitcast [17 x <4 x i32>] addrspace(2)* %arg2 to <16 x i8> addrspace(2)* %tmp23 = bitcast [17 x <4 x i32>] addrspace(4)* %arg2 to <16 x i8> addrspace(4)*
%tmp24 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp23, align 16, !tbaa !0 %tmp24 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp23, align 16, !tbaa !0
%i.i = extractelement <2 x i32> %arg11, i32 0 %i.i = extractelement <2 x i32> %arg11, i32 0
%j.i = extractelement <2 x i32> %arg11, i32 1 %j.i = extractelement <2 x i32> %arg11, i32 1
%i.f.i = bitcast i32 %i.i to float %i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float %j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #1 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg5) #1
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #1 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg5) #1
%i.i1 = extractelement <2 x i32> %arg11, i32 0 %i.i1 = extractelement <2 x i32> %arg11, i32 0
%j.i2 = extractelement <2 x i32> %arg11, i32 1 %j.i2 = extractelement <2 x i32> %arg11, i32 1
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test/CodeGen/AMDGPU/si-sgpr-spill.ll

Show All 18 Lines
; Make sure scratch space isn't being used for SGPR->VGPR spills ; Make sure scratch space isn't being used for SGPR->VGPR spills
; Writing to M0 from an SMRD instruction will hang the GPU. ; Writing to M0 from an SMRD instruction will hang the GPU.
; GCN-NOT: s_buffer_load_dword m0 ; GCN-NOT: s_buffer_load_dword m0
; GCN: s_endpgm ; GCN: s_endpgm
; TOVGPR: ScratchSize: 0{{$}} ; TOVGPR: ScratchSize: 0{{$}}
define amdgpu_ps void @main([17 x <4 x i32>] addrspace(2)* byval %arg, [32 x <4 x i32>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) { define amdgpu_ps void @main([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) {
main_body: main_body:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i64 0, i32 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0
%tmp21 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 96) %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 96)
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 100) %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 100)
%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 104) %tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 104)
%tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 112) %tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 112)
%tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 116) %tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 116)
%tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 120) %tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 120)
%tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 128) %tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 128)
%tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 132) %tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 132)
Show All 22 Lines
%tmp52 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 296) %tmp52 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 296)
%tmp53 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 304) %tmp53 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 304)
%tmp54 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 308) %tmp54 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 308)
%tmp55 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 312) %tmp55 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 312)
%tmp56 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 368) %tmp56 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 368)
%tmp57 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 372) %tmp57 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 372)
%tmp58 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 376) %tmp58 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 376)
%tmp59 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 384) %tmp59 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 384)
%tmp60 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 %tmp60 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0
%tmp61 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp60, !tbaa !0 %tmp61 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp60, !tbaa !0
%tmp62 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 0 %tmp62 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0
%tmp63 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp62, !tbaa !0 %tmp63 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp62, !tbaa !0
%tmp63.bc = bitcast <4 x i32> %tmp63 to <4 x i32> %tmp63.bc = bitcast <4 x i32> %tmp63 to <4 x i32>
%tmp64 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 1 %tmp64 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 1
%tmp65 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp64, !tbaa !0 %tmp65 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp64, !tbaa !0
%tmp66 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 1 %tmp66 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 1
%tmp67 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp66, !tbaa !0 %tmp67 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp66, !tbaa !0
%tmp68 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 2 %tmp68 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 2
%tmp69 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp68, !tbaa !0 %tmp69 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp68, !tbaa !0
%tmp70 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 2 %tmp70 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 2
%tmp71 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp70, !tbaa !0 %tmp71 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp70, !tbaa !0
%tmp72 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 3 %tmp72 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 3
%tmp73 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp72, !tbaa !0 %tmp73 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp72, !tbaa !0
%tmp74 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 3 %tmp74 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 3
%tmp75 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp74, !tbaa !0 %tmp75 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp74, !tbaa !0
%tmp76 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 4 %tmp76 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 4
%tmp77 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp76, !tbaa !0 %tmp77 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp76, !tbaa !0
%tmp78 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 4 %tmp78 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 4
%tmp79 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp78, !tbaa !0 %tmp79 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp78, !tbaa !0
%tmp80 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 5 %tmp80 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 5
%tmp81 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp80, !tbaa !0 %tmp81 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp80, !tbaa !0
%tmp82 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 5 %tmp82 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 5
%tmp83 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp82, !tbaa !0 %tmp83 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp82, !tbaa !0
%tmp84 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 6 %tmp84 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 6
%tmp85 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp84, !tbaa !0 %tmp85 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp84, !tbaa !0
%tmp86 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 6 %tmp86 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 6
%tmp87 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp86, !tbaa !0 %tmp87 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp86, !tbaa !0
%tmp88 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 7 %tmp88 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 7
%tmp89 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp88, !tbaa !0 %tmp89 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp88, !tbaa !0
%tmp90 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 7 %tmp90 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 7
%tmp91 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp90, !tbaa !0 %tmp91 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp90, !tbaa !0
%i.i = extractelement <2 x i32> %arg6, i32 0 %i.i = extractelement <2 x i32> %arg6, i32 0
%j.i = extractelement <2 x i32> %arg6, i32 1 %j.i = extractelement <2 x i32> %arg6, i32 1
%i.f.i = bitcast i32 %i.i to float %i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float %j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0
%i.i91 = extractelement <2 x i32> %arg6, i32 0 %i.i91 = extractelement <2 x i32> %arg6, i32 0
%j.i92 = extractelement <2 x i32> %arg6, i32 1 %j.i92 = extractelement <2 x i32> %arg6, i32 1
▲ Show 20 Lines • Show All 184 Lines • ▼ Show 20 Lines
%tmp609 = fadd float %temp24.1, 1.000000e+00 %tmp609 = fadd float %temp24.1, 1.000000e+00
%tmp610 = fmul float %temp32.0, 5.000000e-01 %tmp610 = fmul float %temp32.0, 5.000000e-01
br label %LOOP65 br label %LOOP65
} }
; GCN-LABEL: {{^}}main1: ; GCN-LABEL: {{^}}main1:
; GCN: s_endpgm ; GCN: s_endpgm
; TOVGPR: ScratchSize: 0{{$}} ; TOVGPR: ScratchSize: 0{{$}}
define amdgpu_ps void @main1([17 x <4 x i32>] addrspace(2)* byval %arg, [32 x <4 x i32>] addrspace(2)* byval %arg1, [16 x <8 x i32>] addrspace(2)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 { define amdgpu_ps void @main1([17 x <4 x i32>] addrspace(4)* byval %arg, [32 x <4 x i32>] addrspace(4)* byval %arg1, [16 x <8 x i32>] addrspace(4)* byval %arg2, float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, <2 x i32> %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19, float %arg20) #0 {
main_body: main_body:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg, i64 0, i32 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg, i64 0, i32 0
%tmp21 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, !tbaa !0 %tmp21 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, !tbaa !0
%tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 0) %tmp22 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 0)
%tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 4) %tmp23 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 4)
%tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 8) %tmp24 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 8)
%tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 12) %tmp25 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 12)
%tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 28) %tmp26 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 28)
%tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 48) %tmp27 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 48)
%tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 52) %tmp28 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 52)
%tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 56) %tmp29 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 56)
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%tmp117 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 696) %tmp117 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 696)
%tmp118 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 700) %tmp118 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 700)
%tmp119 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 704) %tmp119 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 704)
%tmp120 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 708) %tmp120 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 708)
%tmp121 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 712) %tmp121 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 712)
%tmp122 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 716) %tmp122 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 716)
%tmp123 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 864) %tmp123 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 864)
%tmp124 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 868) %tmp124 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp21, i32 868)
%tmp125 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 0 %tmp125 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 0
%tmp126 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp125, !tbaa !0 %tmp126 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp125, !tbaa !0
%tmp127 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 0 %tmp127 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 0
%tmp128 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp127, !tbaa !0 %tmp128 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp127, !tbaa !0
%tmp129 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 1 %tmp129 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 1
%tmp130 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp129, !tbaa !0 %tmp130 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp129, !tbaa !0
%tmp131 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 1 %tmp131 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 1
%tmp132 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp131, !tbaa !0 %tmp132 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp131, !tbaa !0
%tmp133 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 2 %tmp133 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 2
%tmp134 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp133, !tbaa !0 %tmp134 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp133, !tbaa !0
%tmp135 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 2 %tmp135 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 2
%tmp136 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp135, !tbaa !0 %tmp136 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp135, !tbaa !0
%tmp137 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 3 %tmp137 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 3
%tmp138 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp137, !tbaa !0 %tmp138 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp137, !tbaa !0
%tmp139 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 3 %tmp139 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 3
%tmp140 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp139, !tbaa !0 %tmp140 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp139, !tbaa !0
%tmp141 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 4 %tmp141 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 4
%tmp142 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp141, !tbaa !0 %tmp142 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp141, !tbaa !0
%tmp143 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 4 %tmp143 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 4
%tmp144 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp143, !tbaa !0 %tmp144 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp143, !tbaa !0
%tmp145 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 5 %tmp145 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 5
%tmp146 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp145, !tbaa !0 %tmp146 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp145, !tbaa !0
%tmp147 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 5 %tmp147 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 5
%tmp148 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp147, !tbaa !0 %tmp148 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp147, !tbaa !0
%tmp149 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 6 %tmp149 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 6
%tmp150 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp149, !tbaa !0 %tmp150 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp149, !tbaa !0
%tmp151 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 6 %tmp151 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 6
%tmp152 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp151, !tbaa !0 %tmp152 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp151, !tbaa !0
%tmp153 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 7 %tmp153 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 7
%tmp154 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp153, !tbaa !0 %tmp154 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp153, !tbaa !0
%tmp155 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 7 %tmp155 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 7
%tmp156 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp155, !tbaa !0 %tmp156 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp155, !tbaa !0
%tmp157 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(2)* %arg2, i64 0, i32 8 %tmp157 = getelementptr [16 x <8 x i32>], [16 x <8 x i32>] addrspace(4)* %arg2, i64 0, i32 8
%tmp158 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp157, !tbaa !0 %tmp158 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp157, !tbaa !0
%tmp159 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(2)* %arg1, i64 0, i32 8 %tmp159 = getelementptr [32 x <4 x i32>], [32 x <4 x i32>] addrspace(4)* %arg1, i64 0, i32 8
%tmp160 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp159, !tbaa !0 %tmp160 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp159, !tbaa !0
%tmp161 = fcmp ugt float %arg17, 0.000000e+00 %tmp161 = fcmp ugt float %arg17, 0.000000e+00
%tmp162 = select i1 %tmp161, float 1.000000e+00, float 0.000000e+00 %tmp162 = select i1 %tmp161, float 1.000000e+00, float 0.000000e+00
%i.i = extractelement <2 x i32> %arg6, i32 0 %i.i = extractelement <2 x i32> %arg6, i32 0
%j.i = extractelement <2 x i32> %arg6, i32 1 %j.i = extractelement <2 x i32> %arg6, i32 1
%i.f.i = bitcast i32 %i.i to float %i.f.i = bitcast i32 %i.i to float
%j.f.i = bitcast i32 %j.i to float %j.f.i = bitcast i32 %j.i to float
%p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0 %p1.i = call float @llvm.amdgcn.interp.p1(float %i.f.i, i32 0, i32 0, i32 %arg4) #0
%p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0 %p2.i = call float @llvm.amdgcn.interp.p2(float %p1.i, float %j.f.i, i32 0, i32 0, i32 %arg4) #0
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test/CodeGen/AMDGPU/si-triv-disjoint-mem-access.ll

; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=bonaire -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -enable-amdgpu-aa=0 -verify-machineinstrs -enable-misched -enable-aa-sched-mi < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.i32(i32, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1) declare void @llvm.amdgcn.tbuffer.store.v4i32(<4 x i32>, <4 x i32>, i32, i32, i32, i32, i32, i32, i1, i1)
declare void @llvm.amdgcn.s.barrier() #1 declare void @llvm.amdgcn.s.barrier() #1
declare i32 @llvm.amdgcn.workitem.id.x() #2 declare i32 @llvm.amdgcn.workitem.id.x() #2
@stored_lds_ptr = addrspace(3) global i32 addrspace(3)* undef, align 4 @stored_lds_ptr = addrspace(3) global i32 addrspace(3)* undef, align 4
@stored_constant_ptr = addrspace(3) global i32 addrspace(2)* undef, align 8 @stored_constant_ptr = addrspace(3) global i32 addrspace(4)* undef, align 8
@stored_global_ptr = addrspace(3) global i32 addrspace(1)* undef, align 8 @stored_global_ptr = addrspace(3) global i32 addrspace(1)* undef, align 8
; GCN-LABEL: {{^}}reorder_local_load_global_store_local_load: ; GCN-LABEL: {{^}}reorder_local_load_global_store_local_load:
; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3 ; CI: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
; CI: buffer_store_dword ; CI: buffer_store_dword
; GFX9: global_store_dword ; GFX9: global_store_dword
; GFX9: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3 ; GFX9: ds_read2_b32 {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} offset0:1 offset1:3
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; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4 ; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4
; GFX9: global_store_dword ; GFX9: global_store_dword
; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc ; GFX9: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc
; CI: buffer_store_dword ; CI: buffer_store_dword
; GFX9: global_store_dword ; GFX9: global_store_dword
define amdgpu_kernel void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 { define amdgpu_kernel void @reorder_constant_load_global_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(1)* %gptr) #0 {
%ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8 %ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8
%ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 3 %ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 3
%tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4 %tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4
store i32 99, i32 addrspace(1)* %gptr, align 4 store i32 99, i32 addrspace(1)* %gptr, align 4
%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4 %tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
%add = add nsw i32 %tmp1, %tmp2 %add = add nsw i32 %tmp1, %tmp2
store i32 %add, i32 addrspace(1)* %out, align 4 store i32 %add, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}reorder_constant_load_local_store_constant_load: ; GCN-LABEL: {{^}}reorder_constant_load_local_store_constant_load:
; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_LO:[0-9]+]], v{{[0-9]+}}
; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}} ; GCN: v_readfirstlane_b32 s[[PTR_HI:[0-9]+]], v{{[0-9]+}}
; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1 ; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x1
; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3 ; CI-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x3
; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4 ; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0x4
; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc ; GFX9-DAG: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0xc
; GCN: ds_write_b32 ; GCN: ds_write_b32
; CI: buffer_store_dword ; CI: buffer_store_dword
; GFX9: global_store_dword ; GFX9: global_store_dword
define amdgpu_kernel void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 { define amdgpu_kernel void @reorder_constant_load_local_store_constant_load(i32 addrspace(1)* %out, i32 addrspace(3)* %lptr) #0 {
%ptr0 = load i32 addrspace(2)*, i32 addrspace(2)* addrspace(3)* @stored_constant_ptr, align 8 %ptr0 = load i32 addrspace(4)*, i32 addrspace(4)* addrspace(3)* @stored_constant_ptr, align 8
%ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 3 %ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 3
%tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4 %tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4
store i32 99, i32 addrspace(3)* %lptr, align 4 store i32 99, i32 addrspace(3)* %lptr, align 4
%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4 %tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
%add = add nsw i32 %tmp1, %tmp2 %add = add nsw i32 %tmp1, %tmp2
store i32 %add, i32 addrspace(1)* %out, align 4 store i32 %add, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}reorder_smrd_load_local_store_smrd_load: ; GCN-LABEL: {{^}}reorder_smrd_load_local_store_smrd_load:
; GCN: s_load_dword ; GCN: s_load_dword
; GCN: s_load_dword ; GCN: s_load_dword
; GCN: s_load_dword ; GCN: s_load_dword
; GCN: ds_write_b32 ; GCN: ds_write_b32
; CI: buffer_store_dword ; CI: buffer_store_dword
; GFX9: global_store_dword ; GFX9: global_store_dword
define amdgpu_kernel void @reorder_smrd_load_local_store_smrd_load(i32 addrspace(1)* %out, i32 addrspace(3)* noalias %lptr, i32 addrspace(2)* %ptr0) #0 { define amdgpu_kernel void @reorder_smrd_load_local_store_smrd_load(i32 addrspace(1)* %out, i32 addrspace(3)* noalias %lptr, i32 addrspace(4)* %ptr0) #0 {
%ptr1 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 1
%ptr2 = getelementptr inbounds i32, i32 addrspace(2)* %ptr0, i64 2 %ptr2 = getelementptr inbounds i32, i32 addrspace(4)* %ptr0, i64 2
%tmp1 = load i32, i32 addrspace(2)* %ptr1, align 4 %tmp1 = load i32, i32 addrspace(4)* %ptr1, align 4
store i32 99, i32 addrspace(3)* %lptr, align 4 store i32 99, i32 addrspace(3)* %lptr, align 4
%tmp2 = load i32, i32 addrspace(2)* %ptr2, align 4 %tmp2 = load i32, i32 addrspace(4)* %ptr2, align 4
%add = add nsw i32 %tmp1, %tmp2 %add = add nsw i32 %tmp1, %tmp2
store i32 %add, i32 addrspace(1)* %out, align 4 store i32 %add, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}reorder_global_load_local_store_global_load: ; GCN-LABEL: {{^}}reorder_global_load_local_store_global_load:
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test/CodeGen/AMDGPU/smrd-vccz-bug.ll

; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VCCZ-BUG %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOVCCZ-BUG %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=NOVCCZ-BUG %s
; GCN-FUNC: {{^}}vccz_workaround: ; GCN-FUNC: {{^}}vccz_workaround:
; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], 0x0
; GCN: v_cmp_neq_f32_e64 {{[^,]*}}, s{{[0-9]+}}, 0{{$}} ; GCN: v_cmp_neq_f32_e64 {{[^,]*}}, s{{[0-9]+}}, 0{{$}}
; VCCZ-BUG: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; VCCZ-BUG: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; VCCZ-BUG: s_mov_b64 vcc, vcc ; VCCZ-BUG: s_mov_b64 vcc, vcc
; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc ; NOVCCZ-BUG-NOT: s_mov_b64 vcc, vcc
; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]] ; GCN: s_cbranch_vccnz [[EXIT:[0-9A-Za-z_]+]]
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: [[EXIT]]: ; GCN: [[EXIT]]:
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @vccz_workaround(i32 addrspace(2)* %in, i32 addrspace(1)* %out, float %cond) { define amdgpu_kernel void @vccz_workaround(i32 addrspace(4)* %in, i32 addrspace(1)* %out, float %cond) {
entry: entry:
%cnd = fcmp oeq float 0.0, %cond %cnd = fcmp oeq float 0.0, %cond
%sgpr = load volatile i32, i32 addrspace(2)* %in %sgpr = load volatile i32, i32 addrspace(4)* %in
br i1 %cnd, label %if, label %endif br i1 %cnd, label %if, label %endif
if: if:
store i32 %sgpr, i32 addrspace(1)* %out store i32 %sgpr, i32 addrspace(1)* %out
br label %endif br label %endif
endif: endif:
ret void ret void
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test/CodeGen/AMDGPU/smrd.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SICI -check-prefix=SIVIGFX9 %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=SI -check-prefix=GCN -check-prefix=SICI -check-prefix=SIVIGFX9 %s
; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=SICI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=CI -check-prefix=GCN -check-prefix=SICI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=VI -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs -show-mc-encoding < %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN -check-prefix=VIGFX9 -check-prefix=SIVIGFX9 %s
; SMRD load with an immediate offset. ; SMRD load with an immediate offset.
; GCN-LABEL: {{^}}smrd0: ; GCN-LABEL: {{^}}smrd0:
; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01 ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @smrd0(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
entry: entry:
%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 1 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 1
%tmp1 = load i32, i32 addrspace(2)* %tmp %tmp1 = load i32, i32 addrspace(4)* %tmp
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with the largest possible immediate offset. ; SMRD load with the largest possible immediate offset.
; GCN-LABEL: {{^}}smrd1: ; GCN-LABEL: {{^}}smrd1:
; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}} ; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @smrd1(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
entry: entry:
%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 255 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 255
%tmp1 = load i32, i32 addrspace(2)* %tmp %tmp1 = load i32, i32 addrspace(4)* %tmp
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with an offset greater than the largest possible immediate. ; SMRD load with an offset greater than the largest possible immediate.
; GCN-LABEL: {{^}}smrd2: ; GCN-LABEL: {{^}}smrd2:
; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @smrd2(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
entry: entry:
%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 256 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 256
%tmp1 = load i32, i32 addrspace(2)* %tmp %tmp1 = load i32, i32 addrspace(4)* %tmp
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with a 64-bit offset ; SMRD load with a 64-bit offset
; GCN-LABEL: {{^}}smrd3: ; GCN-LABEL: {{^}}smrd3:
; FIXME: There are too many copies here because we don't fold immediates ; FIXME: There are too many copies here because we don't fold immediates
; through REG_SEQUENCE ; through REG_SEQUENCE
; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b ; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
; TODO: Add VI checks ; TODO: Add VI checks
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @smrd3(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
entry: entry:
%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 4294967296 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 4294967296
%tmp1 = load i32, i32 addrspace(2)* %tmp %tmp1 = load i32, i32 addrspace(4)* %tmp
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with the largest possible immediate offset on VI ; SMRD load with the largest possible immediate offset on VI
; GCN-LABEL: {{^}}smrd4: ; GCN-LABEL: {{^}}smrd4:
; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc ; VIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @smrd4(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
entry: entry:
%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 262143 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 262143
%tmp1 = load i32, i32 addrspace(2)* %tmp %tmp1 = load i32, i32 addrspace(4)* %tmp
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
; SMRD load with an offset greater than the largest possible immediate on VI ; SMRD load with an offset greater than the largest possible immediate on VI
; GCN-LABEL: {{^}}smrd5: ; GCN-LABEL: {{^}}smrd5:
; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 ; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
; SIVIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SIVIGFX9: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 ; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @smrd5(i32 addrspace(1)* %out, i32 addrspace(4)* %ptr) #0 {
entry: entry:
%tmp = getelementptr i32, i32 addrspace(2)* %ptr, i64 262144 %tmp = getelementptr i32, i32 addrspace(4)* %ptr, i64 262144
%tmp1 = load i32, i32 addrspace(2)* %tmp %tmp1 = load i32, i32 addrspace(4)* %tmp
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_hazard: ; GCN-LABEL: {{^}}smrd_hazard:
; GCN-DAG: s_mov_b32 s3, 3 ; GCN-DAG: s_mov_b32 s3, 3
; GCN-DAG: s_mov_b32 s2, 2 ; GCN-DAG: s_mov_b32 s2, 2
; GCN-DAG: s_mov_b32 s1, 1 ; GCN-DAG: s_mov_b32 s1, 1
Show All 9 Linesmain_body:
%r = call float @llvm.SI.load.const.v4i32(<4 x i32> %d3, i32 0) %r = call float @llvm.SI.load.const.v4i32(<4 x i32> %d3, i32 0)
ret float %r ret float %r
} }
; SMRD load using the load.const.v4i32 intrinsic with an immediate offset ; SMRD load using the load.const.v4i32 intrinsic with an immediate offset
; GCN-LABEL: {{^}}smrd_load_const0: ; GCN-LABEL: {{^}}smrd_load_const0:
; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04 ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10
define amdgpu_ps void @smrd_load_const0(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @smrd_load_const0(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 16)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
ret void ret void
} }
; SMRD load using the load.const.v4i32 intrinsic with the largest possible immediate ; SMRD load using the load.const.v4i32 intrinsic with the largest possible immediate
; offset. ; offset.
; GCN-LABEL: {{^}}smrd_load_const1: ; GCN-LABEL: {{^}}smrd_load_const1:
; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff ; SICI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff
; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
define amdgpu_ps void @smrd_load_const1(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @smrd_load_const1(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1020) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1020)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
ret void ret void
} }
; SMRD load using the load.const.v4i32 intrinsic with an offset greater than the ; SMRD load using the load.const.v4i32 intrinsic with an offset greater than the
; largets possible immediate. ; largets possible immediate.
; immediate offset. ; immediate offset.
; GCN-LABEL: {{^}}smrd_load_const2: ; GCN-LABEL: {{^}}smrd_load_const2:
; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400 ; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]] ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400 ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
define amdgpu_ps void @smrd_load_const2(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @smrd_load_const2(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1024) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1024)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
ret void ret void
} }
; SMRD load with the largest possible immediate offset on VI ; SMRD load with the largest possible immediate offset on VI
; GCN-LABEL: {{^}}smrd_load_const3: ; GCN-LABEL: {{^}}smrd_load_const3:
; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc ; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc ; VIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
define amdgpu_ps void @smrd_load_const3(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @smrd_load_const3(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048572) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048572)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
ret void ret void
} }
; SMRD load with an offset greater than the largest possible immediate on VI ; SMRD load with an offset greater than the largest possible immediate on VI
; GCN-LABEL: {{^}}smrd_load_const4: ; GCN-LABEL: {{^}}smrd_load_const4:
; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000 ; SIVIGFX9: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
; SIVIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]] ; SIVIGFX9: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000 ; CI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_ps void @smrd_load_const4(<4 x i32> addrspace(2)* inreg %arg, <4 x i32> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 { define amdgpu_ps void @smrd_load_const4(<4 x i32> addrspace(4)* inreg %arg, <4 x i32> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %arg3, <2 x i32> %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <3 x i32> %arg7, <2 x i32> %arg8, <2 x i32> %arg9, <2 x i32> %arg10, float %arg11, float %arg12, float %arg13, float %arg14, float %arg15, float %arg16, float %arg17, float %arg18, float %arg19) #0 {
main_body: main_body:
%tmp = getelementptr <4 x i32>, <4 x i32> addrspace(2)* %arg, i32 0 %tmp = getelementptr <4 x i32>, <4 x i32> addrspace(4)* %arg, i32 0
%tmp20 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp %tmp20 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp
%tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048576) %tmp21 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp20, i32 1048576)
call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %tmp21, float %tmp21, float %tmp21, float %tmp21, i1 true, i1 true) #0
ret void ret void
} }
; GCN-LABEL: {{^}}smrd_sgpr_offset: ; GCN-LABEL: {{^}}smrd_sgpr_offset:
; GCN: s_buffer_load_dword s{{[0-9]}}, s[0:3], s4 ; GCN: s_buffer_load_dword s{{[0-9]}}, s[0:3], s4
define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 { define amdgpu_ps float @smrd_sgpr_offset(<4 x i32> inreg %desc, i32 inreg %offset) #0 {
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test/CodeGen/AMDGPU/spill-m0.ll

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; TOSMEM: BB{{[0-9]+_[0-9]+}}: ; TOSMEM: BB{{[0-9]+_[0-9]+}}:
; TOSMEM: s_add_u32 m0, s7, 0x400 ; TOSMEM: s_add_u32 m0, s7, 0x400
; TOSMEM-NEXT: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Reload ; TOSMEM-NEXT: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Reload
; GCN-NOT: v_readlane_b32 m0 ; GCN-NOT: v_readlane_b32 m0
; GCN-NOT: s_buffer_store_dword m0 ; GCN-NOT: s_buffer_store_dword m0
; GCN-NOT: s_buffer_load_dword m0 ; GCN-NOT: s_buffer_load_dword m0
define amdgpu_ps void @spill_kill_m0_lds(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, i32 inreg %m0) #0 { define amdgpu_ps void @spill_kill_m0_lds(<16 x i8> addrspace(4)* inreg %arg, <16 x i8> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, i32 inreg %m0) #0 {
main_body: main_body:
%tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0) %tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0)
%cmp = fcmp ueq float 0.000000e+00, %tmp %cmp = fcmp ueq float 0.000000e+00, %tmp
br i1 %cmp, label %if, label %else br i1 %cmp, label %if, label %else
if: ; preds = %main_body if: ; preds = %main_body
%lds_ptr = getelementptr [64 x float], [64 x float] addrspace(3)* @lds, i32 0, i32 0 %lds_ptr = getelementptr [64 x float], [64 x float] addrspace(3)* @lds, i32 0, i32 0
%lds_data = load float, float addrspace(3)* %lds_ptr %lds_data = load float, float addrspace(3)* %lds_ptr
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; TOSMEM-NOT: m0 ; TOSMEM-NOT: m0
; TOSMEM: s_mov_b32 m0, s0 ; TOSMEM: s_mov_b32 m0, s0
; TOSMEM: ; use m0 ; TOSMEM: ; use m0
; TOSMEM: s_dcache_wb ; TOSMEM: s_dcache_wb
; TOSMEM: s_endpgm ; TOSMEM: s_endpgm
define amdgpu_kernel void @restore_m0_lds(i32 %arg) { define amdgpu_kernel void @restore_m0_lds(i32 %arg) {
%m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={M0}"() #0 %m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={M0}"() #0
%sval = load volatile i64, i64 addrspace(2)* undef %sval = load volatile i64, i64 addrspace(4)* undef
%cmp = icmp eq i32 %arg, 0 %cmp = icmp eq i32 %arg, 0
br i1 %cmp, label %ret, label %bb br i1 %cmp, label %ret, label %bb
bb: bb:
store volatile i64 %sval, i64 addrspace(3)* undef store volatile i64 %sval, i64 addrspace(3)* undef
call void asm sideeffect "; use $0", "{M0}"(i32 %m0) #0 call void asm sideeffect "; use $0", "{M0}"(i32 %m0) #0
br label %ret br label %ret
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test/CodeGen/AMDGPU/split-smrd.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Move this to sgpr-copy.ll when this is fixed on VI. ; FIXME: Move this to sgpr-copy.ll when this is fixed on VI.
; Make sure that when we split an smrd instruction in order to move it to ; Make sure that when we split an smrd instruction in order to move it to
; the VALU, we are also moving its users to the VALU. ; the VALU, we are also moving its users to the VALU.
; GCN-LABEL: {{^}}split_smrd_add_worklist: ; GCN-LABEL: {{^}}split_smrd_add_worklist:
; GCN: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1 ; GCN: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}] dmask:0x1
define amdgpu_ps void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(2)* byval %arg) #0 { define amdgpu_ps void @split_smrd_add_worklist([34 x <8 x i32>] addrspace(4)* byval %arg) #0 {
bb: bb:
%tmp = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 96) %tmp = call float @llvm.SI.load.const.v4i32(<4 x i32> undef, i32 96)
%tmp1 = bitcast float %tmp to i32 %tmp1 = bitcast float %tmp to i32
br i1 undef, label %bb2, label %bb3 br i1 undef, label %bb2, label %bb3
bb2: ; preds = %bb bb2: ; preds = %bb
unreachable unreachable
bb3: ; preds = %bb bb3: ; preds = %bb
%tmp4 = bitcast float %tmp to i32 %tmp4 = bitcast float %tmp to i32
%tmp5 = add i32 %tmp4, 4 %tmp5 = add i32 %tmp4, 4
%tmp6 = sext i32 %tmp5 to i64 %tmp6 = sext i32 %tmp5 to i64
%tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(2)* %arg, i64 0, i64 %tmp6 %tmp7 = getelementptr [34 x <8 x i32>], [34 x <8 x i32>] addrspace(4)* %arg, i64 0, i64 %tmp6
%tmp8 = load <8 x i32>, <8 x i32> addrspace(2)* %tmp7, align 32, !tbaa !0 %tmp8 = load <8 x i32>, <8 x i32> addrspace(4)* %tmp7, align 32, !tbaa !0
%tmp9 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float bitcast (i32 1061158912 to float), float bitcast (i32 1048576000 to float)>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) %tmp9 = call <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> <float bitcast (i32 1061158912 to float), float bitcast (i32 1048576000 to float)>, <8 x i32> %tmp8, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false)
%tmp10 = extractelement <4 x float> %tmp9, i32 0 %tmp10 = extractelement <4 x float> %tmp9, i32 0
%tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef) %tmp12 = call <2 x half> @llvm.amdgcn.cvt.pkrtz(float %tmp10, float undef)
call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0 call void @llvm.amdgcn.exp.compr.v2f16(i32 0, i32 15, <2 x half> %tmp12, <2 x half> undef, i1 true, i1 true) #0
ret void ret void
} }
declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1 declare <2 x half> @llvm.amdgcn.cvt.pkrtz(float, float) #1
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test/CodeGen/AMDGPU/store-global.ll

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; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XY, T[0-9]+\.X}}, 1 ; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.XY, T[0-9]+\.X}}, 1
; EG-NOT: MEM_RAT_CACHELESS STORE_RAW ; EG-NOT: MEM_RAT_CACHELESS STORE_RAW
; CM: MEM_RAT_CACHELESS STORE_DWORD ; CM: MEM_RAT_CACHELESS STORE_DWORD
; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD ; CM-NOT: MEM_RAT_CACHELESS STORE_DWORD
; SIVI: buffer_store_dwordx2 ; SIVI: buffer_store_dwordx2
; GFX9: global_store_dwordx2 ; GFX9: global_store_dwordx2
define amdgpu_kernel void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { define amdgpu_kernel void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(4)* nocapture %mem) #0 {
entry: entry:
%0 = load i32, i32 addrspace(2)* %mem, align 4 %0 = load i32, i32 addrspace(4)* %mem, align 4
%arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1 %arrayidx1.i = getelementptr inbounds i32, i32 addrspace(4)* %mem, i64 1
%1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4 %1 = load i32, i32 addrspace(4)* %arrayidx1.i, align 4
store i32 %0, i32 addrspace(1)* %out, align 4 store i32 %0, i32 addrspace(1)* %out, align 4
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %out, i64 1
store i32 %1, i32 addrspace(1)* %arrayidx1, align 4 store i32 %1, i32 addrspace(1)* %arrayidx1, align 4
ret void ret void
} }
; When i128 was a legal type this program generated cannot select errors: ; When i128 was a legal type this program generated cannot select errors:
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test/CodeGen/AMDGPU/store-private.ll

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; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x2? ;TODO: why not x2?
; XSI: buffer_store_dwordx2 ; XSI: buffer_store_dwordx2
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @vecload2(i32 addrspace(5)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { define amdgpu_kernel void @vecload2(i32 addrspace(5)* nocapture %out, i32 addrspace(4)* nocapture %mem) #0 {
entry: entry:
%0 = load i32, i32 addrspace(2)* %mem, align 4 %0 = load i32, i32 addrspace(4)* %mem, align 4
%arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1 %arrayidx1.i = getelementptr inbounds i32, i32 addrspace(4)* %mem, i64 1
%1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4 %1 = load i32, i32 addrspace(4)* %arrayidx1.i, align 4
store i32 %0, i32 addrspace(5)* %out, align 4 store i32 %0, i32 addrspace(5)* %out, align 4
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1
store i32 %1, i32 addrspace(5)* %arrayidx1, align 4 store i32 %1, i32 addrspace(5)* %arrayidx1, align 4
ret void ret void
} }
; When i128 was a legal type this program generated cannot select errors: ; When i128 was a legal type this program generated cannot select errors:
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test/CodeGen/AMDGPU/sub.v2i16.ll

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; GCN-LABEL: {{^}}s_test_sub_v2i16: ; GCN-LABEL: {{^}}s_test_sub_v2i16:
; GFX9: s_load_dword [[VAL0:s[0-9]+]] ; GFX9: s_load_dword [[VAL0:s[0-9]+]]
; GFX9: s_load_dword [[VAL1:s[0-9]+]] ; GFX9: s_load_dword [[VAL1:s[0-9]+]]
; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]] ; GFX9: v_mov_b32_e32 [[VVAL1:v[0-9]+]]
; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]] ; GFX9: v_pk_sub_i16 v{{[0-9]+}}, [[VAL0]], [[VVAL1]]
; VI: s_sub_i32 ; VI: s_sub_i32
; VI: s_sub_i32 ; VI: s_sub_i32
define amdgpu_kernel void @s_test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %in0, <2 x i16> addrspace(2)* %in1) #1 { define amdgpu_kernel void @s_test_sub_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0, <2 x i16> addrspace(4)* %in1) #1 {
%a = load <2 x i16>, <2 x i16> addrspace(2)* %in0 %a = load <2 x i16>, <2 x i16> addrspace(4)* %in0
%b = load <2 x i16>, <2 x i16> addrspace(2)* %in1 %b = load <2 x i16>, <2 x i16> addrspace(4)* %in1
%add = sub <2 x i16> %a, %b %add = sub <2 x i16> %a, %b
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}s_test_sub_self_v2i16: ; GCN-LABEL: {{^}}s_test_sub_self_v2i16:
; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]] ; GCN: v_mov_b32_e32 [[ZERO:v[0-9]+]]
; GCN: buffer_store_dword [[ZERO]] ; GCN: buffer_store_dword [[ZERO]]
define amdgpu_kernel void @s_test_sub_self_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(2)* %in0) #1 { define amdgpu_kernel void @s_test_sub_self_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(4)* %in0) #1 {
%a = load <2 x i16>, <2 x i16> addrspace(2)* %in0 %a = load <2 x i16>, <2 x i16> addrspace(4)* %in0
%add = sub <2 x i16> %a, %a %add = sub <2 x i16> %a, %a
store <2 x i16> %add, <2 x i16> addrspace(1)* %out store <2 x i16> %add, <2 x i16> addrspace(1)* %out
ret void ret void
} }
; FIXME: VI should not scalarize arg access. ; FIXME: VI should not scalarize arg access.
; GCN-LABEL: {{^}}s_test_sub_v2i16_kernarg: ; GCN-LABEL: {{^}}s_test_sub_v2i16_kernarg:
; GFX9: v_pk_sub_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}} ; GFX9: v_pk_sub_i16 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}
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test/CodeGen/AMDGPU/target-cpu.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
declare i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() #1 declare i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr() #1
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
; CI+ intrinsic ; CI+ intrinsic
declare void @llvm.amdgcn.s.dcache.inv.vol() #0 declare void @llvm.amdgcn.s.dcache.inv.vol() #0
; VI+ intrinsic ; VI+ intrinsic
declare void @llvm.amdgcn.s.dcache.wb() #0 declare void @llvm.amdgcn.s.dcache.wb() #0
; CHECK-LABEL: {{^}}target_none: ; CHECK-LABEL: {{^}}target_none:
; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400 ; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400
; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]] ; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]]
; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
define amdgpu_kernel void @target_none() #0 { define amdgpu_kernel void @target_none() #0 {
%kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 %kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
%kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64 %id.ext = sext i32 %id to i64
%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
ret void ret void
} }
; CHECK-LABEL: {{^}}target_tahiti: ; CHECK-LABEL: {{^}}target_tahiti:
; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400 ; CHECK: s_movk_i32 [[OFFSETREG:s[0-9]+]], 0x400
; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]] ; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSETREG]]
; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
define amdgpu_kernel void @target_tahiti() #1 { define amdgpu_kernel void @target_tahiti() #1 {
%kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 %kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
%kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64 %id.ext = sext i32 %id to i64
%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
ret void ret void
} }
; CHECK-LABEL: {{^}}target_bonaire: ; CHECK-LABEL: {{^}}target_bonaire:
; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x100 ; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x100
; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64 ; CHECK: buffer_store_dword v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0 addr64
; CHECK: s_dcache_inv_vol ; CHECK: s_dcache_inv_vol
define amdgpu_kernel void @target_bonaire() #3 { define amdgpu_kernel void @target_bonaire() #3 {
%kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 %kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
%kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64 %id.ext = sext i32 %id to i64
%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
call void @llvm.amdgcn.s.dcache.inv.vol() call void @llvm.amdgcn.s.dcache.inv.vol()
ret void ret void
} }
; CHECK-LABEL: {{^}}target_fiji: ; CHECK-LABEL: {{^}}target_fiji:
; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x400 ; CHECK: s_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x400
; CHECK: flat_store_dword ; CHECK: flat_store_dword
; CHECK: s_dcache_wb{{$}} ; CHECK: s_dcache_wb{{$}}
define amdgpu_kernel void @target_fiji() #4 { define amdgpu_kernel void @target_fiji() #4 {
%kernargs = call i8 addrspace(2)* @llvm.amdgcn.kernarg.segment.ptr() %kernargs = call i8 addrspace(4)* @llvm.amdgcn.kernarg.segment.ptr()
%kernargs.gep = getelementptr inbounds i8, i8 addrspace(2)* %kernargs, i64 1024 %kernargs.gep = getelementptr inbounds i8, i8 addrspace(4)* %kernargs, i64 1024
%kernargs.gep.cast = bitcast i8 addrspace(2)* %kernargs.gep to i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast = bitcast i8 addrspace(4)* %kernargs.gep to i32 addrspace(1)* addrspace(4)*
%ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(2)* %kernargs.gep.cast %ptr = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(4)* %kernargs.gep.cast
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%id.ext = sext i32 %id to i64 %id.ext = sext i32 %id to i64
%gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext %gep = getelementptr inbounds i32, i32 addrspace(1)* %ptr, i64 %id.ext
store i32 0, i32 addrspace(1)* %gep store i32 0, i32 addrspace(1)* %gep
call void @llvm.amdgcn.s.dcache.wb() call void @llvm.amdgcn.s.dcache.wb()
ret void ret void
} }
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test/CodeGen/AMDGPU/unaligned-load-store.ll

Show First 20 Lines • Show All 92 Lines • ▼ Show 20 Lines
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; UNALIGNED: s_load_dword ; UNALIGNED: s_load_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @constant_unaligned_load_i32(i32 addrspace(2)* %p, i32 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_unaligned_load_i32(i32 addrspace(4)* %p, i32 addrspace(1)* %r) #0 {
%v = load i32, i32 addrspace(2)* %p, align 1 %v = load i32, i32 addrspace(4)* %p, align 1
store i32 %v, i32 addrspace(1)* %r, align 4 store i32 %v, i32 addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_align2_load_i32: ; SI-LABEL: {{^}}constant_align2_load_i32:
; ALIGNED: buffer_load_ushort ; ALIGNED: buffer_load_ushort
; ALIGNED: buffer_load_ushort ; ALIGNED: buffer_load_ushort
; UNALIGNED: s_load_dword ; UNALIGNED: s_load_dword
; UNALIGNED: buffer_store_dword ; UNALIGNED: buffer_store_dword
define amdgpu_kernel void @constant_align2_load_i32(i32 addrspace(2)* %p, i32 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align2_load_i32(i32 addrspace(4)* %p, i32 addrspace(1)* %r) #0 {
%v = load i32, i32 addrspace(2)* %p, align 2 %v = load i32, i32 addrspace(4)* %p, align 2
store i32 %v, i32 addrspace(1)* %r, align 4 store i32 %v, i32 addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_align2_load_i64: ; SI-LABEL: {{^}}constant_align2_load_i64:
; ALIGNED: buffer_load_ushort ; ALIGNED: buffer_load_ushort
; ALIGNED: buffer_load_ushort ; ALIGNED: buffer_load_ushort
; ALIGNED: buffer_load_ushort ; ALIGNED: buffer_load_ushort
; ALIGNED: buffer_load_ushort ; ALIGNED: buffer_load_ushort
; UNALIGNED: s_load_dwordx2 ; UNALIGNED: s_load_dwordx2
; UNALIGNED: buffer_store_dwordx2 ; UNALIGNED: buffer_store_dwordx2
define amdgpu_kernel void @constant_align2_load_i64(i64 addrspace(2)* %p, i64 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align2_load_i64(i64 addrspace(4)* %p, i64 addrspace(1)* %r) #0 {
%v = load i64, i64 addrspace(2)* %p, align 2 %v = load i64, i64 addrspace(4)* %p, align 2
store i64 %v, i64 addrspace(1)* %r, align 4 store i64 %v, i64 addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_align4_load_i64: ; SI-LABEL: {{^}}constant_align4_load_i64:
; SI: s_load_dwordx2 ; SI: s_load_dwordx2
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @constant_align4_load_i64(i64 addrspace(2)* %p, i64 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align4_load_i64(i64 addrspace(4)* %p, i64 addrspace(1)* %r) #0 {
%v = load i64, i64 addrspace(2)* %p, align 4 %v = load i64, i64 addrspace(4)* %p, align 4
store i64 %v, i64 addrspace(1)* %r, align 4 store i64 %v, i64 addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_align4_load_v4i32: ; SI-LABEL: {{^}}constant_align4_load_v4i32:
; SI: s_load_dwordx4 ; SI: s_load_dwordx4
; SI: buffer_store_dwordx4 ; SI: buffer_store_dwordx4
define amdgpu_kernel void @constant_align4_load_v4i32(<4 x i32> addrspace(2)* %p, <4 x i32> addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align4_load_v4i32(<4 x i32> addrspace(4)* %p, <4 x i32> addrspace(1)* %r) #0 {
%v = load <4 x i32>, <4 x i32> addrspace(2)* %p, align 4 %v = load <4 x i32>, <4 x i32> addrspace(4)* %p, align 4
store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 4 store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_unaligned_load_v2i32: ; SI-LABEL: {{^}}constant_unaligned_load_v2i32:
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; UNALIGNED: buffer_load_dwordx2 ; UNALIGNED: buffer_load_dwordx2
; SI: buffer_store_dwordx2 ; SI: buffer_store_dwordx2
define amdgpu_kernel void @constant_unaligned_load_v2i32(<2 x i32> addrspace(2)* %p, <2 x i32> addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_unaligned_load_v2i32(<2 x i32> addrspace(4)* %p, <2 x i32> addrspace(1)* %r) #0 {
%v = load <2 x i32>, <2 x i32> addrspace(2)* %p, align 1 %v = load <2 x i32>, <2 x i32> addrspace(4)* %p, align 1
store <2 x i32> %v, <2 x i32> addrspace(1)* %r, align 4 store <2 x i32> %v, <2 x i32> addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_unaligned_load_v4i32: ; SI-LABEL: {{^}}constant_unaligned_load_v4i32:
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
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; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; ALIGNED: buffer_load_ubyte ; ALIGNED: buffer_load_ubyte
; UNALIGNED: buffer_load_dwordx4 ; UNALIGNED: buffer_load_dwordx4
; SI: buffer_store_dwordx4 ; SI: buffer_store_dwordx4
define amdgpu_kernel void @constant_unaligned_load_v4i32(<4 x i32> addrspace(2)* %p, <4 x i32> addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_unaligned_load_v4i32(<4 x i32> addrspace(4)* %p, <4 x i32> addrspace(1)* %r) #0 {
%v = load <4 x i32>, <4 x i32> addrspace(2)* %p, align 1 %v = load <4 x i32>, <4 x i32> addrspace(4)* %p, align 1
store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 4 store <4 x i32> %v, <4 x i32> addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_align4_load_i8: ; SI-LABEL: {{^}}constant_align4_load_i8:
; SI: s_load_dword ; SI: s_load_dword
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @constant_align4_load_i8(i8 addrspace(2)* %p, i8 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align4_load_i8(i8 addrspace(4)* %p, i8 addrspace(1)* %r) #0 {
%v = load i8, i8 addrspace(2)* %p, align 4 %v = load i8, i8 addrspace(4)* %p, align 4
store i8 %v, i8 addrspace(1)* %r, align 4 store i8 %v, i8 addrspace(1)* %r, align 4
ret void ret void
} }
; SI-LABEL: {{^}}constant_align2_load_i8: ; SI-LABEL: {{^}}constant_align2_load_i8:
; SI: buffer_load_ubyte ; SI: buffer_load_ubyte
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @constant_align2_load_i8(i8 addrspace(2)* %p, i8 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align2_load_i8(i8 addrspace(4)* %p, i8 addrspace(1)* %r) #0 {
%v = load i8, i8 addrspace(2)* %p, align 2 %v = load i8, i8 addrspace(4)* %p, align 2
store i8 %v, i8 addrspace(1)* %r, align 2 store i8 %v, i8 addrspace(1)* %r, align 2
ret void ret void
} }
; SI-LABEL: {{^}}constant_align4_merge_load_2_i32: ; SI-LABEL: {{^}}constant_align4_merge_load_2_i32:
; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}} ; SI: s_load_dwordx2 s{{\[}}[[LO:[0-9]+]]:[[HI:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x0{{$}}
; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[LO]] ; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[LO]]
; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HI]] ; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[HI]]
; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}} ; SI: buffer_store_dwordx2 v{{\[}}[[VLO]]:[[VHI]]{{\]}}
define amdgpu_kernel void @constant_align4_merge_load_2_i32(i32 addrspace(2)* %p, i32 addrspace(1)* %r) #0 { define amdgpu_kernel void @constant_align4_merge_load_2_i32(i32 addrspace(4)* %p, i32 addrspace(1)* %r) #0 {
%gep0 = getelementptr i32, i32 addrspace(2)* %p, i64 1 %gep0 = getelementptr i32, i32 addrspace(4)* %p, i64 1
%v0 = load i32, i32 addrspace(2)* %p, align 4 %v0 = load i32, i32 addrspace(4)* %p, align 4
%v1 = load i32, i32 addrspace(2)* %gep0, align 4 %v1 = load i32, i32 addrspace(4)* %gep0, align 4
%gep1 = getelementptr i32, i32 addrspace(1)* %r, i64 1 %gep1 = getelementptr i32, i32 addrspace(1)* %r, i64 1
store i32 %v0, i32 addrspace(1)* %r, align 4 store i32 %v0, i32 addrspace(1)* %r, align 4
store i32 %v1, i32 addrspace(1)* %gep1, align 4 store i32 %v1, i32 addrspace(1)* %gep1, align 4
ret void ret void
} }
; SI-LABEL: {{^}}local_load_align1_v16i8: ; SI-LABEL: {{^}}local_load_align1_v16i8:
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test/CodeGen/AMDGPU/uniform-crash.ll

Show All 29 Linesbb:
%cnd = trunc i32 %arg to i1 %cnd = trunc i32 %arg to i1
br i1 %cnd, label %bb2, label %bb5 br i1 %cnd, label %bb2, label %bb5
bb2: ; preds = %bb bb2: ; preds = %bb
%tmp = mul i32 10, %arg1 %tmp = mul i32 10, %arg1
br label %bb3 br label %bb3
bb3: ; preds = %bb3, %bb2 bb3: ; preds = %bb3, %bb2
%val = load volatile i32, i32 addrspace(2)* undef %val = load volatile i32, i32 addrspace(4)* undef
%tmp4 = icmp eq i32 %val, %arg1 %tmp4 = icmp eq i32 %val, %arg1
br i1 %tmp4, label %bb5, label %bb3 br i1 %tmp4, label %bb5, label %bb3
bb5: ; preds = %bb3, %bb bb5: ; preds = %bb3, %bb
%tmp6 = tail call i32 @llvm.amdgcn.workitem.id.y() #1 %tmp6 = tail call i32 @llvm.amdgcn.workitem.id.y() #1
%tmp10 = icmp ult i32 %tmp6, %arg %tmp10 = icmp ult i32 %tmp6, %arg
br i1 %tmp10, label %bb11, label %bb12 br i1 %tmp10, label %bb11, label %bb12
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test/CodeGen/AMDGPU/vertex-fetch-encoding.ll

Show All 30 Linesdefine amdgpu_kernel void @vtx_fetch32_id3(i32 addrspace(1)* %out, i32 addrspace(7)* %in) {
store i32 %v, i32 addrspace(1)* %out store i32 %v, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}vtx_fetch32_id2: ; FUNC-LABEL: {{^}}vtx_fetch32_id2:
; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00 ; EG: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x10,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x08,0x00
; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00 ; CM: VTX_READ_32 T[[GPR:[0-9]]].X, T[[GPR]].X, 0, #2 ; encoding: [0x40,0x02,0x0[[GPR]],0x00,0x0[[GPR]],0xf0,0x5f,0x13,0x00,0x00,0x00,0x00
@t = internal addrspace(2) constant [4 x i32] [i32 0, i32 1, i32 2, i32 3] @t = internal addrspace(4) constant [4 x i32] [i32 0, i32 1, i32 2, i32 3]
define amdgpu_kernel void @vtx_fetch32_id2(i32 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @vtx_fetch32_id2(i32 addrspace(1)* %out, i32 %in) {
%a = getelementptr inbounds [4 x i32], [4 x i32] addrspace(2)* @t, i32 0, i32 %in %a = getelementptr inbounds [4 x i32], [4 x i32] addrspace(4)* @t, i32 0, i32 %in
%v = load i32, i32 addrspace(2)* %a %v = load i32, i32 addrspace(4)* %a
store i32 %v, i32 addrspace(1)* %out store i32 %v, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/vgpr-spill-emergency-stack-slot.ll

Show All 21 Lines
; GFX9-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe00000 ; GFX9-DAG: s_mov_b32 s[[DESC3:[0-9]+]], 0xe00000
; OFFREG is offset system SGPR ; OFFREG is offset system SGPR
; GCN: buffer_store_dword {{v[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], s12 offset:{{[0-9]+}} ; 4-byte Folded Spill ; GCN: buffer_store_dword {{v[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], s12 offset:{{[0-9]+}} ; 4-byte Folded Spill
; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], s12 offset:{{[0-9]+}} ; 4-byte Folded Reload ; GCN: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[DESC0]]:[[DESC3]]], s12 offset:{{[0-9]+}} ; 4-byte Folded Reload
; GCN: NumVgprs: 256 ; GCN: NumVgprs: 256
; GCN: ScratchSize: 1536 ; GCN: ScratchSize: 1536
define amdgpu_vs void @main([9 x <4 x i32>] addrspace(2)* byval %arg, [17 x <4 x i32>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <4 x i32>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { define amdgpu_vs void @main([9 x <4 x i32>] addrspace(4)* byval %arg, [17 x <4 x i32>] addrspace(4)* byval %arg1, [17 x <4 x i32>] addrspace(4)* byval %arg2, [34 x <8 x i32>] addrspace(4)* byval %arg3, [16 x <4 x i32>] addrspace(4)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
bb: bb:
%tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(2)* %arg1, i64 0, i64 0 %tmp = getelementptr [17 x <4 x i32>], [17 x <4 x i32>] addrspace(4)* %arg1, i64 0, i64 0
%tmp11 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp, align 16, !tbaa !0 %tmp11 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp, align 16, !tbaa !0
%tmp12 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp11, i32 0) %tmp12 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp11, i32 0)
%tmp13 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp11, i32 16) %tmp13 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp11, i32 16)
%tmp14 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp11, i32 32) %tmp14 = call float @llvm.SI.load.const.v4i32(<4 x i32> %tmp11, i32 32)
%tmp15 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(2)* %arg4, i64 0, i64 0 %tmp15 = getelementptr [16 x <4 x i32>], [16 x <4 x i32>] addrspace(4)* %arg4, i64 0, i64 0
%tmp16 = load <4 x i32>, <4 x i32> addrspace(2)* %tmp15, align 16, !tbaa !0 %tmp16 = load <4 x i32>, <4 x i32> addrspace(4)* %tmp15, align 16, !tbaa !0
%tmp17 = add i32 %arg5, %arg7 %tmp17 = add i32 %arg5, %arg7
%tmp16.cast = bitcast <4 x i32> %tmp16 to <4 x i32> %tmp16.cast = bitcast <4 x i32> %tmp16 to <4 x i32>
%tmp18 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp16.cast, i32 %tmp17, i32 0, i1 false, i1 false) %tmp18 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp16.cast, i32 %tmp17, i32 0, i1 false, i1 false)
%tmp19 = extractelement <4 x float> %tmp18, i32 0 %tmp19 = extractelement <4 x float> %tmp18, i32 0
%tmp20 = extractelement <4 x float> %tmp18, i32 1 %tmp20 = extractelement <4 x float> %tmp18, i32 1
%tmp21 = extractelement <4 x float> %tmp18, i32 2 %tmp21 = extractelement <4 x float> %tmp18, i32 2
%tmp22 = extractelement <4 x float> %tmp18, i32 3 %tmp22 = extractelement <4 x float> %tmp18, i32 3
%tmp23 = bitcast float %tmp14 to i32 %tmp23 = bitcast float %tmp14 to i32
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test/CodeGen/AMDGPU/wait.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=DEFAULT
; RUN: llc -march=amdgcn --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX ; RUN: llc -march=amdgcn --misched=ilpmax -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX ; RUN: llc -march=amdgcn --misched=ilpmax -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -strict-whitespace %s --check-prefix=ILPMAX
; The ilpmax scheduler is used for the second test to get the ordering we want for the test. ; The ilpmax scheduler is used for the second test to get the ordering we want for the test.
; DEFAULT-LABEL: {{^}}main: ; DEFAULT-LABEL: {{^}}main:
; DEFAULT: s_load_dwordx4 ; DEFAULT: s_load_dwordx4
; DEFAULT: s_load_dwordx4 ; DEFAULT: s_load_dwordx4
; DEFAULT: s_waitcnt vmcnt(0) ; DEFAULT: s_waitcnt vmcnt(0)
; DEFAULT: exp ; DEFAULT: exp
; DEFAULT: s_waitcnt lgkmcnt(0) ; DEFAULT: s_waitcnt lgkmcnt(0)
; DEFAULT: s_endpgm ; DEFAULT: s_endpgm
define amdgpu_vs void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) #0 { define amdgpu_vs void @main(<16 x i8> addrspace(4)* inreg %arg, <16 x i8> addrspace(4)* inreg %arg1, <32 x i8> addrspace(4)* inreg %arg2, <16 x i8> addrspace(4)* inreg %arg3, <16 x i8> addrspace(4)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(4)* inreg %constptr) #0 {
main_body: main_body:
%tmp = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 0 %tmp = getelementptr <16 x i8>, <16 x i8> addrspace(4)* %arg3, i32 0
%tmp10 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, !tbaa !0 %tmp10 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp, !tbaa !0
%tmp10.cast = bitcast <16 x i8> %tmp10 to <4 x i32> %tmp10.cast = bitcast <16 x i8> %tmp10 to <4 x i32>
%tmp11 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp10.cast, i32 %arg6, i32 0, i1 false, i1 false) %tmp11 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp10.cast, i32 %arg6, i32 0, i1 false, i1 false)
%tmp12 = extractelement <4 x float> %tmp11, i32 0 %tmp12 = extractelement <4 x float> %tmp11, i32 0
%tmp13 = extractelement <4 x float> %tmp11, i32 1 %tmp13 = extractelement <4 x float> %tmp11, i32 1
call void @llvm.amdgcn.s.barrier() #1 call void @llvm.amdgcn.s.barrier() #1
%tmp14 = extractelement <4 x float> %tmp11, i32 2 %tmp14 = extractelement <4 x float> %tmp11, i32 2
%tmp15 = load float, float addrspace(2)* %constptr, align 4 %tmp15 = load float, float addrspace(4)* %constptr, align 4
%tmp16 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %arg3, i32 1 %tmp16 = getelementptr <16 x i8>, <16 x i8> addrspace(4)* %arg3, i32 1
%tmp17 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp16, !tbaa !0 %tmp17 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp16, !tbaa !0
%tmp17.cast = bitcast <16 x i8> %tmp17 to <4 x i32> %tmp17.cast = bitcast <16 x i8> %tmp17 to <4 x i32>
%tmp18 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp17.cast, i32 %arg6, i32 0, i1 false, i1 false) %tmp18 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp17.cast, i32 %arg6, i32 0, i1 false, i1 false)
%tmp19 = extractelement <4 x float> %tmp18, i32 0 %tmp19 = extractelement <4 x float> %tmp18, i32 0
%tmp20 = extractelement <4 x float> %tmp18, i32 1 %tmp20 = extractelement <4 x float> %tmp18, i32 1
%tmp21 = extractelement <4 x float> %tmp18, i32 2 %tmp21 = extractelement <4 x float> %tmp18, i32 2
%tmp22 = extractelement <4 x float> %tmp18, i32 3 %tmp22 = extractelement <4 x float> %tmp18, i32 3
call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp19, float %tmp20, float %tmp21, float %tmp22, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 32, i32 15, float %tmp19, float %tmp20, float %tmp21, float %tmp22, i1 false, i1 false) #0
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp12, float %tmp13, float %tmp14, float %tmp15, i1 true, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp12, float %tmp13, float %tmp14, float %tmp15, i1 true, i1 false) #0
ret void ret void
} }
; ILPMAX-LABEL: {{^}}main2: ; ILPMAX-LABEL: {{^}}main2:
; ILPMAX: s_load_dwordx4 ; ILPMAX: s_load_dwordx4
; ILPMAX: s_waitcnt lgkmcnt(0) ; ILPMAX: s_waitcnt lgkmcnt(0)
; ILPMAX: buffer_load ; ILPMAX: buffer_load
; ILPMAX: s_load_dwordx4 ; ILPMAX: s_load_dwordx4
; ILPMAX: s_waitcnt lgkmcnt(0) ; ILPMAX: s_waitcnt lgkmcnt(0)
; ILPMAX: buffer_load ; ILPMAX: buffer_load
; ILPMAX: s_waitcnt vmcnt(0) ; ILPMAX: s_waitcnt vmcnt(0)
; ILPMAX: exp pos0 ; ILPMAX: exp pos0
; ILPMAX-NEXT: exp param0 ; ILPMAX-NEXT: exp param0
; ILPMAX: s_endpgm ; ILPMAX: s_endpgm
define amdgpu_vs void @main2([6 x <16 x i8>] addrspace(2)* byval %arg, [17 x <16 x i8>] addrspace(2)* byval %arg1, [17 x <4 x i32>] addrspace(2)* byval %arg2, [34 x <8 x i32>] addrspace(2)* byval %arg3, [16 x <16 x i8>] addrspace(2)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 { define amdgpu_vs void @main2([6 x <16 x i8>] addrspace(4)* byval %arg, [17 x <16 x i8>] addrspace(4)* byval %arg1, [17 x <4 x i32>] addrspace(4)* byval %arg2, [34 x <8 x i32>] addrspace(4)* byval %arg3, [16 x <16 x i8>] addrspace(4)* byval %arg4, i32 inreg %arg5, i32 inreg %arg6, i32 %arg7, i32 %arg8, i32 %arg9, i32 %arg10) #0 {
main_body: main_body:
%tmp = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %arg4, i64 0, i64 0 %tmp = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(4)* %arg4, i64 0, i64 0
%tmp11 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp, align 16, !tbaa !0 %tmp11 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp, align 16, !tbaa !0
%tmp12 = add i32 %arg5, %arg7 %tmp12 = add i32 %arg5, %arg7
%tmp11.cast = bitcast <16 x i8> %tmp11 to <4 x i32> %tmp11.cast = bitcast <16 x i8> %tmp11 to <4 x i32>
%tmp13 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp11.cast, i32 %tmp12, i32 0, i1 false, i1 false) %tmp13 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp11.cast, i32 %tmp12, i32 0, i1 false, i1 false)
%tmp14 = extractelement <4 x float> %tmp13, i32 0 %tmp14 = extractelement <4 x float> %tmp13, i32 0
%tmp15 = extractelement <4 x float> %tmp13, i32 1 %tmp15 = extractelement <4 x float> %tmp13, i32 1
%tmp16 = extractelement <4 x float> %tmp13, i32 2 %tmp16 = extractelement <4 x float> %tmp13, i32 2
%tmp17 = extractelement <4 x float> %tmp13, i32 3 %tmp17 = extractelement <4 x float> %tmp13, i32 3
%tmp18 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(2)* %arg4, i64 0, i64 1 %tmp18 = getelementptr [16 x <16 x i8>], [16 x <16 x i8>] addrspace(4)* %arg4, i64 0, i64 1
%tmp19 = load <16 x i8>, <16 x i8> addrspace(2)* %tmp18, align 16, !tbaa !0 %tmp19 = load <16 x i8>, <16 x i8> addrspace(4)* %tmp18, align 16, !tbaa !0
%tmp20 = add i32 %arg5, %arg7 %tmp20 = add i32 %arg5, %arg7
%tmp19.cast = bitcast <16 x i8> %tmp19 to <4 x i32> %tmp19.cast = bitcast <16 x i8> %tmp19 to <4 x i32>
%tmp21 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp19.cast, i32 %tmp20, i32 0, i1 false, i1 false) %tmp21 = call <4 x float> @llvm.amdgcn.buffer.load.format.v4f32(<4 x i32> %tmp19.cast, i32 %tmp20, i32 0, i1 false, i1 false)
%tmp22 = extractelement <4 x float> %tmp21, i32 0 %tmp22 = extractelement <4 x float> %tmp21, i32 0
%tmp23 = extractelement <4 x float> %tmp21, i32 1 %tmp23 = extractelement <4 x float> %tmp21, i32 1
%tmp24 = extractelement <4 x float> %tmp21, i32 2 %tmp24 = extractelement <4 x float> %tmp21, i32 2
%tmp25 = extractelement <4 x float> %tmp21, i32 3 %tmp25 = extractelement <4 x float> %tmp21, i32 3
call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp14, float %tmp15, float %tmp16, float %tmp17, i1 false, i1 false) #0 call void @llvm.amdgcn.exp.f32(i32 12, i32 15, float %tmp14, float %tmp15, float %tmp16, float %tmp17, i1 false, i1 false) #0
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test/CodeGen/AMDGPU/waitcnt-looptest.ll

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define amdgpu_kernel void @testKernel(i32 addrspace(1)* nocapture %arg) local_unnamed_addr #0 { define amdgpu_kernel void @testKernel(i32 addrspace(1)* nocapture %arg) local_unnamed_addr #0 {
bb: bb:
store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_generic to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4 store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_generic to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4
store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_reference to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4 store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_reference to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4
br label %bb18 br label %bb18
bb1: ; preds = %bb18 bb1: ; preds = %bb18
%tmp = tail call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %tmp = tail call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%tmp2 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp3 = tail call i32 @llvm.amdgcn.workgroup.id.x() %tmp3 = tail call i32 @llvm.amdgcn.workgroup.id.x()
%tmp4 = getelementptr inbounds i8, i8 addrspace(2)* %tmp, i64 4 %tmp4 = getelementptr inbounds i8, i8 addrspace(4)* %tmp, i64 4
%tmp5 = bitcast i8 addrspace(2)* %tmp4 to i16 addrspace(2)* %tmp5 = bitcast i8 addrspace(4)* %tmp4 to i16 addrspace(4)*
%tmp6 = load i16, i16 addrspace(2)* %tmp5, align 4 %tmp6 = load i16, i16 addrspace(4)* %tmp5, align 4
%tmp7 = zext i16 %tmp6 to i32 %tmp7 = zext i16 %tmp6 to i32
%tmp8 = mul i32 %tmp3, %tmp7 %tmp8 = mul i32 %tmp3, %tmp7
%tmp9 = add i32 %tmp8, %tmp2 %tmp9 = add i32 %tmp8, %tmp2
%tmp10 = tail call i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() %tmp10 = tail call i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr()
%tmp11 = zext i32 %tmp9 to i64 %tmp11 = zext i32 %tmp9 to i64
%tmp12 = bitcast i8 addrspace(2)* %tmp10 to i64 addrspace(2)* %tmp12 = bitcast i8 addrspace(4)* %tmp10 to i64 addrspace(4)*
%tmp13 = load i64, i64 addrspace(2)* %tmp12, align 8 %tmp13 = load i64, i64 addrspace(4)* %tmp12, align 8
%tmp14 = add i64 %tmp13, %tmp11 %tmp14 = add i64 %tmp13, %tmp11
%tmp15 = zext i1 %tmp99 to i32 %tmp15 = zext i1 %tmp99 to i32
%tmp16 = and i64 %tmp14, 4294967295 %tmp16 = and i64 %tmp14, 4294967295
%tmp17 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp16 %tmp17 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp16
store i32 %tmp15, i32 addrspace(1)* %tmp17, align 4 store i32 %tmp15, i32 addrspace(1)* %tmp17, align 4
ret void ret void
bb18: ; preds = %bb18, %bb bb18: ; preds = %bb18, %bb
▲ Show 20 Lines • Show All 80 Lines • ▼ Show 20 Linesbb18: ; preds = %bb18, %bb
%tmp99 = and i1 %tmp91, %tmp98 %tmp99 = and i1 %tmp91, %tmp98
%tmp100 = add nuw nsw i32 %tmp20, 10 %tmp100 = add nuw nsw i32 %tmp20, 10
%tmp101 = icmp eq i32 %tmp100, 100 %tmp101 = icmp eq i32 %tmp100, 100
%tmp102 = sext i32 %tmp100 to i64 %tmp102 = sext i32 %tmp100 to i64
br i1 %tmp101, label %bb1, label %bb18 br i1 %tmp101, label %bb1, label %bb18
} }
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #1
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare i32 @llvm.amdgcn.workgroup.id.x() #1 declare i32 @llvm.amdgcn.workgroup.id.x() #1
; Function Attrs: nounwind readnone speculatable ; Function Attrs: nounwind readnone speculatable
declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #1 declare i8 addrspace(4)* @llvm.amdgcn.implicitarg.ptr() #1
attributes #0 = { "target-cpu"="fiji" "target-features"="-flat-for-global" } attributes #0 = { "target-cpu"="fiji" "target-features"="-flat-for-global" }
attributes #1 = { nounwind readnone speculatable } attributes #1 = { nounwind readnone speculatable }

test/CodeGen/AMDGPU/widen_extending_scalar_loads.ll

; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare < %s | FileCheck -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare < %s | FileCheck -check-prefix=OPT %s
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 declare i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr() #0
; OPT-LABEL: @constant_load_i1 ; OPT-LABEL: @constant_load_i1
; OPT: load i1 ; OPT: load i1
; OPT-NEXT: store i1 ; OPT-NEXT: store i1
define amdgpu_kernel void @constant_load_i1(i1 addrspace(1)* %out, i1 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i1(i1 addrspace(1)* %out, i1 addrspace(4)* %in) #0 {
%val = load i1, i1 addrspace(2)* %in %val = load i1, i1 addrspace(4)* %in
store i1 %val, i1 addrspace(1)* %out store i1 %val, i1 addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_i1_align2 ; OPT-LABEL: @constant_load_i1_align2
; OPT: load i1 ; OPT: load i1
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_i1_align2(i1 addrspace(1)* %out, i1 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i1_align2(i1 addrspace(1)* %out, i1 addrspace(4)* %in) #0 {
%val = load i1, i1 addrspace(2)* %in, align 2 %val = load i1, i1 addrspace(4)* %in, align 2
store i1 %val, i1 addrspace(1)* %out, align 2 store i1 %val, i1 addrspace(1)* %out, align 2
ret void ret void
} }
; OPT-LABEL: @constant_load_i1_align4 ; OPT-LABEL: @constant_load_i1_align4
; OPT: bitcast ; OPT: bitcast
; OPT-NEXT: load i32 ; OPT-NEXT: load i32
; OPT-NEXT: trunc ; OPT-NEXT: trunc
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_i1_align4(i1 addrspace(1)* %out, i1 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i1_align4(i1 addrspace(1)* %out, i1 addrspace(4)* %in) #0 {
%val = load i1, i1 addrspace(2)* %in, align 4 %val = load i1, i1 addrspace(4)* %in, align 4
store i1 %val, i1 addrspace(1)* %out, align 4 store i1 %val, i1 addrspace(1)* %out, align 4
ret void ret void
} }
; OPT-LABEL: @constant_load_i8 ; OPT-LABEL: @constant_load_i8
; OPT: load i8 ; OPT: load i8
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_i8(i8 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i8(i8 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%val = load i8, i8 addrspace(2)* %in %val = load i8, i8 addrspace(4)* %in
store i8 %val, i8 addrspace(1)* %out store i8 %val, i8 addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_i8_align2 ; OPT-LABEL: @constant_load_i8_align2
; OPT: load i8 ; OPT: load i8
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_i8_align2(i8 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i8_align2(i8 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%val = load i8, i8 addrspace(2)* %in, align 2 %val = load i8, i8 addrspace(4)* %in, align 2
store i8 %val, i8 addrspace(1)* %out, align 2 store i8 %val, i8 addrspace(1)* %out, align 2
ret void ret void
} }
; OPT-LABEL: @constant_load_i8align4 ; OPT-LABEL: @constant_load_i8align4
; OPT: bitcast ; OPT: bitcast
; OPT-NEXT: load i32 ; OPT-NEXT: load i32
; OPT-NEXT: trunc ; OPT-NEXT: trunc
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_i8align4(i8 addrspace(1)* %out, i8 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i8align4(i8 addrspace(1)* %out, i8 addrspace(4)* %in) #0 {
%val = load i8, i8 addrspace(2)* %in, align 4 %val = load i8, i8 addrspace(4)* %in, align 4
store i8 %val, i8 addrspace(1)* %out, align 4 store i8 %val, i8 addrspace(1)* %out, align 4
ret void ret void
} }
; OPT-LABEL: @constant_load_v2i8 ; OPT-LABEL: @constant_load_v2i8
; OPT: load <2 x i8> ; OPT: load <2 x i8>
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v2i8(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%ld = load <2 x i8>, <2 x i8> addrspace(2)* %in %ld = load <2 x i8>, <2 x i8> addrspace(4)* %in
store <2 x i8> %ld, <2 x i8> addrspace(1)* %out store <2 x i8> %ld, <2 x i8> addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_v2i8_align4 ; OPT-LABEL: @constant_load_v2i8_align4
; OPT: bitcast ; OPT: bitcast
; OPT-NEXT: load i32 ; OPT-NEXT: load i32
; OPT-NEXT: trunc ; OPT-NEXT: trunc
; OPT-NEXT: bitcast ; OPT-NEXT: bitcast
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_v2i8_align4(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v2i8_align4(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%ld = load <2 x i8>, <2 x i8> addrspace(2)* %in, align 4 %ld = load <2 x i8>, <2 x i8> addrspace(4)* %in, align 4
store <2 x i8> %ld, <2 x i8> addrspace(1)* %out, align 4 store <2 x i8> %ld, <2 x i8> addrspace(1)* %out, align 4
ret void ret void
} }
; OPT-LABEL: @constant_load_v3i8 ; OPT-LABEL: @constant_load_v3i8
; OPT: bitcast <3 x i8> ; OPT: bitcast <3 x i8>
; OPT-NEXT: load i32, i32 addrspace(2) ; OPT-NEXT: load i32, i32 addrspace(4)
; OPT-NEXT: trunc i32 ; OPT-NEXT: trunc i32
; OPT-NEXT: bitcast i24 ; OPT-NEXT: bitcast i24
; OPT-NEXT: store <3 x i8> ; OPT-NEXT: store <3 x i8>
define amdgpu_kernel void @constant_load_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v3i8(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(4)* %in) #0 {
%ld = load <3 x i8>, <3 x i8> addrspace(2)* %in %ld = load <3 x i8>, <3 x i8> addrspace(4)* %in
store <3 x i8> %ld, <3 x i8> addrspace(1)* %out store <3 x i8> %ld, <3 x i8> addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_v3i8_align4 ; OPT-LABEL: @constant_load_v3i8_align4
; OPT: bitcast <3 x i8> ; OPT: bitcast <3 x i8>
; OPT-NEXT: load i32, i32 addrspace(2) ; OPT-NEXT: load i32, i32 addrspace(4)
; OPT-NEXT: trunc i32 ; OPT-NEXT: trunc i32
; OPT-NEXT: bitcast i24 ; OPT-NEXT: bitcast i24
; OPT-NEXT: store <3 x i8> ; OPT-NEXT: store <3 x i8>
define amdgpu_kernel void @constant_load_v3i8_align4(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v3i8_align4(<3 x i8> addrspace(1)* %out, <3 x i8> addrspace(4)* %in) #0 {
%ld = load <3 x i8>, <3 x i8> addrspace(2)* %in, align 4 %ld = load <3 x i8>, <3 x i8> addrspace(4)* %in, align 4
store <3 x i8> %ld, <3 x i8> addrspace(1)* %out, align 4 store <3 x i8> %ld, <3 x i8> addrspace(1)* %out, align 4
ret void ret void
} }
; OPT-LABEL: @constant_load_i16 ; OPT-LABEL: @constant_load_i16
; OPT: load i16 ; OPT: load i16
; OPT: sext ; OPT: sext
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_i16(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i16(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
%ld = load i16, i16 addrspace(2)* %in %ld = load i16, i16 addrspace(4)* %in
%ext = sext i16 %ld to i32 %ext = sext i16 %ld to i32
store i32 %ext, i32 addrspace(1)* %out store i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_i16_align4 ; OPT-LABEL: @constant_load_i16_align4
; OPT: bitcast ; OPT: bitcast
; OPT-NEXT: load i32 ; OPT-NEXT: load i32
; OPT-NEXT: trunc ; OPT-NEXT: trunc
; OPT-NEXT: sext ; OPT-NEXT: sext
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_i16_align4(i32 addrspace(1)* %out, i16 addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_i16_align4(i32 addrspace(1)* %out, i16 addrspace(4)* %in) #0 {
%ld = load i16, i16 addrspace(2)* %in, align 4 %ld = load i16, i16 addrspace(4)* %in, align 4
%ext = sext i16 %ld to i32 %ext = sext i16 %ld to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; OPT-LABEL: @constant_load_f16 ; OPT-LABEL: @constant_load_f16
; OPT: load half ; OPT: load half
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_f16(half addrspace(1)* %out, half addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_f16(half addrspace(1)* %out, half addrspace(4)* %in) #0 {
%ld = load half, half addrspace(2)* %in %ld = load half, half addrspace(4)* %in
store half %ld, half addrspace(1)* %out store half %ld, half addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_v2f16 ; OPT-LABEL: @constant_load_v2f16
; OPT: load <2 x half> ; OPT: load <2 x half>
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v2f16(<2 x half> addrspace(1)* %out, <2 x half> addrspace(4)* %in) #0 {
%ld = load <2 x half>, <2 x half> addrspace(2)* %in %ld = load <2 x half>, <2 x half> addrspace(4)* %in
store <2 x half> %ld, <2 x half> addrspace(1)* %out store <2 x half> %ld, <2 x half> addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @load_volatile ; OPT-LABEL: @load_volatile
; OPT: load volatile i16 ; OPT: load volatile i16
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @load_volatile(i16 addrspace(1)* %out, i16 addrspace(2)* %in) { define amdgpu_kernel void @load_volatile(i16 addrspace(1)* %out, i16 addrspace(4)* %in) {
%a = load volatile i16, i16 addrspace(2)* %in %a = load volatile i16, i16 addrspace(4)* %in
store i16 %a, i16 addrspace(1)* %out store i16 %a, i16 addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_v2i8_volatile ; OPT-LABEL: @constant_load_v2i8_volatile
; OPT: load volatile <2 x i8> ; OPT: load volatile <2 x i8>
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_v2i8_volatile(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(2)* %in) #0 { define amdgpu_kernel void @constant_load_v2i8_volatile(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(4)* %in) #0 {
%ld = load volatile <2 x i8>, <2 x i8> addrspace(2)* %in %ld = load volatile <2 x i8>, <2 x i8> addrspace(4)* %in
store <2 x i8> %ld, <2 x i8> addrspace(1)* %out store <2 x i8> %ld, <2 x i8> addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @constant_load_v2i8_addrspace1 ; OPT-LABEL: @constant_load_v2i8_addrspace1
; OPT: load <2 x i8> ; OPT: load <2 x i8>
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @constant_load_v2i8_addrspace1(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 { define amdgpu_kernel void @constant_load_v2i8_addrspace1(<2 x i8> addrspace(1)* %out, <2 x i8> addrspace(1)* %in) #0 {
%ld = load <2 x i8>, <2 x i8> addrspace(1)* %in %ld = load <2 x i8>, <2 x i8> addrspace(1)* %in
store <2 x i8> %ld, <2 x i8> addrspace(1)* %out store <2 x i8> %ld, <2 x i8> addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @use_dispatch_ptr ; OPT-LABEL: @use_dispatch_ptr
; OPT: bitcast ; OPT: bitcast
; OPT-NEXT: load i32 ; OPT-NEXT: load i32
; OPT-NEXT: trunc ; OPT-NEXT: trunc
; OPT-NEXT: zext ; OPT-NEXT: zext
; OPT-NEXT: store ; OPT-NEXT: store
define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_dispatch_ptr(i32 addrspace(1)* %ptr) #1 {
%dispatch.ptr = call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %dispatch.ptr = call i8 addrspace(4)* @llvm.amdgcn.dispatch.ptr()
%val = load i8, i8 addrspace(2)* %dispatch.ptr, align 4 %val = load i8, i8 addrspace(4)* %dispatch.ptr, align 4
%ld = zext i8 %val to i32 %ld = zext i8 %val to i32
store i32 %ld, i32 addrspace(1)* %ptr store i32 %ld, i32 addrspace(1)* %ptr
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/Transforms/SeparateConstOffsetFromGEP/AMDGPU/split-gep-and-gvn-addrspace-addressing-modes.ll

; RUN: opt -mtriple=amdgcn-- -S -separate-const-offset-from-gep -reassociate-geps-verify-no-dead-code -gvn < %s | FileCheck -check-prefix=IR %s ; RUN: opt -mtriple=amdgcn-- -S -separate-const-offset-from-gep -reassociate-geps-verify-no-dead-code -gvn < %s | FileCheck -check-prefix=IR %s
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
@array = internal addrspace(2) constant [4096 x [32 x float]] zeroinitializer, align 4 @array = internal addrspace(4) constant [4096 x [32 x float]] zeroinitializer, align 4
; IR-LABEL: @sum_of_array( ; IR-LABEL: @sum_of_array(
; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [4096 x [32 x float]], [4096 x [32 x float]] addrspace(2)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [4096 x [32 x float]], [4096 x [32 x float]] addrspace(4)* @array, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 1 ; IR: getelementptr inbounds float, float addrspace(4)* [[BASE_PTR]], i64 1
; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 32 ; IR: getelementptr inbounds float, float addrspace(4)* [[BASE_PTR]], i64 32
; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 33 ; IR: getelementptr inbounds float, float addrspace(4)* [[BASE_PTR]], i64 33
define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, float addrspace(1)* nocapture %output) { define amdgpu_kernel void @sum_of_array(i32 %x, i32 %y, float addrspace(1)* nocapture %output) {
%tmp = sext i32 %y to i64 %tmp = sext i32 %y to i64
%tmp1 = sext i32 %x to i64 %tmp1 = sext i32 %x to i64
%tmp2 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(2)* @array, i64 0, i64 %tmp1, i64 %tmp %tmp2 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(4)* @array, i64 0, i64 %tmp1, i64 %tmp
%tmp4 = load float, float addrspace(2)* %tmp2, align 4 %tmp4 = load float, float addrspace(4)* %tmp2, align 4
%tmp5 = fadd float %tmp4, 0.000000e+00 %tmp5 = fadd float %tmp4, 0.000000e+00
%tmp6 = add i32 %y, 1 %tmp6 = add i32 %y, 1
%tmp7 = sext i32 %tmp6 to i64 %tmp7 = sext i32 %tmp6 to i64
%tmp8 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(2)* @array, i64 0, i64 %tmp1, i64 %tmp7 %tmp8 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(4)* @array, i64 0, i64 %tmp1, i64 %tmp7
%tmp10 = load float, float addrspace(2)* %tmp8, align 4 %tmp10 = load float, float addrspace(4)* %tmp8, align 4
%tmp11 = fadd float %tmp5, %tmp10 %tmp11 = fadd float %tmp5, %tmp10
%tmp12 = add i32 %x, 1 %tmp12 = add i32 %x, 1
%tmp13 = sext i32 %tmp12 to i64 %tmp13 = sext i32 %tmp12 to i64
%tmp14 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(2)* @array, i64 0, i64 %tmp13, i64 %tmp %tmp14 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(4)* @array, i64 0, i64 %tmp13, i64 %tmp
%tmp16 = load float, float addrspace(2)* %tmp14, align 4 %tmp16 = load float, float addrspace(4)* %tmp14, align 4
%tmp17 = fadd float %tmp11, %tmp16 %tmp17 = fadd float %tmp11, %tmp16
%tmp18 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(2)* @array, i64 0, i64 %tmp13, i64 %tmp7 %tmp18 = getelementptr inbounds [4096 x [32 x float]], [4096 x [32 x float]] addrspace(4)* @array, i64 0, i64 %tmp13, i64 %tmp7
%tmp20 = load float, float addrspace(2)* %tmp18, align 4 %tmp20 = load float, float addrspace(4)* %tmp18, align 4
%tmp21 = fadd float %tmp17, %tmp20 %tmp21 = fadd float %tmp17, %tmp20
store float %tmp21, float addrspace(1)* %output, align 4 store float %tmp21, float addrspace(1)* %output, align 4
ret void ret void
} }
@array2 = internal addrspace(2) constant [4096 x [4 x float]] zeroinitializer, align 4 @array2 = internal addrspace(4) constant [4096 x [4 x float]] zeroinitializer, align 4
; Some of the indices go over the maximum mubuf offset, so don't split them. ; Some of the indices go over the maximum mubuf offset, so don't split them.
; IR-LABEL: @sum_of_array_over_max_mubuf_offset( ; IR-LABEL: @sum_of_array_over_max_mubuf_offset(
; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: [[BASE_PTR:%[a-zA-Z0-9]+]] = getelementptr [4096 x [4 x float]], [4096 x [4 x float]] addrspace(4)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
; IR: getelementptr inbounds float, float addrspace(2)* [[BASE_PTR]], i64 255 ; IR: getelementptr inbounds float, float addrspace(4)* [[BASE_PTR]], i64 255
; IR: add i32 %x, 256 ; IR: add i32 %x, 256
; IR: getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(4)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
; IR: getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}} ; IR: getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(4)* @array2, i64 0, i64 %{{[a-zA-Z0-9]+}}, i64 %{{[a-zA-Z0-9]+}}
define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, float addrspace(1)* nocapture %output) { define amdgpu_kernel void @sum_of_array_over_max_mubuf_offset(i32 %x, i32 %y, float addrspace(1)* nocapture %output) {
%tmp = sext i32 %y to i64 %tmp = sext i32 %y to i64
%tmp1 = sext i32 %x to i64 %tmp1 = sext i32 %x to i64
%tmp2 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %tmp1, i64 %tmp %tmp2 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(4)* @array2, i64 0, i64 %tmp1, i64 %tmp
%tmp4 = load float, float addrspace(2)* %tmp2, align 4 %tmp4 = load float, float addrspace(4)* %tmp2, align 4
%tmp5 = fadd float %tmp4, 0.000000e+00 %tmp5 = fadd float %tmp4, 0.000000e+00
%tmp6 = add i32 %y, 255 %tmp6 = add i32 %y, 255
%tmp7 = sext i32 %tmp6 to i64 %tmp7 = sext i32 %tmp6 to i64
%tmp8 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %tmp1, i64 %tmp7 %tmp8 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(4)* @array2, i64 0, i64 %tmp1, i64 %tmp7
%tmp10 = load float, float addrspace(2)* %tmp8, align 4 %tmp10 = load float, float addrspace(4)* %tmp8, align 4
%tmp11 = fadd float %tmp5, %tmp10 %tmp11 = fadd float %tmp5, %tmp10
%tmp12 = add i32 %x, 256 %tmp12 = add i32 %x, 256
%tmp13 = sext i32 %tmp12 to i64 %tmp13 = sext i32 %tmp12 to i64
%tmp14 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %tmp13, i64 %tmp %tmp14 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(4)* @array2, i64 0, i64 %tmp13, i64 %tmp
%tmp16 = load float, float addrspace(2)* %tmp14, align 4 %tmp16 = load float, float addrspace(4)* %tmp14, align 4
%tmp17 = fadd float %tmp11, %tmp16 %tmp17 = fadd float %tmp11, %tmp16
%tmp18 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(2)* @array2, i64 0, i64 %tmp13, i64 %tmp7 %tmp18 = getelementptr inbounds [4096 x [4 x float]], [4096 x [4 x float]] addrspace(4)* @array2, i64 0, i64 %tmp13, i64 %tmp7
%tmp20 = load float, float addrspace(2)* %tmp18, align 4 %tmp20 = load float, float addrspace(4)* %tmp18, align 4
%tmp21 = fadd float %tmp17, %tmp20 %tmp21 = fadd float %tmp17, %tmp20
store float %tmp21, float addrspace(1)* %output, align 4 store float %tmp21, float addrspace(1)* %output, align 4
ret void ret void
} }
@lds_array = internal addrspace(3) global [4096 x [4 x float]] undef, align 4 @lds_array = internal addrspace(3) global [4096 x [4 x float]] undef, align 4
Show All 21 Linesdefine amdgpu_kernel void @sum_of_lds_array_over_max_mubuf_offset(i32 %x, i32 %y, float addrspace(1)* nocapture %output) {
store float %tmp21, float addrspace(1)* %output, align 4 store float %tmp21, float addrspace(1)* %output, align 4
ret void ret void
} }
; IR-LABEL: @keep_metadata( ; IR-LABEL: @keep_metadata(
; IR: getelementptr {{.*}} !amdgpu.uniform ; IR: getelementptr {{.*}} !amdgpu.uniform
; IR: getelementptr {{.*}} !amdgpu.uniform ; IR: getelementptr {{.*}} !amdgpu.uniform
; IR: getelementptr {{.*}} !amdgpu.uniform ; IR: getelementptr {{.*}} !amdgpu.uniform
define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata([0 x <4 x i32>] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), [0 x <4 x i32>] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(2)* inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 { define amdgpu_ps <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> @keep_metadata([0 x <4 x i32>] addrspace(4)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(4)* inreg noalias dereferenceable(18446744073709551615), [0 x <4 x i32>] addrspace(4)* inreg noalias dereferenceable(18446744073709551615), [0 x <8 x i32>] addrspace(4)* inreg noalias dereferenceable(18446744073709551615), float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, i32, i32, float, i32) #5 {
main_body: main_body:
%22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8 %22 = call nsz float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %5) #8
%23 = bitcast float %22 to i32 %23 = bitcast float %22 to i32
%24 = shl i32 %23, 1 %24 = shl i32 %23, 1
%25 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(2)* %1, i32 0, i32 %24, !amdgpu.uniform !0 %25 = getelementptr [0 x <8 x i32>], [0 x <8 x i32>] addrspace(4)* %1, i32 0, i32 %24, !amdgpu.uniform !0
%26 = load <8 x i32>, <8 x i32> addrspace(2)* %25, align 32, !invariant.load !0 %26 = load <8 x i32>, <8 x i32> addrspace(4)* %25, align 32, !invariant.load !0
%27 = shl i32 %23, 2 %27 = shl i32 %23, 2
%28 = or i32 %27, 3 %28 = or i32 %27, 3
%29 = bitcast [0 x <8 x i32>] addrspace(2)* %1 to [0 x <4 x i32>] addrspace(2)* %29 = bitcast [0 x <8 x i32>] addrspace(4)* %1 to [0 x <4 x i32>] addrspace(4)*
%30 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(2)* %29, i32 0, i32 %28, !amdgpu.uniform !0 %30 = getelementptr [0 x <4 x i32>], [0 x <4 x i32>] addrspace(4)* %29, i32 0, i32 %28, !amdgpu.uniform !0
%31 = load <4 x i32>, <4 x i32> addrspace(2)* %30, align 16, !invariant.load !0 %31 = load <4 x i32>, <4 x i32> addrspace(4)* %30, align 16, !invariant.load !0
%32 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> %26, <4 x i32> %31, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #8 %32 = call nsz <4 x float> @llvm.amdgcn.image.sample.v4f32.v2f32.v8i32(<2 x float> zeroinitializer, <8 x i32> %26, <4 x i32> %31, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #8
%33 = extractelement <4 x float> %32, i32 0 %33 = extractelement <4 x float> %32, i32 0
%34 = extractelement <4 x float> %32, i32 1 %34 = extractelement <4 x float> %32, i32 1
%35 = extractelement <4 x float> %32, i32 2 %35 = extractelement <4 x float> %32, i32 2
%36 = extractelement <4 x float> %32, i32 3 %36 = extractelement <4 x float> %32, i32 3
%37 = bitcast float %4 to i32 %37 = bitcast float %4 to i32
%38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %37, 4 %38 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> undef, i32 %37, 4
%39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 5 %39 = insertvalue <{ i32, i32, i32, i32, i32, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float }> %38, float %33, 5
Show All 20 Lines