[ARM] f16 conversions

[SjoerdMeijer]

Summary

This is a follow up of r324321, adding f16 <-> f32 and f16 <-> f64
conversion match patterns.

[olista01]

lib/Target/ARM/ARMInstrVFP.td

682 ↗

(On Diff #132970)

The instruction only requires HasFP16, so why does the pattern need FullFP16? (same question multiple times in this file)

694 ↗

(On Diff #132970)

Should this COPY_TO_REGCLASS target HPR, since the output is an f16?

725 ↗

(On Diff #132970)

VCVTBHD takes the input in an SPR, so should the COPY_TO_REGCLASS target SPR?

test/CodeGen/ARM/fp16-instructions.ll

237 ↗

(On Diff #132970)

It would be better to have each test in its own function, rather then combining them like this.

[SjoerdMeijer]

Addressed comments.

About:

The instruction only requires HasFP16, so why does the pattern need FullFP16? (same question multiple times in this file)

What we are doing here, is "driving" one instruction description by 2 rewrite patterns:
one for FP16, and the other for FullFP16. The pattern names "FullFP16Pat"" and
"FullFP16Pat" are mainly there just to make to make explicit when we are using these
rules. I agree that this is instruction does not FullFP16, so I could remove the predicate
from the pattern definition:

class FullFP16Pat<dag pattern, dag result> : Pat<pattern, result> {
  list<Predicate> Predicates = [HasFullFP16];
}

But as the rewrite rule is using the HPR register class, which is added only when we
have FullFP16 support, I thought it would be good to have it.

[olista01]

Thanks, LGTM.

llvm/trunk/lib/Target/ARM/ARMInstrVFP.td

def VCVTSD  : VFPAI<(outs SPR:$Sd), (ins DPR:$Dm), VFPUnaryFrm,
   let Inst{4}     = 0;
 
   let Predicates = [HasVFP2, HasDPVFP];
 }
 
 // Between half, single and double-precision.
 def VCVTBHS: ASuI<0b11101, 0b11, 0b0010, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTSH, "vcvtb", ".f32.f16\t$Sd, $Sm",
-                 [ /* intentionally left blank, see rule below */ ]>,
+                 [/* Intentionally left blank, see patterns below */]>,
                  Requires<[HasFP16]>,
              Sched<[WriteFPCVT]>;
 
 def : FullFP16Pat<(f32 (fpextend HPR:$Sm)),
                   (VCVTBHS (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
+def : FP16Pat<(f16_to_fp GPR:$a),
+              (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
 
 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTHS, "vcvtb", ".f16.f32\t$Sd, $Sm",
-                 []>,
+                 [/* Intentionally left blank, see patterns below */]>,
                  Requires<[HasFP16]>,
              Sched<[WriteFPCVT]>;
 
+def : FullFP16Pat<(f16 (fpround SPR:$Sm)),
+                  (COPY_TO_REGCLASS (VCVTBSH SPR:$Sm), HPR)>;
+def : FP16Pat<(fp_to_f16 SPR:$a),
+              (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
+
 def VCVTTHS: ASuI<0b11101, 0b11, 0b0010, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTSH, "vcvtt", ".f32.f16\t$Sd, $Sm",
                  [/* For disassembly only; pattern left blank */]>,
                  Requires<[HasFP16]>,
              Sched<[WriteFPCVT]>;
 
 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
                  /* FIXME */ IIC_fpCVTHS, "vcvtt", ".f16.f32\t$Sd, $Sm",
                  [/* For disassembly only; pattern left blank */]>,
                  Requires<[HasFP16]>,
             Sched<[WriteFPCVT]>;
 
 def VCVTBHD : ADuI<0b11101, 0b11, 0b0010, 0b01, 0,
                    (outs DPR:$Dd), (ins SPR:$Sm),
                    NoItinerary, "vcvtb", ".f64.f16\t$Dd, $Sm",
-                   []>, Requires<[HasFPARMv8, HasDPVFP]>,
+                   [/* Intentionally left blank, see patterns below */]>,
+                   Requires<[HasFPARMv8, HasDPVFP]>,
               Sched<[WriteFPCVT]> {
   // Instruction operands.
   bits<5> Sm;
 
   // Encode instruction operands.
   let Inst{3-0} = Sm{4-1};
   let Inst{5}   = Sm{0};
 }
 
+def : FullFP16Pat<(f64 (fpextend HPR:$Sm)),
+                  (VCVTBHD (COPY_TO_REGCLASS HPR:$Sm, SPR))>;
+def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
+              (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
+
 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
                    (outs SPR:$Sd), (ins DPR:$Dm),
                    NoItinerary, "vcvtb", ".f16.f64\t$Sd, $Dm",
-                   []>, Requires<[HasFPARMv8, HasDPVFP]> {
+                   [/* Intentionally left blank, see patterns below */]>,
+                   Requires<[HasFPARMv8, HasDPVFP]> {
   // Instruction operands.
   bits<5> Sd;
   bits<5> Dm;
 
   // Encode instruction operands.
   let Inst{3-0}     = Dm{3-0};
   let Inst{5}       = Dm{4};
   let Inst{15-12}   = Sd{4-1};
   let Inst{22}      = Sd{0};
 }
 
+def : FullFP16Pat<(f16 (fpround DPR:$Dm)),
+                  (COPY_TO_REGCLASS (VCVTBDH DPR:$Dm), HPR)>;
+def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
+              (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
+
 def VCVTTHD : ADuI<0b11101, 0b11, 0b0010, 0b11, 0,
                    (outs DPR:$Dd), (ins SPR:$Sm),
                    NoItinerary, "vcvtt", ".f64.f16\t$Dd, $Sm",
                    []>, Requires<[HasFPARMv8, HasDPVFP]> {
   // Instruction operands.
   bits<5> Sm;
 
   // Encode instruction operands.
def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
 
   // Encode instruction operands.
   let Inst{15-12} = Sd{4-1};
   let Inst{22}    = Sd{0};
   let Inst{3-0}   = Dm{3-0};
   let Inst{5}     = Dm{4};
 }
 
-def : FP16Pat<(fp_to_f16 SPR:$a),
-              (i32 (COPY_TO_REGCLASS (VCVTBSH SPR:$a), GPR))>;
-
-def : FP16Pat<(fp_to_f16 (f64 DPR:$a)),
-              (i32 (COPY_TO_REGCLASS (VCVTBDH DPR:$a), GPR))>;
-
-def : FP16Pat<(f16_to_fp GPR:$a),
-              (VCVTBHS (COPY_TO_REGCLASS GPR:$a, SPR))>;
-
-def : FP16Pat<(f64 (f16_to_fp GPR:$a)),
-              (VCVTBHD (COPY_TO_REGCLASS GPR:$a, SPR))>;
-
 multiclass vcvt_inst<string opc, bits<2> rm,
                      SDPatternOperator node = null_frag> {
   let PostEncoderMethod = "", DecoderNamespace = "VFPV8" in {
     def SH : AHuInp<0b11101, 0b11, 0b1100, 0b11, 0,
                     (outs SPR:$Sd), (ins HPR:$Sm),
                     NoItinerary, !strconcat("vcvt", opc, ".s32.f16\t$Sd, $Sm"),
                     []>,
                     Requires<[HasFullFP16]> {

llvm/trunk/test/CodeGen/ARM/fp16-instructions.ll

entry:
   ret float %2
 
 ; CHECK-LABEL:                 SintToH:
 
 ; CHECK-HARDFP-FULLFP16:       vmov  s0, r0
 ; CHECK-HARDFP-FULLFP16-NEXT:  vcvt.f16.s32  s0, s0
 }
 
+define i32 @f2h(float %f) {
+entry:
+  %conv = fptrunc float %f to half
+  %0 = bitcast half %conv to i16
+  %tmp.0.insert.ext = zext i16 %0 to i32
+  ret i32 %tmp.0.insert.ext
+
+; CHECK-LABEL:            f2h:
+; CHECK-HARDFP-FULLFP16:  vcvtb.f16.f32 s0, s0
+}
+
+define float @h2f(i32 %h.coerce) {
+entry:
+  %tmp.0.extract.trunc = trunc i32 %h.coerce to i16
+  %0 = bitcast i16 %tmp.0.extract.trunc to half
+  %conv = fpext half %0 to float
+  ret float %conv
+
+; CHECK-LABEL:            h2f:
+; CHECK-HARDFP-FULLFP16:  vcvtb.f32.f16 s0, s0
+}
+
+
+define double @h2d(i32 %h.coerce) {
+entry:
+  %tmp.0.extract.trunc = trunc i32 %h.coerce to i16
+  %0 = bitcast i16 %tmp.0.extract.trunc to half
+  %conv = fpext half %0 to double
+  ret double %conv
+
+; CHECK-LABEL:            h2d:
+; CHECK-HARDFP-FULLFP16:  vcvtb.f64.f16 d{{.*}}, s{{.}}
+}
+
+define i32 @d2h(double %d) {
+entry:
+  %conv = fptrunc double %d to half
+  %0 = bitcast half %conv to i16
+  %tmp.0.insert.ext = zext i16 %0 to i32
+  ret i32 %tmp.0.insert.ext
+
+; CHECK-LABEL:            d2h:
+; CHECK-HARDFP-FULLFP16:  vcvtb.f16.f64 s0, d{{.*}}
+}
+
 ; TODO:
 ; 7.  VCVTA
 ; 8.  VCVTM
 ; 9.  VCVTN
 ; 10. VCVTP
 ; 11. VCVTR
 
 ; 12. VDIV