[LivePhysRegs] Fix handling of return instructions.

[efriedma]

Summary

See D42509 for the original version of this.

Basically, there are two significant changes to behavior here:

1. addLiveOuts always adds all pristine registers (even if a block has no successors).
2. addLiveOuts and addLiveOutsNoPristines always add all callee-saved registers for return blocks (including conditional return blocks).

I cleaned up the functions a bit to make it clear these properties hold.

[MatzeB]

Argh:

...
    BX_RET 4, killed %cpsr, implicit %r0
    Successors according to CFG: %bb.2(0x40000000 / 0x80000000 = 50.00%)
...

A conditional return statement breaks the whole nice logic of MachineBasicBlock::isReturnBlock() returning true or false, since it's clearly neither in this case...

LLVM CodeGen isn't really prepared for predicated code (= instructions that don't necessarily execute) it seemed fine to me when they are all packaged up in a bundle and reasoning about it as a bundle made sense, but this is turning a sure branch into a possible branch and a fallthrough...

Apart from that I have really bad feelings about us using MI this way, I'm fine to push this as a fix for now.

lib/CodeGen/LivePhysRegs.cpp

228 ↗

(On Diff #131848)

Being how unintuitive all of this turned out to be this deserves a comment!

[kparzysz]

lib/CodeGen/LivePhysRegs.cpp

232 ↗

(On Diff #131848)

Shouldn't we be doing this even for conditional returns?

[efriedma]

lib/CodeGen/LivePhysRegs.cpp

232 ↗

(On Diff #131848)

I... guess so?

I'll try to come up with something more obviously correct.

[efriedma]

Mark all callee-saved regs live in return blocks in addLiveOuts/addLiveOutsNoPristines. Clean up the code to make the behavior more obvious. Rebase patch against trunk, since the original patch was reverted. Update summary.

llvm/trunk/lib/CodeGen/LivePhysRegs.cpp

void LivePhysRegs::addPristines(const MachineFunction &MF) {
   /// Remove the ones that are not saved/restored; they are pristine.
   for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
     Pristine.removeReg(Info.getReg());
   for (MCPhysReg R : Pristine)
     addReg(R);
 }
 
 void LivePhysRegs::addLiveOutsNoPristines(const MachineBasicBlock &MBB) {
-  if (!MBB.succ_empty()) {
-    // To get the live-outs we simply merge the live-ins of all successors.
-    for (const MachineBasicBlock *Succ : MBB.successors())
-      addBlockLiveIns(*Succ);
-  } else if (MBB.isReturnBlock()) {
-    // For the return block: Add all callee saved registers that are saved and
-    // restored (somewhere); This does not include callee saved registers that
-    // are unused and hence not saved and restored; they are called pristine.
+  if (MBB.isReturnBlock()) {
+    // Return blocks are a special case because we currently don't mark up
+    // return instructions completely: specifically, there is no explicit
+    // use for callee-saved registers. So we add all callee saved registers
+    // that are saved and restored (somewhere). This does not include
+    // callee saved registers that are unused and hence not saved and
+    // restored; they are called pristine.
+    // FIXME: PEI should add explicit markings to return instructions
+    // instead of implicitly handling them here.
     const MachineFunction &MF = *MBB.getParent();
     const MachineFrameInfo &MFI = MF.getFrameInfo();
     if (MFI.isCalleeSavedInfoValid()) {
       for (const CalleeSavedInfo &Info : MFI.getCalleeSavedInfo())
         if (Info.isRestored())
           addReg(Info.getReg());
     }
   }
 }
 
 void LivePhysRegs::addLiveOuts(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
-  if (!MBB.succ_empty()) {
-    addPristines(MF);
-    addLiveOutsNoPristines(MBB);
-  } else if (MBB.isReturnBlock()) {
-    // For the return block: Add all callee saved registers.
-    const MachineFrameInfo &MFI = MF.getFrameInfo();
-    if (MFI.isCalleeSavedInfoValid())
-      addCalleeSavedRegs(*this, MF);
-  }
 }
 
 void LivePhysRegs::addLiveIns(const MachineBasicBlock &MBB) {
   const MachineFunction &MF = *MBB.getParent();
   addPristines(MF);
   addBlockLiveIns(MBB);
 }
 

llvm/trunk/test/CodeGen/ARM/pr25838.ll

-; RUN: llc < %s
+; RUN: llc -verify-machineinstrs < %s
 ; PR25838
 
 target triple = "armv7--linux-android"
 
 %0 = type { i32, i32 }
 
 define i32 @foo(%0* readonly) {
   br i1 undef, label %12, label %2

llvm/trunk/test/CodeGen/Thumb/stm-scavenging.ll

+; RUN: llc < %s | FileCheck %s
+target triple = "thumbv6---gnueabi"
+
+; Use STM to save the three registers
+; CHECK-LABEL: use_stm:
+; CHECK: .save   {r7, lr}
+; CHECK: .setfp  r7, sp
+; CHECK: stm r3!, {r0, r1, r2}
+; CHECK: bl throws_1
+define void @use_stm(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr noreturn "no-frame-pointer-elim"="true" {
+entry:
+  %arrayidx = getelementptr inbounds i32, i32* %d, i32 2
+  store i32 %a, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3
+  store i32 %b, i32* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %d, i32 4
+  store i32 %c, i32* %arrayidx2, align 4
+  tail call void @throws_1(i32 %a, i32 %b, i32 %c) noreturn
+  unreachable
+}
+
+; Don't use STM: there is no available register to store
+; the address. We could transform this with some extra math, but
+; that currently isn't implemented.
+; CHECK-LABEL: no_stm:
+; CHECK: .save   {r7, lr}
+; CHECK: .setfp  r7, sp
+; CHECK: str r0,
+; CHECK: str r1,
+; CHECK: str r2,
+; CHECK: bl throws_2
+define void @no_stm(i32 %a, i32 %b, i32 %c, i32* %d) local_unnamed_addr noreturn "no-frame-pointer-elim"="true" {
+entry:
+  %arrayidx = getelementptr inbounds i32, i32* %d, i32 2
+  store i32 %a, i32* %arrayidx, align 4
+  %arrayidx1 = getelementptr inbounds i32, i32* %d, i32 3
+  store i32 %b, i32* %arrayidx1, align 4
+  %arrayidx2 = getelementptr inbounds i32, i32* %d, i32 4
+  store i32 %c, i32* %arrayidx2, align 4
+  tail call void @throws_2(i32 %a, i32 %b, i32 %c, i32* %d) noreturn
+  unreachable
+}
+
+
+declare void @throws_1(i32, i32, i32) noreturn
+declare void @throws_2(i32, i32, i32, i32*) noreturn