X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW

[zvi]

Summary

AVX512BW adds support for variable shift amount for 16-bit element
vectors.

[RKSimon]

LGTM - I've regenerated x86-shuffle-sink.ll so you'll need to rebase.

[zvi]

Rebase

llvm/trunk/lib/Target/X86/X86ISelLowering.cpp

bool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
   if (Bits == 8)
     return false;
 
   // AVX2 has vpsllv[dq] instructions (and other shifts) that make variable
   // shifts just as cheap as scalar ones.
   if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64))
     return false;
 
+  // AVX512BW has shifts such as vpsllvw.
+  if (Subtarget.hasBWI() && Bits == 16)
+      return false;
+
   // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
   // fully general vector.
   return true;
 }
 
 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
   if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
     return false;

llvm/trunk/test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll

if_true:
   ret <16 x i8> %mask
 
 if_false:
   %res = shl <16 x i8> %lhs, %mask
   ret <16 x i8> %res
 }
 
 define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) {
-; CHECK-LABEL: @test_16bit(
-; CHECK-NEXT:    [[MASK:%.*]] = shufflevector <8 x i16> [[TMP:%.*]], <8 x i16> undef, <8 x i32> zeroinitializer
-; CHECK-NEXT:    br i1 [[TST:%.*]], label [[IF_TRUE:%.*]], label [[IF_FALSE:%.*]]
-; CHECK:       if_true:
-; CHECK-NEXT:    ret <8 x i16> [[MASK]]
-; CHECK:       if_false:
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <8 x i16> [[TMP]], <8 x i16> undef, <8 x i32> zeroinitializer
-; CHECK-NEXT:    [[RES:%.*]] = shl <8 x i16> [[LHS:%.*]], [[TMP1]]
-; CHECK-NEXT:    ret <8 x i16> [[RES]]
-;
+; CHECK-SSE2-LABEL: @test_16bit
+; CHECK-SSE2: if_true:
+; CHECK-SSE2-NOT: shufflevector
+; CHECK-SSE2: if_false:
+; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-SSE2: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-AVX2-LABEL: @test_16bit
+; CHECK-AVX2: if_true:
+; CHECK-AVX2-NOT: shufflevector
+; CHECK-AVX2: if_false:
+; CHECK-AVX2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-AVX2: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-XOP-LABEL: @test_16bit
+; CHECK-XOP: if_true:
+; CHECK-XOP-NOT: shufflevector
+; CHECK-XOP: if_false:
+; CHECK-XOP: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-XOP: shl <8 x i16> %lhs, [[SPLAT]]
+
+; CHECK-AVX512BW-LABEL: @test_16bit
+; CHECK-AVX512BW: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
+; CHECK-AVX512BW: if_true:
+; CHECK-AVX512BW-NOT: shufflevector
+; CHECK-AVX512BW: if_false:
+; CHECK-AVX512BW-NOT: shufflevector
+; CHECK-AVX512BW: shl <8 x i16> %lhs, [[SPLAT]]
   %mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer
   br i1 %tst, label %if_true, label %if_false
 
 if_true:
   ret <8 x i16> %mask
 
 if_false:
   %res = shl <8 x i16> %lhs, %mask