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Differential D42437

X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW
ClosedPublic

Authored by zvi on Jan 23 2018, 12:10 PM.

Details

Reviewers
craig.topper
RKSimon
spatel
Commits
rGb5447b1e7c34: X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW
rL323292: X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW
Summary

AVX512BW adds support for variable shift amount for 16-bit element
vectors.

Diff Detail

Event Timeline

zvi created this revision.Jan 23 2018, 12:10 PM
Herald added subscribers: tschuett, rengolin. · View Herald TranscriptJan 23 2018, 12:10 PM
RKSimon accepted this revision.Jan 23 2018, 2:12 PM

LGTM - I've regenerated x86-shuffle-sink.ll so you'll need to rebase.

This revision is now accepted and ready to land.Jan 23 2018, 2:12 PM
zvi updated this revision to Diff 131178.Jan 23 2018, 5:36 PM

Rebase

Closed by commit rL323292: X86: Update isVectorShiftByScalarCheap with cases covered by AVX512BW (authored by zvi). · Explain WhyJan 23 2018, 5:38 PM
This revision was automatically updated to reflect the committed changes.
RKSimon mentioned this in D42526: [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP.Jan 25 2018, 3:42 AM
RKSimon mentioned this in rL323797: [X86][XOP] Update isVectorShiftByScalarCheap with cases covered by XOP.Jan 30 2018, 10:12 AM

Revision Contents

PathSize
lib/
Target/
X86/
4 lines
test/
Transforms/
CodeGenPrepare/
X86/
28 lines

Diff 131127

lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 25,652 Lines • ▼ Show 20 Linesbool X86TargetLowering::isVectorShiftByScalarCheap(Type *Ty) const {
if (Bits == 8) if (Bits == 8)
return false; return false;
// AVX2 has vpsllv[dq] instructions (and other shifts) that make variable // AVX2 has vpsllv[dq] instructions (and other shifts) that make variable
// shifts just as cheap as scalar ones. // shifts just as cheap as scalar ones.
if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64)) if (Subtarget.hasAVX2() && (Bits == 32 || Bits == 64))
return false; return false;
// AVX512BW has shifts such as vpsllvw.
if (Subtarget.hasBWI() && Bits == 16)
return false;
// Otherwise, it's significantly cheaper to shift by a scalar amount than by a // Otherwise, it's significantly cheaper to shift by a scalar amount than by a
// fully general vector. // fully general vector.
return true; return true;
} }
bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const {
if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy())
return false; return false;
▲ Show 20 Lines • Show All 13,469 Lines • Show Last 20 Lines

test/Transforms/CodeGenPrepare/X86/x86-shuffle-sink.ll

Show All 19 Linesif_true:
ret <16 x i8> %mask ret <16 x i8> %mask
if_false: if_false:
%res = shl <16 x i8> %lhs, %mask %res = shl <16 x i8> %lhs, %mask
ret <16 x i8> %res ret <16 x i8> %res
} }
define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) { define <8 x i16> @test_16bit(<8 x i16> %lhs, <8 x i16> %tmp, i1 %tst) {
; CHECK-LABEL: @test_16bit ; CHECK-SSE2-LABEL: @test_16bit
; CHECK: if_true: ; CHECK-SSE2: if_true:
; CHECK-NOT: shufflevector ; CHECK-SSE2-NOT: shufflevector
; CHECK-SSE2: if_false:
; CHECK-SSE2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
; CHECK-SSE2: shl <8 x i16> %lhs, [[SPLAT]]
; CHECK: if_false: ; CHECK-AVX2-LABEL: @test_16bit
; CHECK: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector ; CHECK-AVX2: if_true:
; CHECK: shl <8 x i16> %lhs, [[SPLAT]] ; CHECK-AVX2-NOT: shufflevector
; CHECK-AVX2: if_false:
; CHECK-AVX2: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
; CHECK-AVX2: shl <8 x i16> %lhs, [[SPLAT]]
; CHECK-AVX512BW-LABEL: @test_16bit
; CHECK-AVX512BW: [[SPLAT:%[0-9a-zA-Z_]+]] = shufflevector
; CHECK-AVX512BW: if_true:
; CHECK-AVX512BW-NOT: shufflevector
; CHECK-AVX512BW: if_false:
; CHECK-AVX512BW-NOT: shufflevector
; CHECK-AVX512BW: shl <8 x i16> %lhs, [[SPLAT]]
%mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer %mask = shufflevector <8 x i16> %tmp, <8 x i16> undef, <8 x i32> zeroinitializer
br i1 %tst, label %if_true, label %if_false br i1 %tst, label %if_true, label %if_false
if_true: if_true:
ret <8 x i16> %mask ret <8 x i16> %mask
if_false: if_false:
%res = shl <8 x i16> %lhs, %mask %res = shl <8 x i16> %lhs, %mask
▲ Show 20 Lines • Show All 64 Lines • Show Last 20 Lines