[GISel]: Eliminate redundant copies b/w VRegs of same regclass at the end of InstructionSelection

[aditya_nandakumar]

Summary

A lot of these copies are useless (copies b/w VRegs having the same regclass) and should be cleaned up so that later passes don't have to all check to walk through the source of copies.

[aditya_nandakumar]

Updated commented in InstructionSelector.cpp

[qcolombet]

Sounds like a good thing to do.

One comment inline.

lib/CodeGen/GlobalISel/InstructionSelect.cpp

194

Instead of having another pass through the IR for this, could we do it while we do the ISel loop?

Meaning, if the register banks match, push the RC to the def and let constraint operand create a new copy if need be.
I would expect this to be more efficient in term of compile time, but we would need to check.

[bogner]

lib/CodeGen/GlobalISel/InstructionSelect.cpp

162

Why are you calling this MBI? It's a "MachineBasicBlock &", so it should really just be called MBB. I'd probably write out MachineBasicBlock instead of using auto here, as well.

167

Don't bother getting a pointer here - just use the reference.

179

Might be more readable to use the early-continue style in all these conditions, ie:

if (MI.getOpcode() != TargetOpcode::COPY)
  continue;

(Feel free to leave as is if that doesn't actually make it more readable)

180

This isn't used until after the next condition, best to move it down.

[aditya_nandakumar]

lib/CodeGen/GlobalISel/InstructionSelect.cpp

167

Will update.

179

Sure. I can update to that.

180

Good point. Will do.

194

That sounds like it might work - let me give that a try.

[aditya_nandakumar]

Updated based on Justin's feedback.

@qcolombet , I'm not sure if it always makes sense to propagate the register class information for all copies and replacing before the select hook for COPY. For all you know the target may want to do something special with the COPY.

[bogner]

LGTM as long as Quentin's convinced the second iteration makes sense.

[qcolombet]

LGTM too. The code is probably simpler to understand like this and if compile-time turns out to be a problem we can revisit.
I wonder though if removing this copies upfront wouldn't have helped tablegen current matching table (because it does not look through COPYs right now).

[aditya_nandakumar]

In D42402#985864, @qcolombet wrote:

LGTM too. The code is probably simpler to understand like this and if compile-time turns out to be a problem we can revisit.
I wonder though if removing this copies upfront wouldn't have helped tablegen current matching table (because it does not look through COPYs right now).

I certainly suspect somehow eliminating these copies upfront will result in tablegen matching patterns more deeply. I wonder if adding another step inside GIM_Try to also walk through copies is too much of a compile time increase as compared to a quick run before ISel removing redundant copies.

[aditya_nandakumar]

Committed in r323291.

lib/CodeGen/GlobalISel/InstructionSelect.cpp

#endif
           dbgs() << "  " << InsertedMI;
         dbgs() << '\n';
       });
     }
   }
 
   const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
 
+  for (MachineBasicBlock &MBB : MF) {
+    if (MBB.empty())
+      continue;
+
+    // Try to find redundant copies b/w vregs of the same register class.
+    bool ReachedBegin = false;
+    for (auto MII = std::prev(MBB.end()), Begin = MBB.begin(); !ReachedBegin;) {
+      // Select this instruction.
+      MachineInstr &MI = *MII;
+
+      // And have our iterator point to the next instruction, if there is one.
+      if (MII == Begin)
+        ReachedBegin = true;
+      else
+        --MII;
+      if (MI.getOpcode() != TargetOpcode::COPY)
+        continue;
+      unsigned SrcReg = MI.getOperand(1).getReg();
+      unsigned DstReg = MI.getOperand(0).getReg();
+      if (TargetRegisterInfo::isVirtualRegister(SrcReg) &&
+          TargetRegisterInfo::isVirtualRegister(DstReg)) {
+        MachineRegisterInfo &MRI = MF.getRegInfo();
+        auto SrcRC = MRI.getRegClass(SrcReg);
+        auto DstRC = MRI.getRegClass(DstReg);
+        if (SrcRC == DstRC) {
+          MRI.replaceRegWith(DstReg, SrcReg);
+          MI.eraseFromParentAndMarkDBGValuesForRemoval();
+        }
+      }
+    }
+  }
+
   // Now that selection is complete, there are no more generic vregs.  Verify
   // that the size of the now-constrained vreg is unchanged and that it has a
   // register class.
   for (auto &VRegToType : MRI.getVRegToType()) {
     unsigned VReg = VRegToType.first;
     auto *RC = MRI.getRegClassOrNull(VReg);
     MachineInstr *MI = nullptr;
     if (!MRI.def_empty(VReg))
       MI = &*MRI.def_instr_begin(VReg);

test/CodeGen/AArch64/GlobalISel/select-bitcast-bigendian.mir

 # RUN: llc -O0 -mtriple=arm64eb-- -run-pass=instruction-select -verify-machineinstrs -global-isel %s -o - | FileCheck %s
 ---
 name:            bitcast_v2f32_to_s64
 legalized:       true
 regBankSelected: true
 
 body:             |
   bb.0:
     liveins: %x0
 
     ; CHECK-LABEL: name: bitcast_v2f32_to_s64
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
-    ; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY1]]
+    ; CHECK: [[REV:%[0-9]+]]:fpr64 = REV64v2i32 [[COPY]]
     ; CHECK: %x0 = COPY [[REV]]
     %0:fpr(<2 x s32>) = COPY %x0
     %1:fpr(s64) = G_BITCAST %0
     %x0 = COPY %1(s64)
 ...

test/CodeGen/AArch64/GlobalISel/select-bitcast.mir

registers:
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: bitcast_s32_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
-    ; CHECK: %w0 = COPY [[COPY1]]
+    ; CHECK: %w0 = COPY [[COPY]]
     %0(s32) = COPY %w0
     %1(s32) = G_BITCAST %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 name:            bitcast_s32_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: %s0
 
     ; CHECK-LABEL: name: bitcast_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY %s0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
-    ; CHECK: %s0 = COPY [[COPY1]]
+    ; CHECK: %s0 = COPY [[COPY]]
     %0(s32) = COPY %s0
     %1(s32) = G_BITCAST %0
     %s0 = COPY %1(s32)
 ...
 
 ---
 name:            bitcast_s32_gpr_fpr
 legalized:       true
registers:
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %x0
 
     ; CHECK-LABEL: name: bitcast_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
-    ; CHECK: %x0 = COPY [[COPY1]]
+    ; CHECK: %x0 = COPY [[COPY]]
     %0(s64) = COPY %x0
     %1(s64) = G_BITCAST %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 name:            bitcast_s64_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: %d0
 
     ; CHECK-LABEL: name: bitcast_s64_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
-    ; CHECK: %d0 = COPY [[COPY1]]
+    ; CHECK: %d0 = COPY [[COPY]]
     %0(s64) = COPY %d0
     %1(s64) = G_BITCAST %0
     %d0 = COPY %1(s64)
 ...
 
 ---
 name:            bitcast_s64_gpr_fpr
 legalized:       true
registers:
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: %d0
 
     ; CHECK-LABEL: name: bitcast_s64_v2f32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
-    ; CHECK: %x0 = COPY [[COPY1]]
+    ; CHECK: %x0 = COPY [[COPY]]
     %0(s64) = COPY %d0
     %1(<2 x s32>) = G_BITCAST %0
     %x0 = COPY %1(<2 x s32>)
 ...
 
 ---
 name:            bitcast_s64_v8i8_fpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
   - { id: 1, class: fpr }
 
 body:             |
   bb.0:
     liveins: %d0
 
     ; CHECK-LABEL: name: bitcast_s64_v8i8_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY %d0
-    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
-    ; CHECK: %x0 = COPY [[COPY1]]
+    ; CHECK: %x0 = COPY [[COPY]]
     %0(s64) = COPY %d0
     %1(<8 x s8>) = G_BITCAST %0
     %x0 = COPY %1(<8 x s8>)
 ...

test/CodeGen/AArch64/GlobalISel/select-br.mir

 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 # CHECK:  body:
 # CHECK:   bb.0:
-# CHECK:    TBNZW %0, 0, %bb.1
+# CHECK:    TBNZW %1, 0, %bb.1
 # CHECK:    B %bb.0
 body:             |
   bb.0:
     successors: %bb.0, %bb.1
     %1(s32) = COPY %w0
     %0(s1) = G_TRUNC %1
     G_BRCOND %0(s1), %bb.1
     G_BR %bb.0

test/CodeGen/AArch64/GlobalISel/select-int-ext.mir

 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: anyext_s64_from_s32
     ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY %w0
     ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_32
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[SUBREG_TO_REG]]
-    ; CHECK: %x0 = COPY [[COPY1]]
+    ; CHECK: %x0 = COPY [[SUBREG_TO_REG]]
     %0(s32) = COPY %w0
     %1(s64) = G_ANYEXT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 name:            anyext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: anyext_s32_from_s8
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
     %1(s32) = G_ANYEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
registers:
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: zext_s32_from_s16
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
     ; CHECK: %w0 = COPY [[UBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s16) = G_TRUNC %2
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1
 ...
 
 ---
 name:            zext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: zext_s32_from_s8
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 15
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 15
     ; CHECK: %w0 = COPY [[UBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s16) = G_TRUNC %2
     %1(s32) = G_ZEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 name:            zext_s16_from_s8
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: zext_s16_from_s8
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[UBFMWri:%[0-9]+]]:gpr32 = UBFMWri [[COPY]], 0, 7
     ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[UBFMWri]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
     %1(s16) = G_ZEXT %0
     %3:gpr(s32) = G_ANYEXT %1
     %w0 = COPY %3(s32)
 ...
registers:
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: sext_s32_from_s16
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 15
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 15
     ; CHECK: %w0 = COPY [[SBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s16) = G_TRUNC %2
     %1(s32) = G_SEXT %0
     %w0 = COPY %1
 ...
 
 ---
 name:            sext_s32_from_s8
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: sext_s32_from_s8
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
     ; CHECK: %w0 = COPY [[SBFMWri]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
     %1(s32) = G_SEXT %0
     %w0 = COPY %1(s32)
 ...
 
 ---
 name:            sext_s16_from_s8
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: sext_s16_from_s8
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY1]], 0, 7
+    ; CHECK: [[SBFMWri:%[0-9]+]]:gpr32 = SBFMWri [[COPY]], 0, 7
     ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[SBFMWri]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %2:gpr(s32) = COPY %w0
     %0(s8) = G_TRUNC %2
     %1(s16) = G_SEXT %0
     %3:gpr(s32) = G_ANYEXT %1
     %w0 = COPY %3(s32)
 ...

test/CodeGen/AArch64/GlobalISel/select-int-ptr-casts.mir

 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: inttoptr_p0_s64
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
-    ; CHECK: %x0 = COPY [[COPY1]]
+    ; CHECK: %x0 = COPY [[COPY]]
     %0(s64) = COPY %x0
     %1(p0) = G_INTTOPTR %0
     %x0 = COPY %1(p0)
 ...
 
 ---
 name:            ptrtoint_s64_p0
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 body:             |
   bb.0:
     liveins: %x0
     ; CHECK-LABEL: name: ptrtoint_s64_p0
     ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY %x0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
-    ; CHECK: %x0 = COPY [[COPY1]]
+    ; CHECK: %x0 = COPY [[COPY]]
     %0(p0) = COPY %x0
     %1(s64) = G_PTRTOINT %0
     %x0 = COPY %1(s64)
 ...
 
 ---
 name:            ptrtoint_s32_p0
 legalized:       true

test/CodeGen/AArch64/GlobalISel/select-store.mir

 
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_s16_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
-    ; CHECK: STRHHui [[COPY2]], [[COPY]], 0 :: (store 2 into %ir.addr)
+    ; CHECK: STRHHui [[COPY1]], [[COPY]], 0 :: (store 2 into %ir.addr)
     %0(p0) = COPY %x0
     %2:gpr(s32) = COPY %w1
     %1(s16) = G_TRUNC %2
     G_STORE  %1, %0 :: (store 2 into %ir.addr)
 
 ...
 
 ---
 name:            store_s8_gpr
 legalized:       true
 regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_s8_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
-    ; CHECK: STRBBui [[COPY2]], [[COPY]], 0 :: (store 1 into %ir.addr)
+    ; CHECK: STRBBui [[COPY1]], [[COPY]], 0 :: (store 1 into %ir.addr)
     %0(p0) = COPY %x0
     %2:gpr(s32) = COPY %w1
     %1(s8) = G_TRUNC %2
     G_STORE  %1, %0 :: (store 1 into %ir.addr)
 
 ...
 
 ---

 
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_gep_64_s16_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
-    ; CHECK: STRHHui [[COPY2]], [[COPY]], 32 :: (store 2 into %ir.addr)
+    ; CHECK: STRHHui [[COPY1]], [[COPY]], 32 :: (store 2 into %ir.addr)
     %0(p0) = COPY %x0
     %4:gpr(s32) = COPY %w1
     %1(s16) = G_TRUNC %4
     %2(s64) = G_CONSTANT i64 64
     %3(p0) = G_GEP %0, %2
     G_STORE %1, %3 :: (store 2 into %ir.addr)
 ...
 

 
 body:             |
   bb.0:
     liveins: %x0, %w1
 
     ; CHECK-LABEL: name: store_gep_1_s8_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY %x0
     ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY %w1
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY [[COPY1]]
-    ; CHECK: STRBBui [[COPY2]], [[COPY]], 1 :: (store 1 into %ir.addr)
+    ; CHECK: STRBBui [[COPY1]], [[COPY]], 1 :: (store 1 into %ir.addr)
     %0(p0) = COPY %x0
     %4:gpr(s32) = COPY %w1
     %1(s8) = G_TRUNC %4
     %2(s64) = G_CONSTANT i64 1
     %3(p0) = G_GEP %0, %2
     G_STORE %1, %3 :: (store 1 into %ir.addr)
 ...
 

test/CodeGen/AArch64/GlobalISel/select-trunc.mir

registers:
   - { id: 1, class: gpr }
 
 body:             |
   bb.0:
     liveins: %w0
 
     ; CHECK-LABEL: name: trunc_s1_s32
     ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY %w0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
-    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY]]
     ; CHECK: %w0 = COPY [[COPY2]]
     %0(s32) = COPY %w0
     %1(s1) = G_TRUNC %0
     %2:gpr(s32) = G_ANYEXT %1
     %w0 = COPY %2(s32)
 ...

test/CodeGen/AArch64/GlobalISel/select.mir

registers:
   - { id: 4, class: gpr }
   - { id: 5, class: gpr }
   - { id: 6, class: gpr }
   - { id: 7, class: gpr }
   - { id: 8, class: gpr }
   - { id: 9, class: gpr }
 
 # CHECK:  body:
-# CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK:      %wzr = ANDSWri %10, 0, implicit-def %nzcv
 # CHECK:      %3:gpr32 = CSELWr %1, %2, 1, implicit %nzcv
-# CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK:      %wzr = ANDSWri %10, 0, implicit-def %nzcv
 # CHECK:      %6:gpr64 = CSELXr %4, %5, 1, implicit %nzcv
-# CHECK:      %wzr = ANDSWri %0, 0, implicit-def %nzcv
+# CHECK:      %wzr = ANDSWri %10, 0, implicit-def %nzcv
 # CHECK:      %9:gpr64 = CSELXr %7, %8, 1, implicit %nzcv
 body:             |
   bb.0:
     liveins: %w0, %w1, %w2
     %10:gpr(s32) = COPY %w0
     %0(s1) = G_TRUNC %10
 
     %1(s32) = COPY %w1

test/CodeGen/ARM/GlobalISel/arm-instruction-select.mir

 body:             |
   bb.0:
     liveins: %r0
 
     %0(s32) = COPY %r0
     ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s1) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_ZEXT %1(s1)
-    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
+    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
     BX_RET 14, %noreg, implicit %r0
     ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---

 body:             |
   bb.0:
     liveins: %r0
 
     %0(s32) = COPY %r0
     ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s1) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_SEXT %1(s1)
-    ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREGTRUNC]], 1, 14, %noreg, %noreg
+    ; CHECK: [[VREGAND:%[0-9]+]]:gpr = ANDri [[VREG]], 1, 14, %noreg, %noreg
     ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = RSBri [[VREGAND]], 0, 14, %noreg, %noreg
 
     %r0 = COPY %2(s32)
     ; CHECK: %r0 = COPY [[VREGEXT]]
 
     BX_RET 14, %noreg, implicit %r0
     ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...

 body:             |
   bb.0:
     liveins: %r0
 
     %0(s32) = COPY %r0
     ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s8) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_ANYEXT %1(s8)
-    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]]
 
     %r0 = COPY %2(s32)
-    ; CHECK: %r0 = COPY [[VREGEXT]]
+    ; CHECK: %r0 = COPY [[VREG]]
 
     BX_RET 14, %noreg, implicit %r0
     ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_and_anyext_s16
 # CHECK-LABEL: name: test_trunc_and_anyext_s16
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
   - { id: 2, class: gprb }
 body:             |
   bb.0:
     liveins: %r0
 
     %0(s32) = COPY %r0
     ; CHECK: [[VREG:%[0-9]+]]:gpr = COPY %r0
 
     %1(s16) = G_TRUNC %0(s32)
-    ; CHECK: [[VREGTRUNC:%[0-9]+]]:gpr = COPY [[VREG]]
 
     %2(s32) = G_ANYEXT %1(s16)
-    ; CHECK: [[VREGEXT:%[0-9]+]]:gpr = COPY [[VREGTRUNC]]
 
     %r0 = COPY %2(s32)
-    ; CHECK: %r0 = COPY [[VREGEXT]]
+    ; CHECK: %r0 = COPY [[VREG]]
 
     BX_RET 14, %noreg, implicit %r0
     ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_trunc_s64
 # CHECK-LABEL: name: test_trunc_s64
 legalized:       true
bb.0:
     %5(s64) = COPY %d2
     %1(s8) = G_TRUNC %3(s32)
     %2(s16) = G_TRUNC %3(s32)
 
     G_STORE %1(s8), %0(p0) :: (store 1)
     ; CHECK: STRBi12 %[[I8]], %[[P]], 0, 14, %noreg
 
     G_STORE %2(s16), %0(p0) :: (store 2)
-    ; CHECK: STRH %[[I16]], %[[P]], %noreg, 0, 14, %noreg
+    ; CHECK: STRH %[[I32]], %[[P]], %noreg, 0, 14, %noreg
 
     G_STORE %3(s32), %0(p0) :: (store 4)
     ; CHECK: STRi12 %[[I32]], %[[P]], 0, 14, %noreg
 
     G_STORE %4(s32), %0(p0) :: (store 4)
     ; CHECK: VSTRS %[[F32]], %[[P]], 0, 14, %noreg
 
     G_STORE %5(s64), %0(p0) :: (store 8)
registers:
   - { id: 1, class: gprb }
 body:             |
   bb.0:
     liveins: %r0
 
     %0(s32) = COPY %r0
     %1(p0) = G_INTTOPTR %0(s32)
     ; CHECK: [[INT:%[0-9]+]]:gpr = COPY %r0
-    ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY [[INT]]
 
     %r0 = COPY %1(p0)
-    ; CHECK: %r0 = COPY [[PTR]]
+    ; CHECK: %r0 = COPY [[INT]]
 
     BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_ptrtoint_s32
 # CHECK-LABEL: name: test_ptrtoint_s32
 legalized:       true
 regBankSelected: true
 selected:        false
 # CHECK: selected: true
 registers:
   - { id: 0, class: gprb }
   - { id: 1, class: gprb }
 body:             |
   bb.0:
     liveins: %r0
 
     %0(p0) = COPY %r0
     %1(s32) = G_PTRTOINT %0(p0)
     ; CHECK: [[PTR:%[0-9]+]]:gpr = COPY %r0
-    ; CHECK: [[INT:%[0-9]+]]:gpr = COPY [[PTR]]
 
     %r0 = COPY %1(s32)
-    ; CHECK: %r0 = COPY [[INT]]
+    ; CHECK: %r0 = COPY [[PTR]]
 
     BX_RET 14, %noreg, implicit %r0
 ...
 ---
 name:            test_select_s32
 # CHECK-LABEL: name: test_select_s32
 legalized:       true
 regBankSelected: true
bb.0:
 
     %0(s32) = COPY %r0
     ; CHECK: [[VREGX:%[0-9]+]]:gpr = COPY %r0
 
     %1(s32) = COPY %r1
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s1) = G_TRUNC %1(s32)
-    ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY [[VREGY]]
 
     %3(s32) = G_SELECT %2(s1),  %0, %1
-    ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr
+    ; CHECK: CMPri [[VREGY]], 0, 14, %noreg, implicit-def %cpsr
     ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
 
     %r0 = COPY %3(s32)
     ; CHECK: %r0 = COPY [[RES]]
 
     BX_RET 14, %noreg, implicit %r0
     ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
bb.0:
 
     %1(p0) = COPY %r1
     ; CHECK: [[VREGY:%[0-9]+]]:gpr = COPY %r1
 
     %2(s32) = COPY %r2
     ; CHECK: [[VREGC:%[0-9]+]]:gpr = COPY %r2
 
     %3(s1) = G_TRUNC %2(s32)
-    ; CHECK: [[VREGD:%[0-9]+]]:gpr = COPY [[VREGC]]
 
     %4(p0) = G_SELECT %3(s1),  %0, %1
-    ; CHECK: CMPri [[VREGD]], 0, 14, %noreg, implicit-def %cpsr
+    ; CHECK: CMPri [[VREGC]], 0, 14, %noreg, implicit-def %cpsr
     ; CHECK: [[RES:%[0-9]+]]:gpr = MOVCCr [[VREGX]], [[VREGY]], 0, %cpsr
 
     %r0 = COPY %4(p0)
     ; CHECK: %r0 = COPY [[RES]]
 
     BX_RET 14, %noreg, implicit %r0
     ; CHECK: BX_RET 14, %noreg, implicit %r0
 ...
body:             |
   bb.0:
   ; CHECK: bb.0
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: %r0
 
     %0(s32) = COPY %r0
     ; CHECK: [[COND32:%[0-9]+]]:gpr = COPY %r0
     %1(s1) = G_TRUNC %0(s32)
-    ; CHECK: [[COND:%[0-9]+]]:gpr = COPY [[COND32]]
 
     G_BRCOND %1(s1), %bb.1
-    ; CHECK: TSTri [[COND]], 1, 14, %noreg, implicit-def %cpsr
+    ; CHECK: TSTri [[COND32]], 1, 14, %noreg, implicit-def %cpsr
     ; CHECK: Bcc %bb.1, 1, %cpsr
     G_BR %bb.2
     ; CHECK: B %bb.2
 
   bb.1:
   ; CHECK: bb.1
     successors: %bb.2(0x80000000)
 

test/CodeGen/X86/GlobalISel/select-ext-x86-64.mir

registers:
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     ; ALL-LABEL: name: test_zext_i1
     ; ALL: [[COPY:%[0-9]+]]:gr8 = COPY %dil
-    ; ALL: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]]
-    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY1]], %subreg.sub_8bit
+    ; ALL: [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, [[COPY]], %subreg.sub_8bit
     ; ALL: [[AND64ri8_:%[0-9]+]]:gr64 = AND64ri8 [[SUBREG_TO_REG]], 1, implicit-def %eflags
     ; ALL: %rax = COPY [[AND64ri8_]]
     ; ALL: RET 0, implicit %rax
     %0(s8) = COPY %dil
     %1(s1) = G_TRUNC %0(s8)
     %2(s64) = G_ZEXT %1(s1)
     %rax = COPY %2(s64)
     RET 0, implicit %rax

test/CodeGen/X86/GlobalISel/select-ext.mir

 # X64-NEXT:   - { id: 2, class: gr8, preferred-register: '' }
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
   - { id: 2, class: gpr }
 # X32:          %0:gr32_abcd = COPY %edi
 # X64:          %0:gr32 = COPY %edi
 # ALL-NEXT:     %1:gr8 = COPY %0.sub_8bit
-# ALL-NEXT:     %2:gr8 = COPY %1
-# ALL-NEXT:     %al = COPY %2
+# ALL-NEXT:     %al = COPY %1
 # ALL-NEXT:     RET 0, implicit %al
 body:             |
   bb.1 (%ir-block.0):
     liveins: %edi
 
     %0(s32) = COPY %edi
     %1(s1) = G_TRUNC %0(s32)
     %2(s8) = G_ANYEXT %1(s1)

test/CodeGen/X86/GlobalISel/select-merge-vec256.mir

 #
 body:             |
   bb.1 (%ir-block.0):
 
     ; AVX-LABEL: name: test_merge
     ; AVX: [[DEF:%[0-9]+]]:vr128 = IMPLICIT_DEF
     ; AVX: undef %2.sub_xmm:vr256 = COPY [[DEF]]
     ; AVX: [[VINSERTF128rr:%[0-9]+]]:vr256 = VINSERTF128rr %2, [[DEF]], 1
-    ; AVX: [[COPY:%[0-9]+]]:vr256 = COPY [[VINSERTF128rr]]
-    ; AVX: %ymm0 = COPY [[COPY]]
+    ; AVX: %ymm0 = COPY [[VINSERTF128rr]]
     ; AVX: RET 0, implicit %ymm0
     ; AVX512VL-LABEL: name: test_merge
     ; AVX512VL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
     ; AVX512VL: undef %2.sub_xmm:vr256x = COPY [[DEF]]
     ; AVX512VL: [[VINSERTF32x4Z256rr:%[0-9]+]]:vr256x = VINSERTF32x4Z256rr %2, [[DEF]], 1
-    ; AVX512VL: [[COPY:%[0-9]+]]:vr256x = COPY [[VINSERTF32x4Z256rr]]
-    ; AVX512VL: %ymm0 = COPY [[COPY]]
+    ; AVX512VL: %ymm0 = COPY [[VINSERTF32x4Z256rr]]
     ; AVX512VL: RET 0, implicit %ymm0
     %0(<4 x s32>) = IMPLICIT_DEF
     %1(<8 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>)
     %ymm0 = COPY %1(<8 x s32>)
     RET 0, implicit %ymm0
 
 ...
 

test/CodeGen/X86/GlobalISel/select-merge-vec512.mir

body:             |
   bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_merge_v128
     ; ALL: [[DEF:%[0-9]+]]:vr128x = IMPLICIT_DEF
     ; ALL: undef %2.sub_xmm:vr512 = COPY [[DEF]]
     ; ALL: [[VINSERTF32x4Zrr:%[0-9]+]]:vr512 = VINSERTF32x4Zrr %2, [[DEF]], 1
     ; ALL: [[VINSERTF32x4Zrr1:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr]], [[DEF]], 2
     ; ALL: [[VINSERTF32x4Zrr2:%[0-9]+]]:vr512 = VINSERTF32x4Zrr [[VINSERTF32x4Zrr1]], [[DEF]], 3
-    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF32x4Zrr2]]
-    ; ALL: %zmm0 = COPY [[COPY]]
+    ; ALL: %zmm0 = COPY [[VINSERTF32x4Zrr2]]
     ; ALL: RET 0, implicit %zmm0
     %0(<4 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_MERGE_VALUES %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>), %0(<4 x s32>)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...
 ---
 name:            test_merge_v256
 alignment:       4
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: vecr }
   - { id: 1, class: vecr }
 body:             |
   bb.1 (%ir-block.0):
 
     ; ALL-LABEL: name: test_merge_v256
     ; ALL: [[DEF:%[0-9]+]]:vr256x = IMPLICIT_DEF
     ; ALL: undef %2.sub_ymm:vr512 = COPY [[DEF]]
     ; ALL: [[VINSERTF64x4Zrr:%[0-9]+]]:vr512 = VINSERTF64x4Zrr %2, [[DEF]], 1
-    ; ALL: [[COPY:%[0-9]+]]:vr512 = COPY [[VINSERTF64x4Zrr]]
-    ; ALL: %zmm0 = COPY [[COPY]]
+    ; ALL: %zmm0 = COPY [[VINSERTF64x4Zrr]]
     ; ALL: RET 0, implicit %zmm0
     %0(<8 x s32>) = IMPLICIT_DEF
     %1(<16 x s32>) = G_MERGE_VALUES %0(<8 x s32>), %0(<8 x s32>)
     %zmm0 = COPY %1(<16 x s32>)
     RET 0, implicit %zmm0
 
 ...