[PowerPC] Legalize SETULT and SETUGT for type f32 and f64.

[jtony]

Summary

ISD::SETULT and ISD::SETUGT for type f32 and f64 on PowerPC are currently set to Expand. They are legalized in this patch.

[nemanjai]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3521

I don't think this is safe to just overlook. Sure the comment doesn't apply any more, but the solution does not appear to be to just remove the comment. You'll have to see where the enclosing function is called and what assumptions are based on us not having FP here.
At the very least, one example shows that we'll have a miscompile due to this:

define double @test(double %a, double %b, double %c, double %d) {
entry:
  %cmp = fcmp ult double %a, %b
  %cond = select i1 %cmp, double %c, double %d
  ret double %cond
}

That'll produce a SET_CC_VSFRC from the ISD::SELECT_CC and the predicate will be PPC::PRED_LT. Of course, that won't consider the UN bit. And sure enough, it'll produce the following code:

xscmpudp 0, 1, 2
blt     0, .LBB0_2

when it should actually be producing:

xscmpudp 0, 1, 2
cror 20, 0, 3
bc 12, 20, .LBB0_2

[jtony]

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

3521

That's a very good catch. I am trying to figure out how we should fix this wrong code-gen here. BTW, one minor nit in the comment: the code you provided will actually produce a SELECT_CC_VSFRC from the ISD::SELECT_CC (we don't have SET_CC_VSFRC)

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) {
   case ISD::SETULE:
   case ISD::SETLE:  return PPC::PRED_LE;
   case ISD::SETOGT:
   case ISD::SETGT:  return PPC::PRED_GT;
   case ISD::SETUGE:
   case ISD::SETGE:  return PPC::PRED_GE;
   case ISD::SETO:   return PPC::PRED_NU;
   case ISD::SETUO:  return PPC::PRED_UN;
-    // These two are invalid for floating point.  Assume we have int.
   case ISD::SETULT: return PPC::PRED_LT;
   case ISD::SETUGT: return PPC::PRED_GT;
   }
 }
 
 /// getCRIdxForSetCC - Return the index of the condition register field
 /// associated with the SetCC condition, and whether or not the field is
 /// treated as inverted.  That is, lt = 0; ge = 0 inverted.

lib/Target/PowerPC/PPCISelLowering.cpp

PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i1, Custom);
 
   setOperationAction(ISD::INTRINSIC_VOID, MVT::i8, Custom);
   setOperationAction(ISD::INTRINSIC_VOID, MVT::i16, Custom);
   setOperationAction(ISD::INTRINSIC_VOID, MVT::i32, Custom);
   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
 
   // Comparisons that require checking two conditions.
-  setCondCodeAction(ISD::SETULT, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETULT, MVT::f64, Expand);
-  setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
-  setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
+  setCondCodeAction(ISD::SETULT, MVT::f32, Legal);
+  setCondCodeAction(ISD::SETULT, MVT::f64, Legal);
+  setCondCodeAction(ISD::SETUGT, MVT::f32, Legal);
+  setCondCodeAction(ISD::SETUGT, MVT::f64, Legal);
   setCondCodeAction(ISD::SETUEQ, MVT::f32, Expand);
   setCondCodeAction(ISD::SETUEQ, MVT::f64, Expand);
   setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
   setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
   setCondCodeAction(ISD::SETOLE, MVT::f32, Expand);
   setCondCodeAction(ISD::SETOLE, MVT::f64, Expand);
   setCondCodeAction(ISD::SETONE, MVT::f32, Expand);
   setCondCodeAction(ISD::SETONE, MVT::f64, Expand);

lib/Target/PowerPC/PPCInstrInfo.td

def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETGT)),
           (CRANDC $s2, $s1)>;
 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETUGT)),
           (CRANDC $s1, $s2)>;
 
 def : Pat<(i1 (setcc i1:$s1, i1:$s2, SETNE)),
           (CRXOR $s1, $s2)>;
 
 // match setcc on non-i1 (non-vector) variables. Note that SETUEQ, SETOGE,
-// SETOLE, SETONE, SETULT and SETUGT should be expanded by legalize for
-// floating-point types.
+// SETOLE, SETONE, should be expanded by legalize for floating-point types.
 
 multiclass CRNotPat<dag pattern, dag result> {
   def : Pat<pattern, (crnot result)>;
   def : Pat<(not pattern), result>;
 
   // We can also fold the crnot into an extension:
   def : Pat<(i32 (zext pattern)),
             (SELECT_I4 result, (LI 0), (LI 1))>;

 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETGT)),
           (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETOEQ)),
           (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETEQ)),
           (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_eq)>;
 def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUO)),
           (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un)>;
+def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETULT)),
+          (CROR (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt),
+                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un))>;
+def : Pat<(i1 (setcc f32:$s1, f32:$s2, SETUGT)),
+          (CROR (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt),
+                (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_un))>;
 
 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETUGE)),
                 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETGE)),
                 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_lt)>;
 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETULE)),
                 (EXTRACT_SUBREG (FCMPUS $s1, $s2), sub_gt)>;
 defm : CRNotPat<(i1 (setcc f32:$s1, f32:$s2, SETLE)),

 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETGT)),
           (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETOEQ)),
           (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETEQ)),
           (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_eq)>;
 def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUO)),
           (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un)>;
+def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETULT)),
+          (CROR (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt),
+                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un))>;
+def : Pat<(i1 (setcc f64:$s1, f64:$s2, SETUGT)),
+          (CROR (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt),
+                (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_un))>;
 
 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETUGE)),
                 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETGE)),
                 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_lt)>;
 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETULE)),
                 (EXTRACT_SUBREG (FCMPUD $s1, $s2), sub_gt)>;
 defm : CRNotPat<(i1 (setcc f64:$s1, f64:$s2, SETLE)),

test/CodeGen/PowerPC/test_fp_ugt.ll

+; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -O3 -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
+
+define i64 @test_fp_ugt(ppc_fp128 %a) {
+entry:
+  %0 = fcmp olt ppc_fp128 %a, 0xM00000000000000000000000000000000
+  br i1 %0, label %bb5, label %bb1
+
+bb1:
+  %1 = fmul ppc_fp128 %a, 0xM3DF00000000000000000000000000000
+  %2 = fptoui ppc_fp128 %1 to i32
+  %3 = zext i32 %2 to i64
+  %4 = shl i64 %3, 32
+  %5 = uitofp i64 %4 to ppc_fp128
+  %6 = fsub ppc_fp128 %a, %5
+  %7 = fcmp olt ppc_fp128 %6, 0xM00000000000000000000000000000000
+  br i1 %7, label %bb2, label %bb3
+
+bb2:
+  %8 = fsub ppc_fp128 0xM80000000000000000000000000000000, %6
+  %9 = fptoui ppc_fp128 %8 to i32
+  %10 = zext i32 %9 to i64
+  %11 = sub i64 %4, %10
+  ret i64 %11
+
+bb3:
+  %12 = fptoui ppc_fp128 %6 to i32
+  %13 = zext i32 %12 to i64
+  %14 = or i64 %13, %4
+  ret i64 %14
+
+bb5:
+  ret i64 0
+
+;CHECK-LABEL: test_fp_ugt
+;CHECK:         fmr f29, f1
+;CHECK-NEXT:  fmr f28, f2
+;CHECK-NEXT:  fcmpu cr0, f29, f31
+;CHECK-NEXT:  fcmpu cr2, f28, f31
+;CHECK-NEXT:  crandc 4*cr5+lt, eq, 4*cr2+lt
+;CHECK-NEXT:  cror 4*cr5+gt, gt, un
+;CHECK-NEXT:  cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+;CHECK-NEXT:  bc 12, 4*cr5+lt, .LBB
+}

test/CodeGen/PowerPC/test_fp_ugt0.ll

+; RUN: llc < %s -mcpu=pwr8 -mattr=-vsx -mtriple=powerpc64le-unknown-unknown -O3 -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
+define i1 @test_fp_ugt_0(double %t0) {
+; CHECK-LABEL: test_fp_ugt_0:
+; CHECK:    lfs f0, 0(r3)
+; CHECK:    fcmpu cr0, f1, f0
+; CHECK:    ble cr0, .LBB0_2
+; CHECK:  # %bb.1: # %good
+; CHECK:    li r3, 1
+; CHECK:    blr
+; CHECK:  .LBB0_2: # %bad
+; CHECK:    li r3, 0
+; CHECK:    blr
+entry:
+  %t1 = fcmp ugt double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}

test/CodeGen/PowerPC/test_fp_ult.ll

+; RUN: llc < %s -mcpu=pwr8 -mtriple=powerpc64le-unknown-unknown -O3 -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
+
+define i64 @test_fp_ult(ppc_fp128 %a) {
+entry:
+  %0 = fcmp ogt ppc_fp128 %a, 0xM00000000000000000000000000000000
+  br i1 %0, label %bb5, label %bb1
+
+bb1:
+  %1 = fmul ppc_fp128 %a, 0xM3DF00000000000000000000000000000
+  %2 = fptoui ppc_fp128 %1 to i32
+  %3 = zext i32 %2 to i64
+  %4 = shl i64 %3, 32
+  %5 = uitofp i64 %4 to ppc_fp128
+  %6 = fsub ppc_fp128 %a, %5
+  %7 = fcmp ogt ppc_fp128 %6, 0xM00000000000000000000000000000000
+  br i1 %7, label %bb2, label %bb3
+
+bb2:
+  %8 = fsub ppc_fp128 0xM80000000000000000000000000000000, %6
+  %9 = fptoui ppc_fp128 %8 to i32
+  %10 = zext i32 %9 to i64
+  %11 = sub i64 %4, %10
+  ret i64 %11
+
+bb3:
+  %12 = fptoui ppc_fp128 %6 to i32
+  %13 = zext i32 %12 to i64
+  %14 = or i64 %13, %4
+  ret i64 %14
+
+bb5:
+  ret i64 0
+
+;CHECK-LABEL: test_fp_ult
+;CHECK:         fmr f29, f1
+;CHECK-NEXT:  fmr f28, f2
+;CHECK-NEXT:  fcmpu cr0, f29, f31
+;CHECK-NEXT:  fcmpu cr2, f28, f31
+;CHECK-NEXT:  crandc 4*cr5+lt, eq, 4*cr2+gt
+;CHECK-NEXT:  cror 4*cr5+gt, lt, un
+;CHECK-NEXT:  cror 4*cr5+lt, 4*cr5+gt, 4*cr5+lt
+;CHECK-NEXT:  bc 12, 4*cr5+lt, .LBB
+}

test/CodeGen/PowerPC/test_fp_ult0.ll

+; RUN: llc < %s -mcpu=pwr8 -mattr=-vsx -mtriple=powerpc64le-unknown-unknown -O3 -ppc-asm-full-reg-names -verify-machineinstrs | FileCheck %s --check-prefix=CHECK
+define i1 @test_fp_ult_0(double %t0) {
+; CHECK-LABEL: test_fp_ult_0:
+; CHECK:    lfs f0, 0(r3)
+; CHECK:    fcmpu cr0, f1, f0
+; CHECK:    bge cr0, .LBB0_2
+; CHECK:  # %bb.1: # %good
+; CHECK:    li r3, 1
+; CHECK:    blr
+; CHECK:  .LBB0_2: # %bad
+; CHECK:    li r3, 0
+; CHECK:    blr
+entry:
+  %t1 = fcmp ult double %t0, 0.000000e+00
+  br i1 %t1, label %good, label %bad
+
+bad:
+  ret i1 false
+
+good:
+  ret i1 true
+}