[X86] Implementation of X86Operand::print

[avt77]

Summary

The current body of the feature is empty. This patch produces the real info describing the given MC operand. Such extended debug logging realy helped when I was working with D41595.

[RKSimon]

lib/Target/X86/AsmParser/X86Operand.h

115

If possible, I'd make this a lambda function inside the print function below and hopefully remove the need for the union.

[avt77]

The implemetation was switched to lambda function.

[RKSimon]

A couple of minors, but no more comments from me. @craig.topper ?

lib/Target/X86/AsmParser/X86Operand.h

102

Capitalization: PrintImmValue

107

Add an assert message

[avt77]

lib/Target/X86/AsmParser/X86Operand.h

107

Maybe it's better something like (instead of assertion):

 if (const MCSymbolRefExpr &SRE = dyn_cast<MCSymbolRefExpr>(*Val)) {
   const MCSymbol &Sym = SRE.getSymbol();
   if (auto SymName = Sym.getName().data())
......

to be sure it can't raise exception?

[avt77]

I renamed the feature and replaced the assertion with dyn_cast.

[craig.topper]

lib/Target/X86/AsmParser/X86Operand.h

39

Why isn't this part of the RegOp struct? Though I suggested a way we can remove this entirely further down.

121

It would print lower case instead of upper case, but I think you can use X86IntelInstPrinter::getRegisterName which is a static method and then you wouldn't have to pass MRI around.

[avt77]

I removed usage of MRI thanking to Craig's suggest.

[craig.topper]

LGTM

lib/Target/X86/AsmParser/X86AsmParser.cpp

std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() {
   InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
 
   // The offset operator will have an 'r' constraint, thus we need to create
   // register operand to ensure proper matching.  Just pick a GPR based on
   // the size of a pointer.
   bool Parse32 = is32BitMode() || Code16GCC;
   unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
 
-  return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
-                               OffsetOfLoc, Identifier, Decl);
+  return X86Operand::CreateReg(
+      RegNo, Start, End, getContext().getRegisterInfo(), /*GetAddress=*/true,
 }
 
 // Query a candidate string for being an Intel assembly operator
 // Report back its kind, or IOK_INVALID if does not evaluated as a known one
 unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
   return StringSwitch<unsigned>(Name)
     .Cases("TYPE","type",IOK_TYPE)
     .Cases("SIZE","size",IOK_SIZE)
std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
 
   // Register operand.
   unsigned RegNo = 0;
   if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
     if (RegNo == X86::RIP)
       return ErrorOperand(Start, "rip can only be used as a base register");
     // A Register followed by ':' is considered a segment override
     if (Tok.isNot(AsmToken::Colon))
-      return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) :
-        ErrorOperand(Start, "expected memory operand after 'ptr', "
+      return !PtrInOperand
+                 ? X86Operand::CreateReg(RegNo, Start, End,
+                                         getContext().getRegisterInfo())
+                 : ErrorOperand(Start, "expected memory operand after 'ptr', "
                                        "found register operand instead");
     // An alleged segment override. check if we have a valid segment register
     if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
       return ErrorOperand(Start, "invalid segment register");
     // Eat ':' and update Start location
     Start = Lex().getLoc();
   }
 
   // Immediates and Memory
if (RegNo == X86::RIP) {
       Error(Start, "%rip can only be used as a base register",
             SMRange(Start, End));
       return nullptr;
     }
 
     // If this is a segment register followed by a ':', then this is the start
     // of a memory reference, otherwise this is a normal register reference.
     if (getLexer().isNot(AsmToken::Colon))
-      return X86Operand::CreateReg(RegNo, Start, End);
+      return X86Operand::CreateReg(RegNo, Start, End,
+                                   getContext().getRegisterInfo());
 
     if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
       return ErrorOperand(Start, "invalid segment register");
 
     getParser().Lex(); // Eat the colon.
     return ParseMemOperand(RegNo, Start);
   }
   case AsmToken::Dollar: {
if (getLexer().is(AsmToken::LCurly)) {
           SMLoc RegLoc;
           if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
               X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
             if (RegNo == X86::K0)
               return Error(RegLoc, "Register k0 can't be used as write mask");
             if (!getLexer().is(AsmToken::RCurly))
               return Error(getLexer().getLoc(), "Expected } at this point");
             Operands.push_back(X86Operand::CreateToken("{", StartLoc));
-            Operands.push_back(
-                X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
+            Operands.push_back(X86Operand::CreateReg(
+                RegNo, StartLoc, StartLoc, getContext().getRegisterInfo()));
             Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
           } else
             return Error(getLexer().getLoc(),
                           "Expected an op-mask register at this point");
           // {%k<NUM>} mark is found, inquire for {z}
           if (getLexer().is(AsmToken::LCurly) && !Z) {
             // Have we've found a parsing error, or found no (expected) {z} mark
             // - report an error
if (Op1.isReg() && Op2.isReg() &&
       // Change instruction name to match new instruction.
       if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
         Name = is16BitMode() ? "movw" : "movl";
         Operands[0] = X86Operand::CreateToken(Name, NameLoc);
       }
       // Select the correct equivalent 16-/32-bit source register.
       unsigned Reg =
           getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
-      Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
+      Operands[1] =
+          X86Operand::CreateReg(Reg, Loc, Loc, getContext().getRegisterInfo());
     }
   }
 
   // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
   // "outb %al, %dx".  Out doesn't take a memory form, but this is a widely
   // documented form in various unofficial manuals, so a lot of code uses it.
   if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
        Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
       Operands.size() == 3) {
     X86Operand &Op = (X86Operand &)*Operands.back();
     if (Op.isMem() && Op.Mem.SegReg == 0 &&
         isa<MCConstantExpr>(Op.Mem.Disp) &&
         cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
       SMLoc Loc = Op.getEndLoc();
-      Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
+      Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc,
+                                              getContext().getRegisterInfo());
     }
   }
   // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
   if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
        Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
       Operands.size() == 3) {
     X86Operand &Op = (X86Operand &)*Operands[1];
     if (Op.isMem() && Op.Mem.SegReg == 0 &&
         isa<MCConstantExpr>(Op.Mem.Disp) &&
         cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
         Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
       SMLoc Loc = Op.getEndLoc();
-      Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
+      Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc,
+                                          getContext().getRegisterInfo());
     }
   }
 
   SmallVector<std::unique_ptr<MCParsedAsmOperand>, 2> TmpOperands;
   bool HadVerifyError = false;
 
   // Append default arguments to "ins[bwld]"
   if (Name.startswith("ins") && 
       (Operands.size() == 1 || Operands.size() == 3) &&
       (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
        Name == "ins")) {
-    
-    AddDefaultSrcDestOperands(TmpOperands,
-                              X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
-                              DefaultMemDIOperand(NameLoc));
+    AddDefaultSrcDestOperands(
+        TmpOperands, X86Operand::CreateReg(X86::DX, NameLoc, NameLoc,
+                                           getContext().getRegisterInfo()),
     HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
   }
 
   // Append default arguments to "outs[bwld]"
   if (Name.startswith("outs") && 
       (Operands.size() == 1 || Operands.size() == 3) &&
       (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
        Name == "outsd" || Name == "outs")) {
-    AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
-                              X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
+    AddDefaultSrcDestOperands(
+        TmpOperands, DefaultMemSIOperand(NameLoc),
+        X86Operand::CreateReg(X86::DX, NameLoc, NameLoc,
+                              getContext().getRegisterInfo()));
     HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
   }
 
   // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
   // values of $SIREG according to the mode. It would be nice if this
   // could be achieved with InstAlias in the tables.
   if (Name.startswith("lods") &&
       (Operands.size() == 1 || Operands.size() == 2) &&

lib/Target/X86/AsmParser/X86Operand.h

 struct X86Operand : public MCParsedAsmOperand {
   enum KindTy { Token, Register, Immediate, Memory, Prefix } Kind;
 
   SMLoc StartLoc, EndLoc;
   SMLoc OffsetOfLoc;
   StringRef SymName;
   void *OpDecl;
   bool AddressOf;
+  const MCRegisterInfo *MRI;
 
   struct TokOp {
     const char *Data;
     unsigned Length;
   };
 
   struct RegOp {
     unsigned RegNo;
struct X86Operand : public MCParsedAsmOperand {
   union {
     struct TokOp Tok;
     struct RegOp Reg;
     struct ImmOp Imm;
     struct MemOp Mem;
     struct PrefOp Pref;
   };
 
-  X86Operand(KindTy K, SMLoc Start, SMLoc End)
-    : Kind(K), StartLoc(Start), EndLoc(End) {}
+  X86Operand(KindTy K, SMLoc Start, SMLoc End,
+             const MCRegisterInfo *RI = nullptr)
+      : Kind(K), StartLoc(Start), EndLoc(End), MRI(RI) {}
 
   StringRef getSymName() override { return SymName; }
   void *getOpDecl() override { return OpDecl; }
 
   /// getStartLoc - Get the location of the first token of this operand.
   SMLoc getStartLoc() const override { return StartLoc; }
 
   /// getEndLoc - Get the location of the last token of this operand.
   SMLoc getEndLoc() const override { return EndLoc; }
 
   /// getLocRange - Get the range between the first and last token of this
   /// operand.
   SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
 
   /// getOffsetOfLoc - Get the location of the offset operator.
   SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
 
-  void print(raw_ostream &OS) const override {}
+  void print(raw_ostream &OS) const override {
+
+    auto printImmValue = [&](const MCExpr *Val, const char *VName) {
+      if (Val->getKind() == MCExpr::Constant) {
+        if (auto Imm = cast<MCConstantExpr>(Val)->getValue())
+          OS << VName << Imm;
+      } else {
+        assert(Val->getKind() == MCExpr::SymbolRef);
+        const MCSymbolRefExpr &SRE = cast<MCSymbolRefExpr>(*Val);
+        const MCSymbol &Sym = SRE.getSymbol();
+        if (auto SymName = Sym.getName().data())
+          OS << VName << SymName;
+      }
+    };
+
+    switch (Kind) {
+    case Token:
+      OS << Tok.Data;
+      break;
+    case Register:
+      assert(MRI && "Invalid register operand");
+      OS << "Reg:" << MRI->getName(Reg.RegNo);
+      break;
+    case Immediate:
+      printImmValue(Imm.Val, "Imm:");
+      break;
+    case Prefix:
+      OS << "Prefix:" << Pref.Prefixes;
+      break;
+    case Memory:
+      OS << "Memory: ModeSize=" << Mem.ModeSize;
+      if (Mem.Size)
+        OS << ",Size=" << Mem.Size;
+      if (Mem.BaseReg)
+        OS << ",BaseReg=" << Mem.BaseReg;
+      if (Mem.IndexReg)
+        OS << ",IndexReg=" << Mem.IndexReg;
+      if (Mem.Scale)
+        OS << ",Scale=" << Mem.Scale;
+      if (Mem.Disp)
+        printImmValue(Mem.Disp, ",Disp=");
+      if (Mem.SegReg)
+        OS << ",SegReg=" << Mem.SegReg;
+      break;
+    }
+  }
 
   StringRef getToken() const {
     assert(Kind == Token && "Invalid access!");
     return StringRef(Tok.Data, Tok.Length);
   }
   void setTokenValue(StringRef Value) {
     assert(Kind == Token && "Invalid access!");
     Tok.Data = Value.data();
static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
     auto Res = llvm::make_unique<X86Operand>(Token, Loc, EndLoc);
     Res->Tok.Data = Str.data();
     Res->Tok.Length = Str.size();
     return Res;
   }
 
   static std::unique_ptr<X86Operand>
   CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
-            bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
-            StringRef SymName = StringRef(), void *OpDecl = nullptr) {
-    auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc);
+            const MCRegisterInfo *MRI, bool AddressOf = false,
+            SMLoc OffsetOfLoc = SMLoc(), StringRef SymName = StringRef(),
+            void *OpDecl = nullptr) {
+    auto Res = llvm::make_unique<X86Operand>(Register, StartLoc, EndLoc, MRI);
     Res->Reg.RegNo = RegNo;
     Res->AddressOf = AddressOf;
     Res->OffsetOfLoc = OffsetOfLoc;
     Res->SymName = SymName;
     Res->OpDecl = OpDecl;
     return Res;
   }
 

test/MC/X86/x86_64-asm-match.s

 // RUN: llvm-mc -triple x86_64-unknown-unknown  -debug-only=asm-matcher  %s 2>&1 | FileCheck %s
 // REQUIRES: asserts
 
 // CHECK: AsmMatcher: found 4 encodings with mnemonic 'pshufb'
-// CHECK:Trying to match opcode MMX_PSHUFBrr64
-// CHECK:  Matching formal operand class MCK_VR64 against actual operand at index 1 (): Opcode result: multiple operand mismatches, ignoring this opcode
-// CHECK:Trying to match opcode PSHUFBrr
-// CHECK:  Matching formal operand class MCK_FR32 against actual operand at index 1 (): Opcode result: multiple operand mismatches, ignoring this opcode
-// CHECK:Trying to match opcode PSHUFBrm
-// CHECK:  Matching formal operand class MCK_Mem128 against actual operand at index 1 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_FR32 against actual operand at index 2 (): match success using generic matcher
-// CHECK:  Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
-// CHECK:AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4'
-// CHECK:Trying to match opcode SHA1RNDS4rri
-// CHECK:  Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_FR32 against actual operand at index 2 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_FR32 against actual operand at index 3 (): match success using generic matcher
-// CHECK:  Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
-// CHECK:AsmMatcher: found 4 encodings with mnemonic 'pinsrw'
-// CHECK:Trying to match opcode MMX_PINSRWirri
-// CHECK:  Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_VR64 against actual operand at index 3 (): Opcode result: multiple operand mismatches, ignoring this opcode
-// CHECK:Trying to match opcode PINSRWrri
-// CHECK:  Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_FR32 against actual operand at index 3 (): match success using generic matcher
-// CHECK:  Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
-// CHECK:AsmMatcher: found 2 encodings with mnemonic 'crc32l'
-// CHECK:Trying to match opcode CRC32r32r32
-// CHECK:  Matching formal operand class MCK_GR32 against actual operand at index 1 (): Opcode result: multiple operand mismatches, ignoring this opcode
-// CHECK:Trying to match opcode CRC32r32m32
-// CHECK:  Matching formal operand class MCK_Mem32 against actual operand at index 1 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_GR32 against actual operand at index 2 (): match success using generic matcher
-// CHECK:  Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
-// CHECK:AsmMatcher: found 4 encodings with mnemonic 'punpcklbw'
-// CHECK:Trying to match opcode MMX_PUNPCKLBWirr
-// CHECK:  Matching formal operand class MCK_VR64 against actual operand at index 1 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_VR64 against actual operand at index 2 (): Opcode result: multiple operand mismatches, ignoring this opcode
-// CHECK:Trying to match opcode MMX_PUNPCKLBWirm
-// CHECK:  Matching formal operand class MCK_VR64 against actual operand at index 1 (): match success using generic matcher
-// CHECK:  Matching formal operand class MCK_Mem32 against actual operand at index 2 (): match success using generic matcher
-// CHECK:  Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: Trying to match opcode MMX_PSHUFBrr64
+// CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=41,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring this opcode
+// CHECK: Trying to match opcode PSHUFBrr
+// CHECK:   Matching formal operand class MCK_FR32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=41,Scale=1,Disp=CPI1_0): Opcode result: multiple operand mismatches, ignoring this opcode
+// CHECK: Trying to match opcode PSHUFBrm
+// CHECK:   Matching formal operand class MCK_Mem128 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=41,Scale=1,Disp=CPI1_0): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_FR32 against actual operand at index 2 (Reg:XMM1): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 2 encodings with mnemonic 'sha1rnds4'
+// CHECK: Trying to match opcode SHA1RNDS4rri
+// CHECK:   Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:1): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_FR32 against actual operand at index 2 (Reg:XMM1): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_FR32 against actual operand at index 3 (Reg:XMM2): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 4 encodings with mnemonic 'pinsrw'
+// CHECK: Trying to match opcode MMX_PINSRWirri
+// CHECK:   Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ECX): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 3 (Reg:XMM5): Opcode result: multiple operand mismatches, ignoring this opcode
+// CHECK: Trying to match opcode PINSRWrri
+// CHECK:   Matching formal operand class MCK_ImmUnsignedi8 against actual operand at index 1 (Imm:3): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_GR32orGR64 against actual operand at index 2 (Reg:ECX): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_FR32 against actual operand at index 3 (Reg:XMM5): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 4: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 2 encodings with mnemonic 'crc32l'
+// CHECK: Trying to match opcode CRC32r32r32
+// CHECK:   Matching formal operand class MCK_GR32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=37,IndexReg=38,Scale=8,Disp=3735928559,SegReg=33): Opcode result: multiple operand mismatches, ignoring this opcode
+// CHECK: Trying to match opcode CRC32r32m32
+// CHECK:   Matching formal operand class MCK_Mem32 against actual operand at index 1 (Memory: ModeSize=64,BaseReg=37,IndexReg=38,Scale=8,Disp=3735928559,SegReg=33): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_GR32 against actual operand at index 2 (Reg:ECX): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
+// CHECK: AsmMatcher: found 4 encodings with mnemonic 'punpcklbw'
+// CHECK: Trying to match opcode MMX_PUNPCKLBWirr
+// CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Reg:MM0): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 2 (Memory: ModeSize=64,Size=32,BaseReg=44,Scale=1): Opcode result: multiple operand mismatches, ignoring this opcode
+// CHECK: Trying to match opcode MMX_PUNPCKLBWirm
+// CHECK:   Matching formal operand class MCK_VR64 against actual operand at index 1 (Reg:MM0): match success using generic matcher
+// CHECK:   Matching formal operand class MCK_Mem32 against actual operand at index 2 (Memory: ModeSize=64,Size=32,BaseReg=44,Scale=1): match success using generic matcher
+// CHECK:   Matching formal operand class InvalidMatchClass against actual operand at index 3: actual operand index out of range Opcode result: complete match, selecting this opcode
 
-
 pshufb    CPI1_0(%rip), %xmm1
 sha1rnds4 $1, %xmm1, %xmm2
 pinsrw    $3, %ecx, %xmm5
 crc32l    %gs:0xdeadbeef(%rbx,%rcx,8),%ecx
 
 .intel_syntax
 punpcklbw mm0, dword ptr [rsp]