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Differential D41186

[AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32
ClosedPublic

Authored by dp on Dec 13 2017, 9:27 AM.

Details

Reviewers
arsenm
artem.tamazov
Commits
rGc5b0c172f655: [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32
rL321367: [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32
Summary

See bug 35645: https://bugs.llvm.org/show_bug.cgi?id=35645

swizzle 'offset' is an optional operand but it has non-standard syntax compared with other optional operands.
So I decided to handle it separately.

Diff Detail

Event Timeline

dp created this revision.Dec 13 2017, 9:27 AM
Herald added subscribers: t-tye, tpr, dstuttard and 4 others. · View Herald TranscriptDec 13 2017, 9:27 AM
artem.tamazov accepted this revision.Dec 14 2017, 7:28 AM

LGTM.

This revision is now accepted and ready to land.Dec 14 2017, 7:28 AM
Closed by commit rL321367: [AMDGPU][MC] Corrected parsing of optional operands for ds_swizzle_b32 (authored by dpreobra). · Explain WhyDec 22 2017, 9:14 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

PathSize
lib/
Target/
AMDGPU/
AsmParser/
4 lines
test/
MC/
AMDGPU/
4 lines
Disassembler/
AMDGPU/
3 lines

Diff 126772

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Show First 20 Lines • Show All 3,832 Lines • ▼ Show 20 Lines if (skipToken(AsmToken::Colon, "expected a colon")) {
Ok = parseSwizzleOffset(Imm); Ok = parseSwizzleOffset(Imm);
} }
} }
Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle)); Operands.push_back(AMDGPUOperand::CreateImm(this, Imm, S, AMDGPUOperand::ImmTySwizzle));
return Ok? MatchOperand_Success : MatchOperand_ParseFail; return Ok? MatchOperand_Success : MatchOperand_ParseFail;
} else { } else {
return MatchOperand_NoMatch; // Swizzle "offset" operand is optional.
// If it is omitted, try parsing other optional operands.
return parseOptionalOperand(Operands);
} }
} }
bool bool
AMDGPUOperand::isSwizzle() const { AMDGPUOperand::isSwizzle() const {
return isImmTy(ImmTySwizzle); return isImmTy(ImmTySwizzle);
} }
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test/MC/AMDGPU/ds.s

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//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// swizzle // swizzle
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
ds_swizzle_b32 v8, v2 ds_swizzle_b32 v8, v2
// SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08] // SICI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0xd4,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08] // VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 gds
// SICI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0xd6,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:0xFFFF ds_swizzle_b32 v8, v2 offset:0xFFFF
// SICI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08] // SICI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0xd4,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x02,0x00,0x00,0x08] // VI: ds_swizzle_b32 v8, v2 offset:65535 ; encoding: [0xff,0xff,0x7a,0xd8,0x02,0x00,0x00,0x08]
ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3) ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM, 0, 1, 2, 3)
// SICI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,0,1,2,3) ; encoding: [0xe4,0x80,0xd4,0xd8,0x02,0x00,0x00,0x08] // SICI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,0,1,2,3) ; encoding: [0xe4,0x80,0xd4,0xd8,0x02,0x00,0x00,0x08]
// VI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,0,1,2,3) ; encoding: [0xe4,0x80,0x7a,0xd8,0x02,0x00,0x00,0x08] // VI: ds_swizzle_b32 v8, v2 offset:swizzle(QUAD_PERM,0,1,2,3) ; encoding: [0xe4,0x80,0x7a,0xd8,0x02,0x00,0x00,0x08]
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test/MC/Disassembler/AMDGPU/ds_vi.txt

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0x00 0x00 0x64 0xd8 0x02 0x04 0x00 0x08 0x00 0x00 0x64 0xd8 0x02 0x04 0x00 0x08
# VI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x00,0x08] # VI: ds_max_rtn_f32 v8, v2, v4 ; encoding: [0x00,0x00,0x66,0xd8,0x02,0x04,0x00,0x08]
0x00 0x00 0x66 0xd8 0x02 0x04 0x00 0x08 0x00 0x00 0x66 0xd8 0x02 0x04 0x00 0x08
# VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08] # VI: ds_swizzle_b32 v8, v2 ; encoding: [0x00,0x00,0x7a,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08 0x00 0x00 0x7a 0xd8 0x02 0x00 0x00 0x08
# VI: ds_swizzle_b32 v8, v2 gds ; encoding: [0x00,0x00,0x7b,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x7b 0xd8 0x02 0x00 0x00 0x08
# VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08] # VI: ds_read_b32 v8, v2 ; encoding: [0x00,0x00,0x6c,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08 0x00 0x00 0x6c 0xd8 0x02 0x00 0x00 0x08
# VI: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08] # VI: ds_read2_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x6e,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x6e 0xd8 0x02 0x00 0x00 0x08 0x00 0x00 0x6e 0xd8 0x02 0x00 0x00 0x08
# VI: ds_read2st64_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x70,0xd8,0x02,0x00,0x00,0x08] # VI: ds_read2st64_b32 v[8:9], v2 ; encoding: [0x00,0x00,0x70,0xd8,0x02,0x00,0x00,0x08]
0x00 0x00 0x70 0xd8 0x02 0x00 0x00 0x08 0x00 0x00 0x70 0xd8 0x02 0x00 0x00 0x08
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