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[AMDGPU][MC][GFX9] Corrected encoding of ttmp registers, disabled tba/tma
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Authored by dp on Dec 8 2017, 6:58 AM.

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rL LLVM

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dp created this revision.Dec 8 2017, 6:58 AM
artem.tamazov requested changes to this revision.Dec 8 2017, 7:35 AM

Very good, but looks like some minor fixes are needed.

lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
636 ↗(On Diff #126138)

I do not think we should assert here for Gfx9. Just "break" looks enough.

662 ↗(On Diff #126138)

Ditto.

This revision now requires changes to proceed.Dec 8 2017, 7:35 AM
dp added inline comments.Dec 8 2017, 7:46 AM
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
636 ↗(On Diff #126138)

I assert'ed these lines because they are not reachable in the current implementation (ttmp registers are handled first).
An assert will be helpful to make sure future changes take into account this assumption.

Do you suggest to replace asserts with breaks?

case 108: if (isGFX9()) break; else return createRegOperand(TBA_LO);

I do not see why this code is better. It will hide real problem.

artem.tamazov added inline comments.Dec 8 2017, 7:50 AM
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
636 ↗(On Diff #126138)

Is it so that disassembler shall never hit this place with Gfx9 target?

dp added inline comments.Dec 8 2017, 7:51 AM
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
636 ↗(On Diff #126138)

Should we just delete assert's? This looks acceptable.

636 ↗(On Diff #126138)

Exactly

artem.tamazov added inline comments.Dec 8 2017, 7:57 AM
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
636 ↗(On Diff #126138)

I would even say this is valid. Otherwise the reader (like me) may get that false impression that dasm may hit this place of code for Gfx9.
BTW how Gfx9 dasm handles this?

s_add_u32 ttmp4, tba_lo, 4
dp added inline comments.Dec 8 2017, 8:11 AM
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
636 ↗(On Diff #126138)

tba/tma went away in gfx9; the freed sgpr range is now occupied by ttmp registers. So if ttmp registers are handled first, we never hit tba/tma.

Regarding the code

s_add_u32 ttmp4, tba_lo, 4

This code will be rejected by the parser. If you compile this for gfx8 and then disassemble for gfx9, the result will be:

s_add_u32 ttmp8, ttmp0, 4
artem.tamazov added inline comments.Dec 8 2017, 8:35 AM
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
636 ↗(On Diff #126138)

I think that cases 108..111 shall be handled for Gfx9 just like "unknown operand", e.g. case 252.

artem.tamazov accepted this revision.Dec 8 2017, 8:37 AM
This revision is now accepted and ready to land.Dec 8 2017, 8:37 AM
This revision was automatically updated to reflect the committed changes.