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Differential D40955

[AMDGPU] Make the new addr space mapping default
ClosedPublic

Authored by yaxunl on Dec 7 2017, 7:28 AM.

Details

Reviewers
arsenm
rampitec
b-sumner
t-tye
Commits
rG2a22c5deff38: [AMDGPU] Switch to the new addr space mapping by default
rL324101: [AMDGPU] Switch to the new addr space mapping by default
Summary

Will clean up the enum in another patch.

Diff Detail

Event Timeline

yaxunl created this revision.Dec 7 2017, 7:28 AM
Herald added subscribers: JDevlieghere, eraman, t-tye and 5 others. · View Herald TranscriptDec 7 2017, 7:28 AM
yaxunl mentioned this in D39560: [AMDGPU] Convert lit tests to new addr space mapping, part 1.Dec 7 2017, 7:51 AM
yaxunl added reviewers: b-sumner, t-tye.Dec 11 2017, 7:40 AM
arsenm added inline comments.Dec 11 2017, 2:37 PM
test/Analysis/CostModel/AMDGPU/addrspacecast.ll
1

That this is necessary is a bug. The specified triple should be sufficient

yaxunl updated this revision to Diff 127794.Dec 20 2017, 3:53 PM

Remove unnecessary datalayout from tests.

yaxunl added inline comments.Dec 20 2017, 6:16 PM
test/Analysis/CostModel/AMDGPU/addrspacecast.ll
1

Removed. Thanks.

yaxunl added inline comments.Jan 8 2018, 12:27 PM
test/Analysis/CostModel/AMDGPU/addrspacecast.ll
1

Fixed this issue in another patch https://reviews.llvm.org/D41832

yaxunl added a comment.Jan 16 2018, 2:38 PM

Ping.

Since https://reviews.llvm.org/D41832 is not trivial and may take some time, I am wondering if we should not let it block this patch.

yaxunl updated this revision to Diff 132256.Jan 31 2018, 12:48 PM

Update tests. Removed redundant data layout.

Herald added a subscriber: qcolombet. · View Herald TranscriptJan 31 2018, 12:48 PM
arsenm accepted this revision.Jan 31 2018, 5:06 PM

LGTM

This revision is now accepted and ready to land.Jan 31 2018, 5:06 PM
Closed by commit rL324101: [AMDGPU] Switch to the new addr space mapping by default (authored by yaxunl). · Explain WhyFeb 2 2018, 8:10 AM
This revision was automatically updated to reflect the committed changes.

Revision Contents

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lib/
Target/
AMDGPU/
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Utils/
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test/
Analysis/
CostModel/
AMDGPU/
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AMDGPU/
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Diff 132256

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Show First 20 Lines • Show All 254 Lines • ▼ Show 20 Lines
static MachineSchedRegistry static MachineSchedRegistry
GCNILPSchedRegistry("gcn-ilp", GCNILPSchedRegistry("gcn-ilp",
"Run GCN iterative scheduler for ILP scheduling (experimental)", "Run GCN iterative scheduler for ILP scheduling (experimental)",
createIterativeILPMachineScheduler); createIterativeILPMachineScheduler);
static StringRef computeDataLayout(const Triple &TT) { static StringRef computeDataLayout(const Triple &TT) {
if (TT.getArch() == Triple::r600) { if (TT.getArch() == Triple::r600) {
// 32-bit pointers. // 32-bit pointers.
if (TT.getEnvironmentName() == "amdgiz" ||
TT.getEnvironmentName() == "amdgizcl")
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
return "e-p:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
} }
// 32-bit private, local, and region pointers. 64-bit global, constant and // 32-bit private, local, and region pointers. 64-bit global, constant and
// flat. // flat.
if (TT.getEnvironmentName() == "amdgiz" ||
TT.getEnvironmentName() == "amdgizcl")
return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32" return "e-p:64:64-p1:64:64-p2:64:64-p3:32:32-p4:32:32-p5:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128" "-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"; "-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5";
return "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32"
"-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128"
"-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64";
} }
LLVM_READNONE LLVM_READNONE
static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) { static StringRef getGPUOrDefault(const Triple &TT, StringRef GPU) {
if (!GPU.empty()) if (!GPU.empty())
return GPU; return GPU;
if (TT.getArch() == Triple::amdgcn) if (TT.getArch() == Triple::amdgcn)
▲ Show 20 Lines • Show All 611 Lines • Show Last 20 Lines

lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp

Show First 20 Lines • Show All 931 Lines • ▼ Show 20 Lines
} // end namespace llvm } // end namespace llvm
namespace llvm { namespace llvm {
namespace AMDGPU { namespace AMDGPU {
AMDGPUAS getAMDGPUAS(Triple T) { AMDGPUAS getAMDGPUAS(Triple T) {
auto Env = T.getEnvironmentName(); auto Env = T.getEnvironmentName();
AMDGPUAS AS; AMDGPUAS AS;
if (Env == "amdgiz" || Env == "amdgizcl") {
AS.FLAT_ADDRESS = 0; AS.FLAT_ADDRESS = 0;
AS.PRIVATE_ADDRESS = 5; AS.PRIVATE_ADDRESS = 5;
AS.REGION_ADDRESS = 4; AS.REGION_ADDRESS = 4;
}
else {
AS.FLAT_ADDRESS = 4;
AS.PRIVATE_ADDRESS = 0;
AS.REGION_ADDRESS = 5;
}
return AS; return AS;
} }
AMDGPUAS getAMDGPUAS(const TargetMachine &M) { AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
return getAMDGPUAS(M.getTargetTriple()); return getAMDGPUAS(M.getTargetTriple());
} }
AMDGPUAS getAMDGPUAS(const Module &M) { AMDGPUAS getAMDGPUAS(const Module &M) {
return getAMDGPUAS(Triple(M.getTargetTriple())); return getAMDGPUAS(Triple(M.getTargetTriple()));
} }
} // namespace AMDGPU } // namespace AMDGPU
} // namespace llvm } // namespace llvm

test/Analysis/CostModel/AMDGPU/addrspacecast.ll

; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri < %s | FileCheck %s ; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri < %s | FileCheck %s
arsenmUnsubmitted
Not Done
ReplyInline Actions

That this is necessary is a bug. The specified triple should be sufficient

arsenm: That this is necessary is a bug. The specified triple should be sufficient
yaxunlAuthorUnsubmitted
Not Done
ReplyInline Actions

Removed. Thanks.

yaxunl: Removed. Thanks.
yaxunlAuthorUnsubmitted
Not Done
ReplyInline Actions

Fixed this issue in another patch https://reviews.llvm.org/D41832

yaxunl: Fixed this issue in another patch https://reviews.llvm.org/D41832
; CHECK: 'addrspacecast_global_to_flat' ; CHECK: 'addrspacecast_global_to_flat'
; CHECK: estimated cost of 0 for {{.*}} addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(4)* ; CHECK: estimated cost of 0 for {{.*}} addrspacecast i8 addrspace(1)* %ptr to i8*
define i8 addrspace(4)* @addrspacecast_global_to_flat(i8 addrspace(1)* %ptr) #0 { define i8* @addrspacecast_global_to_flat(i8 addrspace(1)* %ptr) #0 {
%cast = addrspacecast i8 addrspace(1)* %ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(1)* %ptr to i8*
ret i8 addrspace(4)* %cast ret i8* %cast
} }
; CHECK: 'addrspacecast_global_to_flat_v2' ; CHECK: 'addrspacecast_global_to_flat_v2'
; CHECK: estimated cost of 0 for {{.*}} addrspacecast <2 x i8 addrspace(1)*> %ptr to <2 x i8 addrspace(4)*> ; CHECK: estimated cost of 0 for {{.*}} addrspacecast <2 x i8 addrspace(1)*> %ptr to <2 x i8*>
define <2 x i8 addrspace(4)*> @addrspacecast_global_to_flat_v2(<2 x i8 addrspace(1)*> %ptr) #0 { define <2 x i8*> @addrspacecast_global_to_flat_v2(<2 x i8 addrspace(1)*> %ptr) #0 {
%cast = addrspacecast <2 x i8 addrspace(1)*> %ptr to <2 x i8 addrspace(4)*> %cast = addrspacecast <2 x i8 addrspace(1)*> %ptr to <2 x i8*>
ret <2 x i8 addrspace(4)*> %cast ret <2 x i8*> %cast
} }
; CHECK: 'addrspacecast_global_to_flat_v32' ; CHECK: 'addrspacecast_global_to_flat_v32'
; CHECK: estimated cost of 0 for {{.*}} addrspacecast <32 x i8 addrspace(1)*> %ptr to <32 x i8 addrspace(4)*> ; CHECK: estimated cost of 0 for {{.*}} addrspacecast <32 x i8 addrspace(1)*> %ptr to <32 x i8*>
define <32 x i8 addrspace(4)*> @addrspacecast_global_to_flat_v32(<32 x i8 addrspace(1)*> %ptr) #0 { define <32 x i8*> @addrspacecast_global_to_flat_v32(<32 x i8 addrspace(1)*> %ptr) #0 {
%cast = addrspacecast <32 x i8 addrspace(1)*> %ptr to <32 x i8 addrspace(4)*> %cast = addrspacecast <32 x i8 addrspace(1)*> %ptr to <32 x i8*>
ret <32 x i8 addrspace(4)*> %cast ret <32 x i8*> %cast
} }
; CHECK: 'addrspacecast_local_to_flat' ; CHECK: 'addrspacecast_local_to_flat'
; CHECK: estimated cost of 1 for {{.*}} addrspacecast i8 addrspace(3)* %ptr to i8 addrspace(4)* ; CHECK: estimated cost of 1 for {{.*}} addrspacecast i8 addrspace(3)* %ptr to i8*
define i8 addrspace(4)* @addrspacecast_local_to_flat(i8 addrspace(3)* %ptr) #0 { define i8* @addrspacecast_local_to_flat(i8 addrspace(3)* %ptr) #0 {
%cast = addrspacecast i8 addrspace(3)* %ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(3)* %ptr to i8*
ret i8 addrspace(4)* %cast ret i8* %cast
} }
; CHECK: 'addrspacecast_local_to_flat_v2' ; CHECK: 'addrspacecast_local_to_flat_v2'
; CHECK: estimated cost of 2 for {{.*}} addrspacecast <2 x i8 addrspace(3)*> %ptr to <2 x i8 addrspace(4)*> ; CHECK: estimated cost of 2 for {{.*}} addrspacecast <2 x i8 addrspace(3)*> %ptr to <2 x i8*>
define <2 x i8 addrspace(4)*> @addrspacecast_local_to_flat_v2(<2 x i8 addrspace(3)*> %ptr) #0 { define <2 x i8*> @addrspacecast_local_to_flat_v2(<2 x i8 addrspace(3)*> %ptr) #0 {
%cast = addrspacecast <2 x i8 addrspace(3)*> %ptr to <2 x i8 addrspace(4)*> %cast = addrspacecast <2 x i8 addrspace(3)*> %ptr to <2 x i8*>
ret <2 x i8 addrspace(4)*> %cast ret <2 x i8*> %cast
} }
; CHECK: 'addrspacecast_local_to_flat_v32' ; CHECK: 'addrspacecast_local_to_flat_v32'
; CHECK: estimated cost of 32 for {{.*}} addrspacecast <32 x i8 addrspace(3)*> %ptr to <32 x i8 addrspace(4)*> ; CHECK: estimated cost of 32 for {{.*}} addrspacecast <32 x i8 addrspace(3)*> %ptr to <32 x i8*>
define <32 x i8 addrspace(4)*> @addrspacecast_local_to_flat_v32(<32 x i8 addrspace(3)*> %ptr) #0 { define <32 x i8*> @addrspacecast_local_to_flat_v32(<32 x i8 addrspace(3)*> %ptr) #0 {
%cast = addrspacecast <32 x i8 addrspace(3)*> %ptr to <32 x i8 addrspace(4)*> %cast = addrspacecast <32 x i8 addrspace(3)*> %ptr to <32 x i8*>
ret <32 x i8 addrspace(4)*> %cast ret <32 x i8*> %cast
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }

test/CodeGen/AMDGPU/InlineAsmCrash.ll

; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; CHECK: ;;#ASMSTART ; CHECK: ;;#ASMSTART
; CHECK-NEXT: s_nop 0 ; CHECK-NEXT: s_nop 0
; CHECK-NEXT: ;;#ASMEND ; CHECK-NEXT: ;;#ASMEND
define void @foo(i32* %ptr) { define void @foo(i32 addrspace(5)* %ptr) {
%tmp = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "s_nop 0", "=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65"(i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2) %tmp = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm "s_nop 0", "=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,=v,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,39,40,41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,57,58,59,60,61,62,63,64,65"(i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2, i32 2)
%tmp2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %tmp, 0 %tmp2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %tmp, 0
store i32 %tmp2, i32* %ptr, align 4 store i32 %tmp2, i32 addrspace(5)* %ptr, align 4
ret void ret void
} }

test/CodeGen/AMDGPU/addrspacecast.ll

Show All 29 Lines
; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
; At most 2 digits. Make sure src_shared_base is not counted as a high ; At most 2 digits. Make sure src_shared_base is not counted as a high
; number SGPR. ; number SGPR.
; CI: NumSgprs: {{[0-9][0-9]+}} ; CI: NumSgprs: {{[0-9][0-9]+}}
; GFX9: NumSgprs: {{[0-9]+}} ; GFX9: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 7, i32 addrspace(4)* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast: ; HSA-LABEL: {{^}}use_private_to_flat_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; CI: enable_sgpr_queue_ptr = 1 ; CI: enable_sgpr_queue_ptr = 1
; GFX9: enable_sgpr_queue_ptr = 0 ; GFX9: enable_sgpr_queue_ptr = 0
Show All 20 Lines
; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc ; GFX9: v_cndmask_b32_e32 v[[HI:[0-9]+]], 0, [[VAPERTURE]], vcc
; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]] ; GFX9: v_mov_b32_e32 [[VPTR:v[0-9]+]], [[PTR]]
; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]] ; GFX9-DAG: v_cndmask_b32_e32 v[[LO:[0-9]+]], 0, [[VPTR]]
; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]] ; HSA: flat_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, [[K]]
; CI: NumSgprs: {{[0-9][0-9]+}} ; CI: NumSgprs: {{[0-9][0-9]+}}
; GFX9: NumSgprs: {{[0-9]+}} ; GFX9: NumSgprs: {{[0-9]+}}
define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32* %ptr) #0 { define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #0 {
%stof = addrspacecast i32* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(5)* %ptr to i32*
store volatile i32 7, i32 addrspace(4)* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
; no-op ; no-op
; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast: ; HSA-LABEL: {{^}}use_global_to_flat_addrspacecast:
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7
; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] ; HSA: flat_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 { define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(1)* %ptr to i32*
store volatile i32 7, i32 addrspace(4)* %stof store volatile i32 7, i32* %stof
ret void ret void
} }
; no-op ; no-op
; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast: ; HSA-LABEl: {{^}}use_constant_to_flat_addrspacecast:
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}} ; HSA: flat_load_dword v{{[0-9]+}}, v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}
define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #0 { define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #0 {
%stof = addrspacecast i32 addrspace(2)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(2)* %ptr to i32*
%ld = load volatile i32, i32 addrspace(4)* %stof %ld = load volatile i32, i32* %stof
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_group_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}
; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} ; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]] ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], -1, v[[VPTR_LO]]
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
; HSA: ds_write_b32 [[CASTPTR]], v[[K]] ; HSA: ds_write_b32 [[CASTPTR]], v[[K]]
define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(3)* %ftos = addrspacecast i32* %ptr to i32 addrspace(3)*
store volatile i32 0, i32 addrspace(3)* %ftos store volatile i32 0, i32 addrspace(3)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_private_addrspacecast:
; HSA: enable_sgpr_private_segment_buffer = 1 ; HSA: enable_sgpr_private_segment_buffer = 1
; HSA: enable_sgpr_dispatch_ptr = 0 ; HSA: enable_sgpr_dispatch_ptr = 0
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}} ; HSA: s_load_dwordx2 s{{\[}}[[PTR_LO:[0-9]+]]:[[PTR_HI:[0-9]+]]{{\]}}
; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}} ; HSA-DAG: v_cmp_ne_u64_e64 vcc, s{{\[}}[[PTR_LO]]:[[PTR_HI]]{{\]}}, 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTR_LO:[0-9]+]], s[[PTR_LO]]
; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], 0, v[[VPTR_LO]] ; HSA-DAG: v_cndmask_b32_e32 [[CASTPTR:v[0-9]+]], 0, v[[VPTR_LO]]
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 0{{$}}
; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} ; HSA: buffer_store_dword v[[K]], [[CASTPTR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}
define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32* %ftos = addrspacecast i32* %ptr to i32 addrspace(5)*
store volatile i32 0, i32* %ftos store volatile i32 0, i32 addrspace(5)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_global_addrspacecast:
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRLO:[0-9]+]], s[[PTRLO]]
; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]] ; HSA-DAG: v_mov_b32_e32 v[[VPTRHI:[0-9]+]], s[[PTRHI]]
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0 ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0
; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[VPTRLO]]:[[VPTRHI]]{{\]}}, [[K]]
define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* %ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
store volatile i32 0, i32 addrspace(1)* %ftos store volatile i32 0, i32 addrspace(1)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast: ; HSA-LABEL: {{^}}use_flat_to_constant_addrspacecast:
; HSA: enable_sgpr_queue_ptr = 0 ; HSA: enable_sgpr_queue_ptr = 0
; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0 ; HSA: s_load_dwordx2 s{{\[}}[[PTRLO:[0-9]+]]:[[PTRHI:[0-9]+]]{{\]}}, s[4:5], 0x0
; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0 ; HSA: s_load_dword s{{[0-9]+}}, s{{\[}}[[PTRLO]]:[[PTRHI]]{{\]}}, 0x0
define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #0 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(2)* %ftos = addrspacecast i32* %ptr to i32 addrspace(2)*
load volatile i32, i32 addrspace(2)* %ftos load volatile i32, i32 addrspace(2)* %ftos
ret void ret void
} }
; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}cast_0_group_to_flat_addrspacecast:
; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10 ; CI: s_load_dword [[APERTURE:s[0-9]+]], s[4:5], 0x10
; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]] ; CI-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE]]
; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16) ; GFX9-DAG: s_getreg_b32 [[SSRC_SHARED:s[0-9]+]], hwreg(HW_REG_SH_MEM_BASES, 16, 16)
; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16 ; GFX9-DAG: s_lshl_b32 [[SSRC_SHARED_BASE:s[0-9]+]], [[SSRC_SHARED]], 16
; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]] ; GFX9-DAG: v_mov_b32_e32 v[[HI:[0-9]+]], [[SSRC_SHARED_BASE]]
; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base ; GFX9-XXX: v_mov_b32_e32 v[[HI:[0-9]+]], src_shared_base
; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_0_group_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(3)* null to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* null to i32*
store volatile i32 7, i32 addrspace(4)* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast: ; HSA-LABEL: {{^}}cast_0_flat_to_group_addrspacecast:
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: ds_write_b32 [[PTR]], [[K]] ; HSA: ds_write_b32 [[PTR]], [[K]]
define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 { define amdgpu_kernel void @cast_0_flat_to_group_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(4)* null to i32 addrspace(3)* %cast = addrspacecast i32* null to i32 addrspace(3)*
store volatile i32 7, i32 addrspace(3)* %cast store volatile i32 7, i32 addrspace(3)* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast: ; HSA-LABEL: {{^}}cast_neg1_group_to_flat_addrspacecast:
; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; HSA: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_neg1_group_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* inttoptr (i32 -1 to i32 addrspace(3)*) to i32*
store volatile i32 7, i32 addrspace(4)* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast: ; HSA-LABEL: {{^}}cast_neg1_flat_to_group_addrspacecast:
; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}} ; HSA-DAG: v_mov_b32_e32 [[PTR:v[0-9]+]], -1{{$}}
; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: ds_write_b32 [[PTR]], [[K]] ; HSA: ds_write_b32 [[PTR]], [[K]]
define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 { define amdgpu_kernel void @cast_neg1_flat_to_group_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(4)* inttoptr (i64 -1 to i32 addrspace(4)*) to i32 addrspace(3)* %cast = addrspacecast i32* inttoptr (i64 -1 to i32*) to i32 addrspace(3)*
store volatile i32 7, i32 addrspace(3)* %cast store volatile i32 7, i32 addrspace(3)* %cast
ret void ret void
} }
; FIXME: Shouldn't need to enable queue ptr ; FIXME: Shouldn't need to enable queue ptr
; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast: ; HSA-LABEL: {{^}}cast_0_private_to_flat_addrspacecast:
; CI: enable_sgpr_queue_ptr = 1 ; CI: enable_sgpr_queue_ptr = 1
; GFX9: enable_sgpr_queue_ptr = 0 ; GFX9: enable_sgpr_queue_ptr = 0
; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}} ; HSA-DAG: v_mov_b32_e32 v[[LO:[0-9]+]], 0{{$}}
; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}} ; HSA-DAG: v_mov_b32_e32 v[[K:[0-9]+]], 7{{$}}
; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}} ; HSA: v_mov_b32_e32 v[[HI:[0-9]+]], 0{{$}}
; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]] ; HSA: {{flat|global}}_store_dword v{{\[}}[[LO]]:[[HI]]{{\]}}, v[[K]]
define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 { define amdgpu_kernel void @cast_0_private_to_flat_addrspacecast() #0 {
%cast = addrspacecast i32* null to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(5)* null to i32*
store volatile i32 7, i32 addrspace(4)* %cast store volatile i32 7, i32* %cast
ret void ret void
} }
; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast: ; HSA-LABEL: {{^}}cast_0_flat_to_private_addrspacecast:
; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}} ; HSA: v_mov_b32_e32 [[K:v[0-9]+]], 7{{$}}
; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}} ; HSA: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+$}}
define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 { define amdgpu_kernel void @cast_0_flat_to_private_addrspacecast() #0 {
%cast = addrspacecast i32 addrspace(4)* null to i32 addrspace(0)* %cast = addrspacecast i32* null to i32 addrspace(5)*
store volatile i32 7, i32* %cast store volatile i32 7, i32 addrspace(5)* %cast
ret void ret void
} }
; Disable optimizations in case there are optimizations added that ; Disable optimizations in case there are optimizations added that
; specialize away generic pointer accesses. ; specialize away generic pointer accesses.
; HSA-LABEL: {{^}}branch_use_flat_i32: ; HSA-LABEL: {{^}}branch_use_flat_i32:
; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}} ; HSA: {{flat|global}}_store_dword {{v\[[0-9]+:[0-9]+\]}}, {{v[0-9]+}}
; HSA: s_endpgm ; HSA: s_endpgm
define amdgpu_kernel void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 { define amdgpu_kernel void @branch_use_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* %gptr, i32 addrspace(3)* %lptr, i32 %x, i32 %c) #0 {
entry: entry:
%cmp = icmp ne i32 %c, 0 %cmp = icmp ne i32 %c, 0
br i1 %cmp, label %local, label %global br i1 %cmp, label %local, label %global
local: local:
%flat_local = addrspacecast i32 addrspace(3)* %lptr to i32 addrspace(4)* %flat_local = addrspacecast i32 addrspace(3)* %lptr to i32*
br label %end br label %end
global: global:
%flat_global = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* %flat_global = addrspacecast i32 addrspace(1)* %gptr to i32*
br label %end br label %end
end: end:
%fptr = phi i32 addrspace(4)* [ %flat_local, %local ], [ %flat_global, %global ] %fptr = phi i32* [ %flat_local, %local ], [ %flat_global, %global ]
store volatile i32 %x, i32 addrspace(4)* %fptr, align 4 store volatile i32 %x, i32* %fptr, align 4
; %val = load i32, i32 addrspace(4)* %fptr, align 4 ; %val = load i32, i32* %fptr, align 4
; store i32 %val, i32 addrspace(1)* %out, align 4 ; store i32 %val, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; Check for prologue initializing special SGPRs pointing to scratch. ; Check for prologue initializing special SGPRs pointing to scratch.
; HSA-LABEL: {{^}}store_flat_scratch: ; HSA-LABEL: {{^}}store_flat_scratch:
; CI-DAG: s_mov_b32 flat_scratch_lo, s9 ; CI-DAG: s_mov_b32 flat_scratch_lo, s9
; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11 ; CI-DAG: s_add_u32 [[ADD:s[0-9]+]], s8, s11
; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8 ; CI: s_lshr_b32 flat_scratch_hi, [[ADD]], 8
; GFX9: s_add_u32 flat_scratch_lo, s6, s9 ; GFX9: s_add_u32 flat_scratch_lo, s6, s9
; GFX9: s_addc_u32 flat_scratch_hi, s7, 0 ; GFX9: s_addc_u32 flat_scratch_hi, s7, 0
; HSA: {{flat|global}}_store_dword ; HSA: {{flat|global}}_store_dword
; HSA: s_barrier ; HSA: s_barrier
; HSA: {{flat|global}}_load_dword ; HSA: {{flat|global}}_load_dword
define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 { define amdgpu_kernel void @store_flat_scratch(i32 addrspace(1)* noalias %out, i32) #0 {
%alloca = alloca i32, i32 9, align 4 %alloca = alloca i32, i32 9, align 4, addrspace(5)
%x = call i32 @llvm.amdgcn.workitem.id.x() #2 %x = call i32 @llvm.amdgcn.workitem.id.x() #2
%pptr = getelementptr i32, i32* %alloca, i32 %x %pptr = getelementptr i32, i32 addrspace(5)* %alloca, i32 %x
%fptr = addrspacecast i32* %pptr to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(5)* %pptr to i32*
store volatile i32 %x, i32 addrspace(4)* %fptr store volatile i32 %x, i32* %fptr
; Dummy call ; Dummy call
call void @llvm.amdgcn.s.barrier() #1 call void @llvm.amdgcn.s.barrier() #1
%reload = load volatile i32, i32 addrspace(4)* %fptr, align 4 %reload = load volatile i32, i32* %fptr, align 4
store volatile i32 %reload, i32 addrspace(1)* %out, align 4 store volatile i32 %reload, i32 addrspace(1)* %out, align 4
ret void ret void
} }
declare void @llvm.amdgcn.s.barrier() #1 declare void @llvm.amdgcn.s.barrier() #1
declare i32 @llvm.amdgcn.workitem.id.x() #2 declare i32 @llvm.amdgcn.workitem.id.x() #2
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind convergent } attributes #1 = { nounwind convergent }
attributes #2 = { nounwind readnone } attributes #2 = { nounwind readnone }

test/CodeGen/AMDGPU/amdgcn.private-memory.ll

Show All 11 Lines
; Make sure we don't overwrite workitem information with private memory ; Make sure we don't overwrite workitem information with private memory
; GCN-LABEL: {{^}}work_item_info: ; GCN-LABEL: {{^}}work_item_info:
; GCN-NOT: v0 ; GCN-NOT: v0
; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v0, v{{[0-9]+}} ; GCN: v_add_{{[iu]}}32_e32 [[RESULT:v[0-9]+]], vcc, v0, v{{[0-9]+}}
; GCN: buffer_store_dword [[RESULT]] ; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
entry: entry:
%0 = alloca [2 x i32] %0 = alloca [2 x i32], addrspace(5)
%1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0 %1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
%2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1 %2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
store i32 0, i32* %1 store i32 0, i32 addrspace(5)* %1
store i32 1, i32* %2 store i32 1, i32 addrspace(5)* %2
%3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in %3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in
%4 = load i32, i32* %3 %4 = load i32, i32 addrspace(5)* %3
%5 = call i32 @llvm.amdgcn.workitem.id.x() %5 = call i32 @llvm.amdgcn.workitem.id.x()
%6 = add i32 %4, %5 %6 = add i32 %4, %5
store i32 %6, i32 addrspace(1)* %out store i32 %6, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/amdgpu-alias-analysis.ll

; RUN: opt -mtriple=amdgcn-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s ; RUN: opt -mtriple=amdgcn-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s
; RUN: opt -mtriple=r600-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s ; RUN: opt -mtriple=r600-- -O3 -aa-eval -print-all-alias-modref-info -disable-output < %s 2>&1 | FileCheck %s
; CHECK: NoAlias: i8 addrspace(1)* %p1, i8* %p ; CHECK: NoAlias: i8 addrspace(1)* %p1, i8 addrspace(5)* %p
define void @test(i8* %p, i8 addrspace(1)* %p1) { define void @test(i8 addrspace(5)* %p, i8 addrspace(1)* %p1) {
ret void ret void
} }

test/CodeGen/AMDGPU/amdgpu-inline.ll

; RUN: opt -mtriple=amdgcn--amdhsa -O3 -S -amdgpu-function-calls -inline-threshold=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INL1 %s ; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -amdgpu-function-calls -inline-threshold=1 < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INL1 %s
; RUN: opt -mtriple=amdgcn--amdhsa -O3 -S -amdgpu-function-calls < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INLDEF %s ; RUN: opt -mtriple=amdgcn--amdhsa -data-layout=A5 -O3 -S -amdgpu-function-calls < %s | FileCheck -check-prefix=GCN -check-prefix=GCN-INLDEF %s
define coldcc float @foo(float %x, float %y) { define coldcc float @foo(float %x, float %y) {
entry: entry:
%cmp = fcmp ogt float %x, 0.000000e+00 %cmp = fcmp ogt float %x, 0.000000e+00
%div = fdiv float %y, %x %div = fdiv float %y, %x
%mul = fmul float %x, %y %mul = fmul float %x, %y
%cond = select i1 %cmp, float %div, float %mul %cond = select i1 %cmp, float %div, float %mul
ret float %cond ret float %cond
} }
define coldcc void @foo_private_ptr(float* nocapture %p) { define coldcc void @foo_private_ptr(float addrspace(5)* nocapture %p) {
entry: entry:
%tmp1 = load float, float* %p, align 4 %tmp1 = load float, float addrspace(5)* %p, align 4
%cmp = fcmp ogt float %tmp1, 1.000000e+00 %cmp = fcmp ogt float %tmp1, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
%div = fdiv float 1.000000e+00, %tmp1 %div = fdiv float 1.000000e+00, %tmp1
store float %div, float* %p, align 4 store float %div, float addrspace(5)* %p, align 4
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret void ret void
} }
define coldcc void @foo_private_ptr2(float* nocapture %p1, float* nocapture %p2) { define coldcc void @foo_private_ptr2(float addrspace(5)* nocapture %p1, float addrspace(5)* nocapture %p2) {
entry: entry:
%tmp1 = load float, float* %p1, align 4 %tmp1 = load float, float addrspace(5)* %p1, align 4
%cmp = fcmp ogt float %tmp1, 1.000000e+00 %cmp = fcmp ogt float %tmp1, 1.000000e+00
br i1 %cmp, label %if.then, label %if.end br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry if.then: ; preds = %entry
%div = fdiv float 2.000000e+00, %tmp1 %div = fdiv float 2.000000e+00, %tmp1
store float %div, float* %p2, align 4 store float %div, float addrspace(5)* %p2, align 4
br label %if.end br label %if.end
if.end: ; preds = %if.then, %entry if.end: ; preds = %if.then, %entry
ret void ret void
} }
define coldcc float @sin_wrapper(float %x) { define coldcc float @sin_wrapper(float %x) {
bb: bb:
%call = tail call float @_Z3sinf(float %x) %call = tail call float @_Z3sinf(float %x)
ret float %call ret float %call
} }
define void @foo_noinline(float* nocapture %p) #0 { define void @foo_noinline(float addrspace(5)* nocapture %p) #0 {
entry: entry:
%tmp1 = load float, float* %p, align 4 %tmp1 = load float, float addrspace(5)* %p, align 4
%mul = fmul float %tmp1, 2.000000e+00 %mul = fmul float %tmp1, 2.000000e+00
store float %mul, float* %p, align 4 store float %mul, float addrspace(5)* %p, align 4
ret void ret void
} }
; GCN: define amdgpu_kernel void @test_inliner( ; GCN: define amdgpu_kernel void @test_inliner(
; GCN-INL1: %c1 = tail call coldcc float @foo( ; GCN-INL1: %c1 = tail call coldcc float @foo(
; GCN-INLDEF: %cmp.i = fcmp ogt float %tmp2, 0.000000e+00 ; GCN-INLDEF: %cmp.i = fcmp ogt float %tmp2, 0.000000e+00
; GCN: %div.i{{[0-9]*}} = fdiv float 1.000000e+00, %c ; GCN: %div.i{{[0-9]*}} = fdiv float 1.000000e+00, %c
; GCN: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i ; GCN: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
; GCN: call void @foo_noinline( ; GCN: call void @foo_noinline(
; GCN: tail call float @_Z3sinf( ; GCN: tail call float @_Z3sinf(
define amdgpu_kernel void @test_inliner(float addrspace(1)* nocapture %a, i32 %n) { define amdgpu_kernel void @test_inliner(float addrspace(1)* nocapture %a, i32 %n) {
entry: entry:
%pvt_arr = alloca [64 x float], align 4 %pvt_arr = alloca [64 x float], align 4, addrspace(5)
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
%tmp2 = load float, float addrspace(1)* %arrayidx, align 4 %tmp2 = load float, float addrspace(1)* %arrayidx, align 4
%add = add i32 %tid, 1 %add = add i32 %tid, 1
%arrayidx2 = getelementptr inbounds float, float addrspace(1)* %a, i32 %add %arrayidx2 = getelementptr inbounds float, float addrspace(1)* %a, i32 %add
%tmp5 = load float, float addrspace(1)* %arrayidx2, align 4 %tmp5 = load float, float addrspace(1)* %arrayidx2, align 4
%c1 = tail call coldcc float @foo(float %tmp2, float %tmp5) %c1 = tail call coldcc float @foo(float %tmp2, float %tmp5)
%or = or i32 %tid, %n %or = or i32 %tid, %n
%arrayidx5 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %or %arrayidx5 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
store float %c1, float* %arrayidx5, align 4 store float %c1, float addrspace(5)* %arrayidx5, align 4
%arrayidx7 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %or %arrayidx7 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %or
call coldcc void @foo_private_ptr(float* %arrayidx7) call coldcc void @foo_private_ptr(float addrspace(5)* %arrayidx7)
%arrayidx8 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 1 %arrayidx8 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 1
%arrayidx9 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 2 %arrayidx9 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 2
call coldcc void @foo_private_ptr2(float* %arrayidx8, float* %arrayidx9) call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
call void @foo_noinline(float* %arrayidx7) call void @foo_noinline(float addrspace(5)* %arrayidx7)
%and = and i32 %tid, %n %and = and i32 %tid, %n
%arrayidx11 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %and %arrayidx11 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %and
%tmp12 = load float, float* %arrayidx11, align 4 %tmp12 = load float, float addrspace(5)* %arrayidx11, align 4
%c2 = call coldcc float @sin_wrapper(float %tmp12) %c2 = call coldcc float @sin_wrapper(float %tmp12)
store float %c2, float* %arrayidx7, align 4 store float %c2, float addrspace(5)* %arrayidx7, align 4
%xor = xor i32 %tid, %n %xor = xor i32 %tid, %n
%arrayidx16 = getelementptr inbounds [64 x float], [64 x float]* %pvt_arr, i32 0, i32 %xor %arrayidx16 = getelementptr inbounds [64 x float], [64 x float] addrspace(5)* %pvt_arr, i32 0, i32 %xor
%tmp16 = load float, float* %arrayidx16, align 4 %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
store float %tmp16, float addrspace(1)* %arrayidx, align 4 store float %tmp16, float addrspace(1)* %arrayidx, align 4
ret void ret void
} }
; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr( ; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr(
; GCN: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i ; GCN: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
define amdgpu_kernel void @test_inliner_multi_pvt_ptr(float addrspace(1)* nocapture %a, i32 %n, float %v) { define amdgpu_kernel void @test_inliner_multi_pvt_ptr(float addrspace(1)* nocapture %a, i32 %n, float %v) {
entry: entry:
%pvt_arr1 = alloca [32 x float], align 4 %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
%pvt_arr2 = alloca [32 x float], align 4 %pvt_arr2 = alloca [32 x float], align 4, addrspace(5)
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
%or = or i32 %tid, %n %or = or i32 %tid, %n
%arrayidx4 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %or %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
%arrayidx5 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr2, i32 0, i32 %or %arrayidx5 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
store float %v, float* %arrayidx4, align 4 store float %v, float addrspace(5)* %arrayidx4, align 4
store float %v, float* %arrayidx5, align 4 store float %v, float addrspace(5)* %arrayidx5, align 4
%arrayidx8 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 1 %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
%arrayidx9 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr2, i32 0, i32 2 %arrayidx9 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
call coldcc void @foo_private_ptr2(float* %arrayidx8, float* %arrayidx9) call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
%xor = xor i32 %tid, %n %xor = xor i32 %tid, %n
%arrayidx15 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %xor %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
%arrayidx16 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr2, i32 0, i32 %xor %arrayidx16 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
%tmp15 = load float, float* %arrayidx15, align 4 %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
%tmp16 = load float, float* %arrayidx16, align 4 %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
%tmp17 = fadd float %tmp15, %tmp16 %tmp17 = fadd float %tmp15, %tmp16
store float %tmp17, float addrspace(1)* %arrayidx, align 4 store float %tmp17, float addrspace(1)* %arrayidx, align 4
ret void ret void
} }
; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff( ; GCN: define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(
; GCN-INL1: call coldcc void @foo_private_ptr2 ; GCN-INL1: call coldcc void @foo_private_ptr2
; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i ; GCN-INLDEF: %div.i{{[0-9]*}} = fdiv float 2.000000e+00, %tmp1.i
define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(float addrspace(1)* nocapture %a, i32 %n, float %v) { define amdgpu_kernel void @test_inliner_multi_pvt_ptr_cutoff(float addrspace(1)* nocapture %a, i32 %n, float %v) {
entry: entry:
%pvt_arr1 = alloca [32 x float], align 4 %pvt_arr1 = alloca [32 x float], align 4, addrspace(5)
%pvt_arr2 = alloca [33 x float], align 4 %pvt_arr2 = alloca [33 x float], align 4, addrspace(5)
%tid = tail call i32 @llvm.amdgcn.workitem.id.x() %tid = tail call i32 @llvm.amdgcn.workitem.id.x()
%arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid %arrayidx = getelementptr inbounds float, float addrspace(1)* %a, i32 %tid
%or = or i32 %tid, %n %or = or i32 %tid, %n
%arrayidx4 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %or %arrayidx4 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %or
%arrayidx5 = getelementptr inbounds [33 x float], [33 x float]* %pvt_arr2, i32 0, i32 %or %arrayidx5 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %or
store float %v, float* %arrayidx4, align 4 store float %v, float addrspace(5)* %arrayidx4, align 4
store float %v, float* %arrayidx5, align 4 store float %v, float addrspace(5)* %arrayidx5, align 4
%arrayidx8 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 1 %arrayidx8 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 1
%arrayidx9 = getelementptr inbounds [33 x float], [33 x float]* %pvt_arr2, i32 0, i32 2 %arrayidx9 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 2
call coldcc void @foo_private_ptr2(float* %arrayidx8, float* %arrayidx9) call coldcc void @foo_private_ptr2(float addrspace(5)* %arrayidx8, float addrspace(5)* %arrayidx9)
%xor = xor i32 %tid, %n %xor = xor i32 %tid, %n
%arrayidx15 = getelementptr inbounds [32 x float], [32 x float]* %pvt_arr1, i32 0, i32 %xor %arrayidx15 = getelementptr inbounds [32 x float], [32 x float] addrspace(5)* %pvt_arr1, i32 0, i32 %xor
%arrayidx16 = getelementptr inbounds [33 x float], [33 x float]* %pvt_arr2, i32 0, i32 %xor %arrayidx16 = getelementptr inbounds [33 x float], [33 x float] addrspace(5)* %pvt_arr2, i32 0, i32 %xor
%tmp15 = load float, float* %arrayidx15, align 4 %tmp15 = load float, float addrspace(5)* %arrayidx15, align 4
%tmp16 = load float, float* %arrayidx16, align 4 %tmp16 = load float, float addrspace(5)* %arrayidx16, align 4
%tmp17 = fadd float %tmp15, %tmp16 %tmp17 = fadd float %tmp15, %tmp16
store float %tmp17, float addrspace(1)* %arrayidx, align 4 store float %tmp17, float addrspace(1)* %arrayidx, align 4
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare float @_Z3sinf(float) #1 declare float @_Z3sinf(float) #1
attributes #0 = { noinline } attributes #0 = { noinline }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/amdgpu.private-memory.ll

; RUN: llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s ; RUN: llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn--amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-PROMOTE %s
; RUN: llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC ; RUN: llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -march=amdgcn < %s | FileCheck %s -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC
; RUN: llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s ; RUN: llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -mcpu=kaveri -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC -check-prefix=HSA-ALLOCA %s
; RUN: llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -show-mc-encoding -mattr=+promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-PROMOTE -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -show-mc-encoding -mattr=-promote-alloca -amdgpu-load-store-vectorizer=0 -enable-amdgpu-aa=0 -verify-machineinstrs -mtriple=amdgcn-amdhsa -march=amdgcn -mcpu=tonga -mattr=-unaligned-buffer-access < %s | FileCheck -enable-var-scope -check-prefix=SI-ALLOCA -check-prefix=SI -check-prefix=FUNC %s
; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck -enable-var-scope -check-prefix=HSAOPT -check-prefix=OPT %s
; RUN: opt -S -mtriple=amdgcn-unknown-unknown -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s ; RUN: opt -S -mtriple=amdgcn-unknown-unknown -data-layout=A5 -mcpu=kaveri -amdgpu-promote-alloca < %s | FileCheck -enable-var-scope -check-prefix=NOHSAOPT -check-prefix=OPT %s
; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
; HSAOPT: @mova_same_clause.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] undef, align 4 ; HSAOPT: @mova_same_clause.stack = internal unnamed_addr addrspace(3) global [256 x [5 x i32]] undef, align 4
; HSAOPT: @high_alignment.stack = internal unnamed_addr addrspace(3) global [256 x [8 x i32]] undef, align 16 ; HSAOPT: @high_alignment.stack = internal unnamed_addr addrspace(3) global [256 x [8 x i32]] undef, align 16
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; NOHSAOPT: call i32 @llvm.r600.read.local.size.y(), !range !0 ; NOHSAOPT: call i32 @llvm.r600.read.local.size.y(), !range !0
; NOHSAOPT: call i32 @llvm.r600.read.local.size.z(), !range !0 ; NOHSAOPT: call i32 @llvm.r600.read.local.size.z(), !range !0
; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.x(), !range !1 ; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.x(), !range !1
; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.y(), !range !1 ; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.y(), !range !1
; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.z(), !range !1 ; NOHSAOPT: call i32 @llvm.amdgcn.workitem.id.z(), !range !1
define amdgpu_kernel void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { define amdgpu_kernel void @mova_same_clause(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
} }
; OPT-LABEL: @high_alignment( ; OPT-LABEL: @high_alignment(
; OPT: getelementptr inbounds [256 x [8 x i32]], [256 x [8 x i32]] addrspace(3)* @high_alignment.stack, i32 0, i32 %{{[0-9]+}} ; OPT: getelementptr inbounds [256 x [8 x i32]], [256 x [8 x i32]] addrspace(3)* @high_alignment.stack, i32 0, i32 %{{[0-9]+}}
define amdgpu_kernel void @high_alignment(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { define amdgpu_kernel void @high_alignment(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
entry: entry:
%stack = alloca [8 x i32], align 16 %stack = alloca [8 x i32], align 16, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [8 x i32], [8 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
} }
; FUNC-LABEL: {{^}}no_replace_inbounds_gep: ; FUNC-LABEL: {{^}}no_replace_inbounds_gep:
; OPT-LABEL: @no_replace_inbounds_gep( ; OPT-LABEL: @no_replace_inbounds_gep(
; OPT: alloca [5 x i32] ; OPT: alloca [5 x i32]
; SI-NOT: ds_write ; SI-NOT: ds_write
define amdgpu_kernel void @no_replace_inbounds_gep(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { define amdgpu_kernel void @no_replace_inbounds_gep(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
} }
; This test checks that the stack offset is calculated correctly for structs. ; This test checks that the stack offset is calculated correctly for structs.
; All register loads/stores should be optimized away, so there shouldn't be ; All register loads/stores should be optimized away, so there shouldn't be
; any MOVA instructions. ; any MOVA instructions.
; ;
; XXX: This generated code has unnecessary MOVs, we should be able to optimize ; XXX: This generated code has unnecessary MOVs, we should be able to optimize
; this. ; this.
; FUNC-LABEL: {{^}}multiple_structs: ; FUNC-LABEL: {{^}}multiple_structs:
; OPT-LABEL: @multiple_structs( ; OPT-LABEL: @multiple_structs(
; R600-NOT: MOVA_INT ; R600-NOT: MOVA_INT
; SI-NOT: v_movrel ; SI-NOT: v_movrel
; SI-NOT: v_movrel ; SI-NOT: v_movrel
%struct.point = type { i32, i32 } %struct.point = type { i32, i32 }
define amdgpu_kernel void @multiple_structs(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @multiple_structs(i32 addrspace(1)* %out) #0 {
entry: entry:
%a = alloca %struct.point %a = alloca %struct.point, addrspace(5)
%b = alloca %struct.point %b = alloca %struct.point, addrspace(5)
%a.x.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0 %a.x.ptr = getelementptr %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0
%a.y.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 1 %a.y.ptr = getelementptr %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 1
%b.x.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0 %b.x.ptr = getelementptr %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0
%b.y.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 1 %b.y.ptr = getelementptr %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 1
store i32 0, i32* %a.x.ptr store i32 0, i32 addrspace(5)* %a.x.ptr
store i32 1, i32* %a.y.ptr store i32 1, i32 addrspace(5)* %a.y.ptr
store i32 2, i32* %b.x.ptr store i32 2, i32 addrspace(5)* %b.x.ptr
store i32 3, i32* %b.y.ptr store i32 3, i32 addrspace(5)* %b.y.ptr
%a.indirect.ptr = getelementptr %struct.point, %struct.point* %a, i32 0, i32 0 %a.indirect.ptr = getelementptr %struct.point, %struct.point addrspace(5)* %a, i32 0, i32 0
%b.indirect.ptr = getelementptr %struct.point, %struct.point* %b, i32 0, i32 0 %b.indirect.ptr = getelementptr %struct.point, %struct.point addrspace(5)* %b, i32 0, i32 0
%a.indirect = load i32, i32* %a.indirect.ptr %a.indirect = load i32, i32 addrspace(5)* %a.indirect.ptr
%b.indirect = load i32, i32* %b.indirect.ptr %b.indirect = load i32, i32 addrspace(5)* %b.indirect.ptr
%0 = add i32 %a.indirect, %b.indirect %0 = add i32 %a.indirect, %b.indirect
store i32 %0, i32 addrspace(1)* %out store i32 %0, i32 addrspace(1)* %out
ret void ret void
} }
; Test direct access of a private array inside a loop. The private array ; Test direct access of a private array inside a loop. The private array
; loads and stores should be lowered to copies, so there shouldn't be any ; loads and stores should be lowered to copies, so there shouldn't be any
; MOVA instructions. ; MOVA instructions.
; FUNC-LABEL: {{^}}direct_loop: ; FUNC-LABEL: {{^}}direct_loop:
; R600-NOT: MOVA_INT ; R600-NOT: MOVA_INT
; SI-NOT: v_movrel ; SI-NOT: v_movrel
define amdgpu_kernel void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 { define amdgpu_kernel void @direct_loop(i32 addrspace(1)* %out, i32 addrspace(1)* %in) #0 {
entry: entry:
%prv_array_const = alloca [2 x i32] %prv_array_const = alloca [2 x i32], addrspace(5)
%prv_array = alloca [2 x i32] %prv_array = alloca [2 x i32], addrspace(5)
%a = load i32, i32 addrspace(1)* %in %a = load i32, i32 addrspace(1)* %in
%b_src_ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %b_src_ptr = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%b = load i32, i32 addrspace(1)* %b_src_ptr %b = load i32, i32 addrspace(1)* %b_src_ptr
%a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 %a_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0
store i32 %a, i32* %a_dst_ptr store i32 %a, i32 addrspace(5)* %a_dst_ptr
%b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 1 %b_dst_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 1
store i32 %b, i32* %b_dst_ptr store i32 %b, i32 addrspace(5)* %b_dst_ptr
br label %for.body br label %for.body
for.body: for.body:
%inc = phi i32 [0, %entry], [%count, %for.body] %inc = phi i32 [0, %entry], [%count, %for.body]
%x_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array_const, i32 0, i32 0 %x_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array_const, i32 0, i32 0
%x = load i32, i32* %x_ptr %x = load i32, i32 addrspace(5)* %x_ptr
%y_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 %y_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0
%y = load i32, i32* %y_ptr %y = load i32, i32 addrspace(5)* %y_ptr
%xy = add i32 %x, %y %xy = add i32 %x, %y
store i32 %xy, i32* %y_ptr store i32 %xy, i32 addrspace(5)* %y_ptr
%count = add i32 %inc, 1 %count = add i32 %inc, 1
%done = icmp eq i32 %count, 4095 %done = icmp eq i32 %count, 4095
br i1 %done, label %for.end, label %for.body br i1 %done, label %for.end, label %for.body
for.end: for.end:
%value_ptr = getelementptr inbounds [2 x i32], [2 x i32]* %prv_array, i32 0, i32 0 %value_ptr = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %prv_array, i32 0, i32 0
%value = load i32, i32* %value_ptr %value = load i32, i32 addrspace(5)* %value_ptr
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}short_array: ; FUNC-LABEL: {{^}}short_array:
; R600: MOVA_INT ; R600: MOVA_INT
; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:6 ; encoding: [0x06,0x00,0x68,0xe0 ; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:6 ; encoding: [0x06,0x00,0x68,0xe0
; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding: [0x04,0x00,0x68,0xe0 ; SI-ALLOCA-DAG: buffer_store_short v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding: [0x04,0x00,0x68,0xe0
; Loaded value is 0 or 1, so sext will become zext, so we get buffer_load_ushort instead of buffer_load_sshort. ; Loaded value is 0 or 1, so sext will become zext, so we get buffer_load_ushort instead of buffer_load_sshort.
; SI-ALLOCA: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} ; SI-ALLOCA: buffer_load_sshort v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}}
; SI-PROMOTE: s_load_dword [[IDX:s[0-9]+]] ; SI-PROMOTE: s_load_dword [[IDX:s[0-9]+]]
; SI-PROMOTE: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 16 ; SI-PROMOTE: s_lshl_b32 [[SCALED_IDX:s[0-9]+]], [[IDX]], 16
; SI-PROMOTE: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[SCALED_IDX]], 16 ; SI-PROMOTE: v_bfe_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[SCALED_IDX]], 16
define amdgpu_kernel void @short_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @short_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%0 = alloca [2 x i16] %0 = alloca [2 x i16], addrspace(5)
%1 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 0 %1 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 0
%2 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 1 %2 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 1
store i16 0, i16* %1 store i16 0, i16 addrspace(5)* %1
store i16 1, i16* %2 store i16 1, i16 addrspace(5)* %2
%3 = getelementptr inbounds [2 x i16], [2 x i16]* %0, i32 0, i32 %index %3 = getelementptr inbounds [2 x i16], [2 x i16] addrspace(5)* %0, i32 0, i32 %index
%4 = load i16, i16* %3 %4 = load i16, i16 addrspace(5)* %3
%5 = sext i16 %4 to i32 %5 = sext i16 %4 to i32
store i32 %5, i32 addrspace(1)* %out store i32 %5, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}char_array: ; FUNC-LABEL: {{^}}char_array:
; R600: MOVA_INT ; R600: MOVA_INT
; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding: ; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding:
; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding: ; SI-PROMOTE-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding:
; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding: [0x04,0x00,0x60,0xe0 ; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; encoding: [0x04,0x00,0x60,0xe0
; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding: [0x05,0x00,0x60,0xe0 ; SI-ALLOCA-DAG: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:5 ; encoding: [0x05,0x00,0x60,0xe0
define amdgpu_kernel void @char_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @char_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%0 = alloca [2 x i8] %0 = alloca [2 x i8], addrspace(5)
%1 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 0 %1 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 0
%2 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 1 %2 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 1
store i8 0, i8* %1 store i8 0, i8 addrspace(5)* %1
store i8 1, i8* %2 store i8 1, i8 addrspace(5)* %2
%3 = getelementptr inbounds [2 x i8], [2 x i8]* %0, i32 0, i32 %index %3 = getelementptr inbounds [2 x i8], [2 x i8] addrspace(5)* %0, i32 0, i32 %index
%4 = load i8, i8* %3 %4 = load i8, i8 addrspace(5)* %3
%5 = sext i8 %4 to i32 %5 = sext i8 %4 to i32
store i32 %5, i32 addrspace(1)* %out store i32 %5, i32 addrspace(1)* %out
ret void ret void
} }
; Test that two stack objects are not stored in the same register ; Test that two stack objects are not stored in the same register
; The second stack object should be in T3.X ; The second stack object should be in T3.X
; FUNC-LABEL: {{^}}no_overlap: ; FUNC-LABEL: {{^}}no_overlap:
; R600-CHECK: MOV ; R600-CHECK: MOV
; R600-CHECK: [[CHAN:[XYZW]]]+ ; R600-CHECK: [[CHAN:[XYZW]]]+
; R600-NOT: [[CHAN]]+ ; R600-NOT: [[CHAN]]+
; ;
; A total of 5 bytes should be allocated and used. ; A total of 5 bytes should be allocated and used.
; SI: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ; ; SI: buffer_store_byte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4 ;
define amdgpu_kernel void @no_overlap(i32 addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @no_overlap(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%0 = alloca [3 x i8], align 1 %0 = alloca [3 x i8], align 1, addrspace(5)
%1 = alloca [2 x i8], align 1 %1 = alloca [2 x i8], align 1, addrspace(5)
%2 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 0 %2 = getelementptr [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 0
%3 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 1 %3 = getelementptr [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 1
%4 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 2 %4 = getelementptr [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 2
%5 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 0 %5 = getelementptr [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 0
%6 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 1 %6 = getelementptr [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 1
store i8 0, i8* %2 store i8 0, i8 addrspace(5)* %2
store i8 1, i8* %3 store i8 1, i8 addrspace(5)* %3
store i8 2, i8* %4 store i8 2, i8 addrspace(5)* %4
store i8 1, i8* %5 store i8 1, i8 addrspace(5)* %5
store i8 0, i8* %6 store i8 0, i8 addrspace(5)* %6
%7 = getelementptr [3 x i8], [3 x i8]* %0, i32 0, i32 %in %7 = getelementptr [3 x i8], [3 x i8] addrspace(5)* %0, i32 0, i32 %in
%8 = getelementptr [2 x i8], [2 x i8]* %1, i32 0, i32 %in %8 = getelementptr [2 x i8], [2 x i8] addrspace(5)* %1, i32 0, i32 %in
%9 = load i8, i8* %7 %9 = load i8, i8 addrspace(5)* %7
%10 = load i8, i8* %8 %10 = load i8, i8 addrspace(5)* %8
%11 = add i8 %9, %10 %11 = add i8 %9, %10
%12 = sext i8 %11 to i32 %12 = sext i8 %11 to i32
store i32 %12, i32 addrspace(1)* %out store i32 %12, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @char_array_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @char_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x [2 x i8]] %alloca = alloca [2 x [2 x i8]], addrspace(5)
%gep0 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 0 %gep0 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
%gep1 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 1 %gep1 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
store i8 0, i8* %gep0 store i8 0, i8 addrspace(5)* %gep0
store i8 1, i8* %gep1 store i8 1, i8 addrspace(5)* %gep1
%gep2 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]]* %alloca, i32 0, i32 0, i32 %index %gep2 = getelementptr [2 x [2 x i8]], [2 x [2 x i8]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
%load = load i8, i8* %gep2 %load = load i8, i8 addrspace(5)* %gep2
%sext = sext i8 %load to i32 %sext = sext i8 %load to i32
store i32 %sext, i32 addrspace(1)* %out store i32 %sext, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x [2 x i32]] %alloca = alloca [2 x [2 x i32]], addrspace(5)
%gep0 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 %gep0 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
%gep1 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 %gep1 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
store i32 0, i32* %gep0 store i32 0, i32 addrspace(5)* %gep0
store i32 1, i32* %gep1 store i32 1, i32 addrspace(5)* %gep1
%gep2 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index %gep2 = getelementptr [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
%load = load i32, i32* %gep2 %load = load i32, i32 addrspace(5)* %gep2
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @i64_array_array(i64 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @i64_array_array(i64 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x [2 x i64]] %alloca = alloca [2 x [2 x i64]], addrspace(5)
%gep0 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 0 %gep0 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
%gep1 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 1 %gep1 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
store i64 0, i64* %gep0 store i64 0, i64 addrspace(5)* %gep0
store i64 1, i64* %gep1 store i64 1, i64 addrspace(5)* %gep1
%gep2 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]]* %alloca, i32 0, i32 0, i32 %index %gep2 = getelementptr [2 x [2 x i64]], [2 x [2 x i64]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
%load = load i64, i64* %gep2 %load = load i64, i64 addrspace(5)* %gep2
store i64 %load, i64 addrspace(1)* %out store i64 %load, i64 addrspace(1)* %out
ret void ret void
} }
%struct.pair32 = type { i32, i32 } %struct.pair32 = type { i32, i32 }
define amdgpu_kernel void @struct_array_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @struct_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x [2 x %struct.pair32]] %alloca = alloca [2 x [2 x %struct.pair32]], addrspace(5)
%gep0 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 0, i32 1 %gep0 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0, i32 1
%gep1 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 1, i32 1 %gep1 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1, i32 1
store i32 0, i32* %gep0 store i32 0, i32 addrspace(5)* %gep0
store i32 1, i32* %gep1 store i32 1, i32 addrspace(5)* %gep1
%gep2 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]]* %alloca, i32 0, i32 0, i32 %index, i32 0 %gep2 = getelementptr [2 x [2 x %struct.pair32]], [2 x [2 x %struct.pair32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index, i32 0
%load = load i32, i32* %gep2 %load = load i32, i32 addrspace(5)* %gep2
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @struct_pair32_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x %struct.pair32] %alloca = alloca [2 x %struct.pair32], addrspace(5)
%gep0 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 0, i32 1 %gep0 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 0, i32 1
%gep1 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 1, i32 0 %gep1 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 1, i32 0
store i32 0, i32* %gep0 store i32 0, i32 addrspace(5)* %gep0
store i32 1, i32* %gep1 store i32 1, i32 addrspace(5)* %gep1
%gep2 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32]* %alloca, i32 0, i32 %index, i32 0 %gep2 = getelementptr [2 x %struct.pair32], [2 x %struct.pair32] addrspace(5)* %alloca, i32 0, i32 %index, i32 0
%load = load i32, i32* %gep2 %load = load i32, i32 addrspace(5)* %gep2
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind { define amdgpu_kernel void @select_private(i32 addrspace(1)* %out, i32 %in) nounwind {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%cmp = icmp eq i32 %in, 0 %cmp = icmp eq i32 %in, 0
%sel = select i1 %cmp, i32* %tmp1, i32* %tmp2 %sel = select i1 %cmp, i32 addrspace(5)* %tmp1, i32 addrspace(5)* %tmp2
%load = load i32, i32* %sel %load = load i32, i32 addrspace(5)* %sel
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it ; AMDGPUPromoteAlloca does not know how to handle ptrtoint. When it
; finds one, it should stop trying to promote. ; finds one, it should stop trying to promote.
; FUNC-LABEL: ptrtoint: ; FUNC-LABEL: ptrtoint:
; SI-NOT: ds_write ; SI-NOT: ds_write
; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; SI: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen
; SI: v_add_{{[iu]}}32_e32 [[ADD_OFFSET:v[0-9]+]], vcc, 5, ; SI: v_add_{{[iu]}}32_e32 [[ADD_OFFSET:v[0-9]+]], vcc, 5,
; SI: buffer_load_dword v{{[0-9]+}}, [[ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ; ; SI: buffer_load_dword v{{[0-9]+}}, [[ADD_OFFSET:v[0-9]+]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen ;
define amdgpu_kernel void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 { define amdgpu_kernel void @ptrtoint(i32 addrspace(1)* %out, i32 %a, i32 %b) #0 {
%alloca = alloca [16 x i32] %alloca = alloca [16 x i32], addrspace(5)
%tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %a %tmp0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %a
store i32 5, i32* %tmp0 store i32 5, i32 addrspace(5)* %tmp0
%tmp1 = ptrtoint [16 x i32]* %alloca to i32 %tmp1 = ptrtoint [16 x i32] addrspace(5)* %alloca to i32
%tmp2 = add i32 %tmp1, 5 %tmp2 = add i32 %tmp1, 5
%tmp3 = inttoptr i32 %tmp2 to i32* %tmp3 = inttoptr i32 %tmp2 to i32 addrspace(5)*
%tmp4 = getelementptr i32, i32* %tmp3, i32 %b %tmp4 = getelementptr i32, i32 addrspace(5)* %tmp3, i32 %b
%tmp5 = load i32, i32* %tmp4 %tmp5 = load i32, i32 addrspace(5)* %tmp4
store i32 %tmp5, i32 addrspace(1)* %out store i32 %tmp5, i32 addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @pointer_typed_alloca( ; OPT-LABEL: @pointer_typed_alloca(
; OPT: getelementptr inbounds [256 x i32 addrspace(1)*], [256 x i32 addrspace(1)*] addrspace(3)* @pointer_typed_alloca.A.addr, i32 0, i32 %{{[0-9]+}} ; OPT: getelementptr inbounds [256 x i32 addrspace(1)*], [256 x i32 addrspace(1)*] addrspace(3)* @pointer_typed_alloca.A.addr, i32 0, i32 %{{[0-9]+}}
; OPT: load i32 addrspace(1)*, i32 addrspace(1)* addrspace(3)* %{{[0-9]+}}, align 4 ; OPT: load i32 addrspace(1)*, i32 addrspace(1)* addrspace(3)* %{{[0-9]+}}, align 4
define amdgpu_kernel void @pointer_typed_alloca(i32 addrspace(1)* %A) { define amdgpu_kernel void @pointer_typed_alloca(i32 addrspace(1)* %A) {
entry: entry:
%A.addr = alloca i32 addrspace(1)*, align 4 %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
%ld0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4 %ld0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %ld0, i32 0 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %ld0, i32 0
store i32 1, i32 addrspace(1)* %arrayidx, align 4 store i32 1, i32 addrspace(1)* %arrayidx, align 4
%ld1 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4 %ld1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %ld1, i32 1 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %ld1, i32 1
store i32 2, i32 addrspace(1)* %arrayidx1, align 4 store i32 2, i32 addrspace(1)* %arrayidx1, align 4
%ld2 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4 %ld2 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %ld2, i32 2 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %ld2, i32 2
store i32 3, i32 addrspace(1)* %arrayidx2, align 4 store i32 3, i32 addrspace(1)* %arrayidx2, align 4
ret void ret void
} }
; FUNC-LABEL: v16i32_stack: ; FUNC-LABEL: v16i32_stack:
; R600: MOVA_INT ; R600: MOVA_INT
Show All 26 Lines
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
define amdgpu_kernel void @v16i32_stack(<16 x i32> addrspace(1)* %out, i32 %a) { define amdgpu_kernel void @v16i32_stack(<16 x i32> addrspace(1)* %out, i32 %a) {
%alloca = alloca [2 x <16 x i32>] %alloca = alloca [2 x <16 x i32>], addrspace(5)
%tmp0 = getelementptr [2 x <16 x i32>], [2 x <16 x i32>]* %alloca, i32 0, i32 %a %tmp0 = getelementptr [2 x <16 x i32>], [2 x <16 x i32>] addrspace(5)* %alloca, i32 0, i32 %a
%tmp5 = load <16 x i32>, <16 x i32>* %tmp0 %tmp5 = load <16 x i32>, <16 x i32> addrspace(5)* %tmp0
store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out store <16 x i32> %tmp5, <16 x i32> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: v16float_stack: ; FUNC-LABEL: v16float_stack:
; R600: MOVA_INT ; R600: MOVA_INT
; R600: MOVA_INT ; R600: MOVA_INT
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; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
define amdgpu_kernel void @v16float_stack(<16 x float> addrspace(1)* %out, i32 %a) { define amdgpu_kernel void @v16float_stack(<16 x float> addrspace(1)* %out, i32 %a) {
%alloca = alloca [2 x <16 x float>] %alloca = alloca [2 x <16 x float>], addrspace(5)
%tmp0 = getelementptr [2 x <16 x float>], [2 x <16 x float>]* %alloca, i32 0, i32 %a %tmp0 = getelementptr [2 x <16 x float>], [2 x <16 x float>] addrspace(5)* %alloca, i32 0, i32 %a
%tmp5 = load <16 x float>, <16 x float>* %tmp0 %tmp5 = load <16 x float>, <16 x float> addrspace(5)* %tmp0
store <16 x float> %tmp5, <16 x float> addrspace(1)* %out store <16 x float> %tmp5, <16 x float> addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: v2float_stack: ; FUNC-LABEL: v2float_stack:
; R600: MOVA_INT ; R600: MOVA_INT
; R600: MOVA_INT ; R600: MOVA_INT
; SI: buffer_load_dword ; SI: buffer_load_dword
; SI: buffer_load_dword ; SI: buffer_load_dword
define amdgpu_kernel void @v2float_stack(<2 x float> addrspace(1)* %out, i32 %a) { define amdgpu_kernel void @v2float_stack(<2 x float> addrspace(1)* %out, i32 %a) {
%alloca = alloca [16 x <2 x float>] %alloca = alloca [16 x <2 x float>], addrspace(5)
%tmp0 = getelementptr [16 x <2 x float>], [16 x <2 x float>]* %alloca, i32 0, i32 %a %tmp0 = getelementptr [16 x <2 x float>], [16 x <2 x float>] addrspace(5)* %alloca, i32 0, i32 %a
%tmp5 = load <2 x float>, <2 x float>* %tmp0 %tmp5 = load <2 x float>, <2 x float> addrspace(5)* %tmp0
store <2 x float> %tmp5, <2 x float> addrspace(1)* %out store <2 x float> %tmp5, <2 x float> addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @direct_alloca_read_0xi32( ; OPT-LABEL: @direct_alloca_read_0xi32(
; OPT: store [0 x i32] undef, [0 x i32] addrspace(3)* ; OPT: store [0 x i32] undef, [0 x i32] addrspace(3)*
; OPT: load [0 x i32], [0 x i32] addrspace(3)* ; OPT: load [0 x i32], [0 x i32] addrspace(3)*
define amdgpu_kernel void @direct_alloca_read_0xi32([0 x i32] addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @direct_alloca_read_0xi32([0 x i32] addrspace(1)* %out, i32 %index) {
entry: entry:
%tmp = alloca [0 x i32] %tmp = alloca [0 x i32], addrspace(5)
store [0 x i32] [], [0 x i32]* %tmp store [0 x i32] [], [0 x i32] addrspace(5)* %tmp
%load = load [0 x i32], [0 x i32]* %tmp %load = load [0 x i32], [0 x i32] addrspace(5)* %tmp
store [0 x i32] %load, [0 x i32] addrspace(1)* %out store [0 x i32] %load, [0 x i32] addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @direct_alloca_read_1xi32( ; OPT-LABEL: @direct_alloca_read_1xi32(
; OPT: store [1 x i32] zeroinitializer, [1 x i32] addrspace(3)* ; OPT: store [1 x i32] zeroinitializer, [1 x i32] addrspace(3)*
; OPT: load [1 x i32], [1 x i32] addrspace(3)* ; OPT: load [1 x i32], [1 x i32] addrspace(3)*
define amdgpu_kernel void @direct_alloca_read_1xi32([1 x i32] addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @direct_alloca_read_1xi32([1 x i32] addrspace(1)* %out, i32 %index) {
entry: entry:
%tmp = alloca [1 x i32] %tmp = alloca [1 x i32], addrspace(5)
store [1 x i32] [i32 0], [1 x i32]* %tmp store [1 x i32] [i32 0], [1 x i32] addrspace(5)* %tmp
%load = load [1 x i32], [1 x i32]* %tmp %load = load [1 x i32], [1 x i32] addrspace(5)* %tmp
store [1 x i32] %load, [1 x i32] addrspace(1)* %out store [1 x i32] %load, [1 x i32] addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,2" } attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,2" }
; HSAOPT: !0 = !{} ; HSAOPT: !0 = !{}
; HSAOPT: !1 = !{i32 0, i32 257} ; HSAOPT: !1 = !{i32 0, i32 257}
; HSAOPT: !2 = !{i32 0, i32 256} ; HSAOPT: !2 = !{i32 0, i32 256}
; NOHSAOPT: !0 = !{i32 0, i32 257} ; NOHSAOPT: !0 = !{i32 0, i32 257}
; NOHSAOPT: !1 = !{i32 0, i32 256} ; NOHSAOPT: !1 = !{i32 0, i32 256}

test/CodeGen/AMDGPU/amdpal.ll

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; where the high half of the address comes from s_getpc. ; where the high half of the address comes from s_getpc.
; PAL-LABEL: {{^}}scratch: ; PAL-LABEL: {{^}}scratch:
; PAL: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]: ; PAL: s_getpc_b64 s{{\[}}[[GITPTR:[0-9]+]]:
; PAL: s_mov_b32 s[[GITPTR]], s0 ; PAL: s_mov_b32 s[[GITPTR]], s0
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]: ; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: ; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32* %out) { define amdgpu_kernel void @scratch(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) {
entry: entry:
%v = alloca [2 x i32] %v = alloca [2 x i32], addrspace(5)
%vv = bitcast [2 x i32]* %v to <2 x i32>* %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
store <2 x i32> %in, <2 x i32>* %vv store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
%e = getelementptr [2 x i32], [2 x i32]* %v, i32 0, i32 %idx %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
%x = load i32, i32* %e %x = load i32, i32 addrspace(5)* %e
store i32 %x, i32* %out store i32 %x, i32 addrspace(5)* %out
ret void ret void
} }
; Check code sequence for amdpal use of scratch for alloca. This is the case ; Check code sequence for amdpal use of scratch for alloca. This is the case
; where the amdgpu-git-ptr-high function attribute gives the high half of the ; where the amdgpu-git-ptr-high function attribute gives the high half of the
; address to use. ; address to use.
; Looks like you can't do arithmetic on a filecheck variable, so we can't test ; Looks like you can't do arithmetic on a filecheck variable, so we can't test
; that the s_movk_i32 is into a reg that is one more than the following ; that the s_movk_i32 is into a reg that is one more than the following
; s_mov_b32. ; s_mov_b32.
; PAL-LABEL: {{^}}scratch2: ; PAL-LABEL: {{^}}scratch2:
; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234 ; PAL: s_movk_i32 s{{[0-9]+}}, 0x1234
; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0 ; PAL: s_mov_b32 s[[GITPTR:[0-9]+]], s0
; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]: ; PAL: s_load_dwordx4 s{{\[}}[[SCRATCHDESC:[0-9]+]]:{{[0-9]+]}}, s{{\[}}[[GITPTR]]:
; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]: ; PAL: buffer_store{{.*}}, s{{\[}}[[SCRATCHDESC]]:
define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32* %out) #0 { define amdgpu_kernel void @scratch2(<2 x i32> %in, i32 %idx, i32 addrspace(5)* %out) #0 {
entry: entry:
%v = alloca [2 x i32] %v = alloca [2 x i32], addrspace(5)
%vv = bitcast [2 x i32]* %v to <2 x i32>* %vv = bitcast [2 x i32] addrspace(5)* %v to <2 x i32> addrspace(5)*
store <2 x i32> %in, <2 x i32>* %vv store <2 x i32> %in, <2 x i32> addrspace(5)* %vv
%e = getelementptr [2 x i32], [2 x i32]* %v, i32 0, i32 %idx %e = getelementptr [2 x i32], [2 x i32] addrspace(5)* %v, i32 0, i32 %idx
%x = load i32, i32* %e %x = load i32, i32 addrspace(5)* %e
store i32 %x, i32* %out store i32 %x, i32 addrspace(5)* %out
ret void ret void
} }
attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" } attributes #0 = { nounwind "amdgpu-git-ptr-high"="0x1234" }
; Check we have CS_NUM_USED_VGPRS in PAL metadata. ; Check we have CS_NUM_USED_VGPRS in PAL metadata.
; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027, ; PAL: .amd_amdgpu_pal_metadata {{.*}},0x10000027,

test/CodeGen/AMDGPU/annotate-kernel-features-hsa.ll

Show First 20 Lines • Show All 170 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @use_kernarg_segment_ptr(i32 addrspace(1)* %ptr) #1 {
%bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)* %bc = bitcast i8 addrspace(2)* %dispatch.ptr to i32 addrspace(2)*
%val = load i32, i32 addrspace(2)* %bc %val = load i32, i32 addrspace(2)* %bc
store i32 %val, i32 addrspace(1)* %ptr store i32 %val, i32 addrspace(1)* %ptr
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #11 { ; HSA: define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #11 {
define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 { define amdgpu_kernel void @use_group_to_flat_addrspacecast(i32 addrspace(3)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32* %ptr) #11 { ; HSA: define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #11 {
define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32* %ptr) #1 { define amdgpu_kernel void @use_private_to_flat_addrspacecast(i32 addrspace(5)* %ptr) #1 {
%stof = addrspacecast i32* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(5)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_group_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(3)* %ftos = addrspacecast i32* %ptr to i32 addrspace(3)*
store volatile i32 0, i32 addrspace(3)* %ftos store volatile i32 0, i32 addrspace(3)* %ftos
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_private_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32* %ftos = addrspacecast i32* %ptr to i32 addrspace(5)*
store volatile i32 0, i32* %ftos store volatile i32 0, i32 addrspace(5)* %ftos
ret void ret void
} }
; No-op addrspacecast should not use queue ptr ; No-op addrspacecast should not use queue ptr
; HSA: define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 {
define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 { define amdgpu_kernel void @use_global_to_flat_addrspacecast(i32 addrspace(1)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(1)* %ptr to i32*
store volatile i32 0, i32 addrspace(4)* %stof store volatile i32 0, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 {
define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 { define amdgpu_kernel void @use_constant_to_flat_addrspacecast(i32 addrspace(2)* %ptr) #1 {
%stof = addrspacecast i32 addrspace(2)* %ptr to i32 addrspace(4)* %stof = addrspacecast i32 addrspace(2)* %ptr to i32*
%ld = load volatile i32, i32 addrspace(4)* %stof %ld = load volatile i32, i32* %stof
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_global_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(1)* %ftos = addrspacecast i32* %ptr to i32 addrspace(1)*
store volatile i32 0, i32 addrspace(1)* %ftos store volatile i32 0, i32 addrspace(1)* %ftos
ret void ret void
} }
; HSA: define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #1 { ; HSA: define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 {
define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32 addrspace(4)* %ptr) #1 { define amdgpu_kernel void @use_flat_to_constant_addrspacecast(i32* %ptr) #1 {
%ftos = addrspacecast i32 addrspace(4)* %ptr to i32 addrspace(2)* %ftos = addrspacecast i32* %ptr to i32 addrspace(2)*
%ld = load volatile i32, i32 addrspace(2)* %ftos %ld = load volatile i32, i32 addrspace(2)* %ftos
ret void ret void
} }
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind } attributes #1 = { nounwind }
; HSA: attributes #0 = { nounwind readnone speculatable } ; HSA: attributes #0 = { nounwind readnone speculatable }
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test/CodeGen/AMDGPU/array-ptr-calc-i32.ll

Show All 14 Lines
; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 16, v{{[0-9]+}} ; SI-ALLOCA: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 16, v{{[0-9]+}}
; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64 ; SI-ALLOCA: buffer_store_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64
; SI-ALLOCA: s_barrier ; SI-ALLOCA: s_barrier
; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64 ; SI-ALLOCA: buffer_load_dword {{v[0-9]+}}, [[PTRREG]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen offset:64
; ;
; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this ; FIXME: The AMDGPUPromoteAlloca pass should be able to convert this
; alloca to a vector. It currently fails because it does not know how ; alloca to a vector. It currently fails because it does not know how
; to interpret: ; to interpret:
; getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b ; getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 1, i32 %b
; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64 ; SI-PROMOTE: v_add_i32_e32 [[PTRREG:v[0-9]+]], vcc, 64
; SI-PROMOTE: ds_write_b32 [[PTRREG]] ; SI-PROMOTE: ds_write_b32 [[PTRREG]]
define amdgpu_kernel void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 { define amdgpu_kernel void @test_private_array_ptr_calc(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %inA, i32 addrspace(1)* noalias %inB) #0 {
%alloca = alloca [16 x i32], align 16 %alloca = alloca [16 x i32], align 16, addrspace(5)
%mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0); %mbcnt.lo = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0);
%tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo) %tid = call i32 @llvm.amdgcn.mbcnt.hi(i32 -1, i32 %mbcnt.lo)
%a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid %a_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inA, i32 %tid
%b_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inB, i32 %tid %b_ptr = getelementptr inbounds i32, i32 addrspace(1)* %inB, i32 %tid
%a = load i32, i32 addrspace(1)* %a_ptr, !range !0 %a = load i32, i32 addrspace(1)* %a_ptr, !range !0
%b = load i32, i32 addrspace(1)* %b_ptr, !range !0 %b = load i32, i32 addrspace(1)* %b_ptr, !range !0
%result = add i32 %a, %b %result = add i32 %a, %b
%alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 1, i32 %b %alloca_ptr = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 1, i32 %b
store i32 %result, i32* %alloca_ptr, align 4 store i32 %result, i32 addrspace(5)* %alloca_ptr, align 4
; Dummy call ; Dummy call
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%reload = load i32, i32* %alloca_ptr, align 4, !range !0 %reload = load i32, i32 addrspace(5)* %alloca_ptr, align 4, !range !0
%out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid %out_ptr = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
store i32 %reload, i32 addrspace(1)* %out_ptr, align 4 store i32 %reload, i32 addrspace(1)* %out_ptr, align 4
ret void ret void
} }
attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" } attributes #0 = { nounwind "amdgpu-waves-per-eu"="1,1" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind convergent } attributes #2 = { nounwind convergent }
!0 = !{i32 0, i32 65536 } !0 = !{i32 0, i32 65536 }

test/CodeGen/AMDGPU/byval-frame-setup.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -enable-ipra=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI %s
%struct.ByValStruct = type { [4 x i32] } %struct.ByValStruct = type { [4 x i32] }
; GCN-LABEL: {{^}}void_func_byval_struct: ; GCN-LABEL: {{^}}void_func_byval_struct:
; GCN: s_mov_b32 s5, s32 ; GCN: s_mov_b32 s5, s32
; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s5 offset:4{{$}} ; GCN: buffer_load_dword [[LOAD0:v[0-9]+]], off, s[0:3], s5 offset:4{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s5 offset:4{{$}} ; GCN: buffer_store_dword [[LOAD0]], off, s[0:3], s5 offset:4{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s5 offset:20{{$}} ; GCN: buffer_load_dword [[LOAD1:v[0-9]+]], off, s[0:3], s5 offset:20{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s5 offset:20{{$}} ; GCN: buffer_store_dword [[LOAD1]], off, s[0:3], s5 offset:20{{$}}
; GCN-NOT: s32 ; GCN-NOT: s32
define void @void_func_byval_struct(%struct.ByValStruct* byval noalias nocapture align 4 %arg0, %struct.ByValStruct* byval noalias nocapture align 4 %arg1) #1 { define void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1) #1 {
entry: entry:
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
%tmp = load volatile i32, i32* %arrayidx, align 4 %tmp = load volatile i32, i32 addrspace(5)* %arrayidx, align 4
%add = add nsw i32 %tmp, 1 %add = add nsw i32 %tmp, 1
store volatile i32 %add, i32* %arrayidx, align 4 store volatile i32 %add, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
%tmp1 = load volatile i32, i32* %arrayidx2, align 4 %tmp1 = load volatile i32, i32 addrspace(5)* %arrayidx2, align 4
%add3 = add nsw i32 %tmp1, 2 %add3 = add nsw i32 %tmp1, 2
store volatile i32 %add3, i32* %arrayidx2, align 4 store volatile i32 %add3, i32 addrspace(5)* %arrayidx2, align 4
store volatile i32 9, i32 addrspace(1)* null, align 4 store volatile i32 9, i32 addrspace(1)* null, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_struct_non_leaf: ; GCN-LABEL: {{^}}void_func_byval_struct_non_leaf:
; GCN: s_mov_b32 s5, s32 ; GCN: s_mov_b32 s5, s32
; GCN-DAG: buffer_store_dword v32 ; GCN-DAG: buffer_store_dword v32
; GCN-DAG: buffer_store_dword v33 ; GCN-DAG: buffer_store_dword v33
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; GCN: buffer_store_dword [[ADD1]], off, s[0:3], s5 offset:20{{$}} ; GCN: buffer_store_dword [[ADD1]], off, s[0:3], s5 offset:20{{$}}
; GCN: v_readlane_b32 ; GCN: v_readlane_b32
; GCN-NOT: v_readlane_b32 s32 ; GCN-NOT: v_readlane_b32 s32
; GCN: buffer_load_dword v32, ; GCN: buffer_load_dword v32,
; GCN: buffer_load_dword v33, ; GCN: buffer_load_dword v33,
; GCN: s_sub_u32 s32, s32, 0xb00{{$}} ; GCN: s_sub_u32 s32, s32, 0xb00{{$}}
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @void_func_byval_struct_non_leaf(%struct.ByValStruct* byval noalias nocapture align 4 %arg0, %struct.ByValStruct* byval noalias nocapture align 4 %arg1) #1 { define void @void_func_byval_struct_non_leaf(%struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg0, %struct.ByValStruct addrspace(5)* byval noalias nocapture align 4 %arg1) #1 {
entry: entry:
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
%tmp = load volatile i32, i32* %arrayidx, align 4 %tmp = load volatile i32, i32 addrspace(5)* %arrayidx, align 4
%add = add nsw i32 %tmp, 1 %add = add nsw i32 %tmp, 1
store volatile i32 %add, i32* %arrayidx, align 4 store volatile i32 %add, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
%tmp1 = load volatile i32, i32* %arrayidx2, align 4 %tmp1 = load volatile i32, i32 addrspace(5)* %arrayidx2, align 4
%add3 = add nsw i32 %tmp1, 2 %add3 = add nsw i32 %tmp1, 2
call void @external_void_func_void() call void @external_void_func_void()
store volatile i32 %add3, i32* %arrayidx2, align 4 store volatile i32 %add3, i32 addrspace(5)* %arrayidx2, align 4
store volatile i32 9, i32 addrspace(1)* null, align 4 store volatile i32 9, i32 addrspace(1)* null, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}call_void_func_byval_struct_func: ; GCN-LABEL: {{^}}call_void_func_byval_struct_func:
; GCN: s_mov_b32 s5, s32 ; GCN: s_mov_b32 s5, s32
; GCN-DAG: s_add_u32 s32, s32, 0xc00{{$}} ; GCN-DAG: s_add_u32 s32, s32, 0xc00{{$}}
; GCN-DAG: v_writelane_b32 ; GCN-DAG: v_writelane_b32
Show All 33 Lines
; GCN-NOT: s_sub_u32 s32, s32, 0x800 ; GCN-NOT: s_sub_u32 s32, s32, 0x800
; GCN: s_sub_u32 s32, s32, 0xc00{{$}} ; GCN: s_sub_u32 s32, s32, 0xc00{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @call_void_func_byval_struct_func() #0 { define void @call_void_func_byval_struct_func() #0 {
entry: entry:
%arg0 = alloca %struct.ByValStruct, align 4 %arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
%arg1 = alloca %struct.ByValStruct, align 4 %arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
%tmp = bitcast %struct.ByValStruct* %arg0 to i8* %tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp)
%tmp1 = bitcast %struct.ByValStruct* %arg1 to i8* %tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp1)
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
store volatile i32 9, i32* %arrayidx, align 4 store volatile i32 9, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
store volatile i32 13, i32* %arrayidx2, align 4 store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 4
call void @void_func_byval_struct(%struct.ByValStruct* byval nonnull align 4 %arg0, %struct.ByValStruct* byval nonnull align 4 %arg1) call void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp)
ret void ret void
} }
; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel: ; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel:
; GCN: s_mov_b32 s33, s7 ; GCN: s_mov_b32 s33, s7
; GCN: s_add_u32 s32, s33, 0xa00{{$}} ; GCN: s_add_u32 s32, s33, 0xa00{{$}}
; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9 ; GCN-DAG: v_mov_b32_e32 [[NINE:v[0-9]+]], 9
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; GCN-DAG: buffer_store_dword [[LOAD7]], off, s[0:3], s32 offset:32 ; GCN-DAG: buffer_store_dword [[LOAD7]], off, s[0:3], s32 offset:32
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN-NOT: s_sub_u32 s32 ; GCN-NOT: s_sub_u32 s32
; GCN: s_endpgm ; GCN: s_endpgm
define amdgpu_kernel void @call_void_func_byval_struct_kernel() #0 { define amdgpu_kernel void @call_void_func_byval_struct_kernel() #0 {
entry: entry:
%arg0 = alloca %struct.ByValStruct, align 4 %arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
%arg1 = alloca %struct.ByValStruct, align 4 %arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
%tmp = bitcast %struct.ByValStruct* %arg0 to i8* %tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp)
%tmp1 = bitcast %struct.ByValStruct* %arg1 to i8* %tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp1)
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
store volatile i32 9, i32* %arrayidx, align 4 store volatile i32 9, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
store volatile i32 13, i32* %arrayidx2, align 4 store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 4
call void @void_func_byval_struct(%struct.ByValStruct* byval nonnull align 4 %arg0, %struct.ByValStruct* byval nonnull align 4 %arg1) call void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp)
ret void ret void
} }
; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel_no_frame_pointer_elim: ; GCN-LABEL: {{^}}call_void_func_byval_struct_kernel_no_frame_pointer_elim:
define amdgpu_kernel void @call_void_func_byval_struct_kernel_no_frame_pointer_elim() #2 { define amdgpu_kernel void @call_void_func_byval_struct_kernel_no_frame_pointer_elim() #2 {
entry: entry:
%arg0 = alloca %struct.ByValStruct, align 4 %arg0 = alloca %struct.ByValStruct, align 4, addrspace(5)
%arg1 = alloca %struct.ByValStruct, align 4 %arg1 = alloca %struct.ByValStruct, align 4, addrspace(5)
%tmp = bitcast %struct.ByValStruct* %arg0 to i8* %tmp = bitcast %struct.ByValStruct addrspace(5)* %arg0 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp)
%tmp1 = bitcast %struct.ByValStruct* %arg1 to i8* %tmp1 = bitcast %struct.ByValStruct addrspace(5)* %arg1 to i8 addrspace(5)*
call void @llvm.lifetime.start.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.start.p5i8(i64 32, i8 addrspace(5)* %tmp1)
%arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg0, i32 0, i32 0, i32 0 %arrayidx = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg0, i32 0, i32 0, i32 0
store volatile i32 9, i32* %arrayidx, align 4 store volatile i32 9, i32 addrspace(5)* %arrayidx, align 4
%arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct* %arg1, i32 0, i32 0, i32 0 %arrayidx2 = getelementptr inbounds %struct.ByValStruct, %struct.ByValStruct addrspace(5)* %arg1, i32 0, i32 0, i32 0
store volatile i32 13, i32* %arrayidx2, align 4 store volatile i32 13, i32 addrspace(5)* %arrayidx2, align 4
call void @void_func_byval_struct(%struct.ByValStruct* byval nonnull align 4 %arg0, %struct.ByValStruct* byval nonnull align 4 %arg1) call void @void_func_byval_struct(%struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg0, %struct.ByValStruct addrspace(5)* byval nonnull align 4 %arg1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp1) call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp1)
call void @llvm.lifetime.end.p0i8(i64 32, i8* %tmp) call void @llvm.lifetime.end.p5i8(i64 32, i8 addrspace(5)* %tmp)
ret void ret void
} }
declare void @external_void_func_void() #0 declare void @external_void_func_void() #0
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #3 declare void @llvm.lifetime.start.p5i8(i64, i8 addrspace(5)* nocapture) #3
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #3 declare void @llvm.lifetime.end.p5i8(i64, i8 addrspace(5)* nocapture) #3
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { noinline norecurse nounwind } attributes #1 = { noinline norecurse nounwind }
attributes #2 = { nounwind norecurse "no-frame-pointer-elim"="true" } attributes #2 = { nounwind norecurse "no-frame-pointer-elim"="true" }

test/CodeGen/AMDGPU/call-argument-types.ll

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declare void @external_void_func_v32i32(<32 x i32>) #0 declare void @external_void_func_v32i32(<32 x i32>) #0
declare void @external_void_func_v32i32_i32(<32 x i32>, i32) #0 declare void @external_void_func_v32i32_i32(<32 x i32>, i32) #0
; return value and argument ; return value and argument
declare i32 @external_i32_func_i32(i32) #0 declare i32 @external_i32_func_i32(i32) #0
; Structs ; Structs
declare void @external_void_func_struct_i8_i32({ i8, i32 }) #0 declare void @external_void_func_struct_i8_i32({ i8, i32 }) #0
declare void @external_void_func_byval_struct_i8_i32({ i8, i32 }* byval) #0 declare void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval) #0
declare void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 }* sret, { i8, i32 }* byval) #0 declare void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* sret, { i8, i32 } addrspace(5)* byval) #0
declare void @external_void_func_v16i8(<16 x i8>) #0 declare void @external_void_func_v16i8(<16 x i8>) #0
; FIXME: Should be passing -1 ; FIXME: Should be passing -1
; GCN-LABEL: {{^}}test_call_external_void_func_i1_imm: ; GCN-LABEL: {{^}}test_call_external_void_func_i1_imm:
; MESA: s_mov_b32 s36, SCRATCH_RSRC_DWORD ; MESA: s_mov_b32 s36, SCRATCH_RSRC_DWORD
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; MESA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[36:39], s33 offset:12 ; MESA: buffer_load_dword [[RELOAD_VAL1:v[0-9]+]], off, s[36:39], s33 offset:12
; MESA-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s[36:39], [[SP]] offset:4 ; MESA-DAG: buffer_store_dword [[RELOAD_VAL0]], off, s[36:39], [[SP]] offset:4
; MESA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[36:39], [[SP]] offset:8 ; MESA-DAG: buffer_store_dword [[RELOAD_VAL1]], off, s[36:39], [[SP]] offset:8
; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
; GCN-NOT: [[SP]] ; GCN-NOT: [[SP]]
define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 { define amdgpu_kernel void @test_call_external_void_func_byval_struct_i8_i32() #0 {
%val = alloca { i8, i32 }, align 4 %val = alloca { i8, i32 }, align 4, addrspace(5)
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %val, i32 0, i32 0 %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %val, i32 0, i32 1 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %val, i32 0, i32 1
store i8 3, i8* %gep0 store i8 3, i8 addrspace(5)* %gep0
store i32 8, i32* %gep1 store i32 8, i32 addrspace(5)* %gep1
call void @external_void_func_byval_struct_i8_i32({ i8, i32 }* %val) call void @external_void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %val)
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32: ; GCN-LABEL: {{^}}test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32:
; MESA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x600{{$}} ; MESA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x600{{$}}
; HSA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x600{{$}} ; HSA-DAG: s_add_u32 [[SP:s[0-9]+]], [[FP_REG:s[0-9]+]], 0x600{{$}}
; GCN-DAG: v_mov_b32_e32 [[VAL0:v[0-9]+]], 3 ; GCN-DAG: v_mov_b32_e32 [[VAL0:v[0-9]+]], 3
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; GCN-NEXT: s_swappc_b64 ; GCN-NEXT: s_swappc_b64
; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:16 ; GCN-DAG: buffer_load_ubyte [[LOAD_OUT_VAL0:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:16
; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:20 ; GCN-DAG: buffer_load_dword [[LOAD_OUT_VAL1:v[0-9]+]], off, s{{\[[0-9]+:[0-9]+\]}}, [[FP_REG]] offset:20
; GCN-NOT: s_sub_u32 [[SP]] ; GCN-NOT: s_sub_u32 [[SP]]
; GCN: buffer_store_byte [[LOAD_OUT_VAL0]], off ; GCN: buffer_store_byte [[LOAD_OUT_VAL0]], off
; GCN: buffer_store_dword [[LOAD_OUT_VAL1]], off ; GCN: buffer_store_dword [[LOAD_OUT_VAL1]], off
define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 { define amdgpu_kernel void @test_call_external_void_func_sret_struct_i8_i32_byval_struct_i8_i32(i32) #0 {
%in.val = alloca { i8, i32 }, align 4 %in.val = alloca { i8, i32 }, align 4, addrspace(5)
%out.val = alloca { i8, i32 }, align 4 %out.val = alloca { i8, i32 }, align 4, addrspace(5)
%in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %in.val, i32 0, i32 0 %in.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 0
%in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %in.val, i32 0, i32 1 %in.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %in.val, i32 0, i32 1
store i8 3, i8* %in.gep0 store i8 3, i8 addrspace(5)* %in.gep0
store i32 8, i32* %in.gep1 store i32 8, i32 addrspace(5)* %in.gep1
call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 }* %out.val, { i8, i32 }* %in.val) call void @external_void_func_sret_struct_i8_i32_byval_struct_i8_i32({ i8, i32 } addrspace(5)* %out.val, { i8, i32 } addrspace(5)* %in.val)
%out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %out.val, i32 0, i32 0 %out.gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 0
%out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %out.val, i32 0, i32 1 %out.gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %out.val, i32 0, i32 1
%out.val0 = load i8, i8* %out.gep0 %out.val0 = load i8, i8 addrspace(5)* %out.gep0
%out.val1 = load i32, i32* %out.gep1 %out.val1 = load i32, i32 addrspace(5)* %out.gep1
store volatile i8 %out.val0, i8 addrspace(1)* undef store volatile i8 %out.val0, i8 addrspace(1)* undef
store volatile i32 %out.val1, i32 addrspace(1)* undef store volatile i32 %out.val1, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}test_call_external_void_func_v16i8: ; GCN-LABEL: {{^}}test_call_external_void_func_v16i8:
define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 { define amdgpu_kernel void @test_call_external_void_func_v16i8() #0 {
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test/CodeGen/AMDGPU/call-graph-register-usage.ll

Show First 20 Lines • Show All 126 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @indirect_2_level_use_80_sgpr() #0 {
call void @indirect_use_80_sgpr() call void @indirect_use_80_sgpr()
ret void ret void
} }
; GCN-LABEL: {{^}}use_stack0: ; GCN-LABEL: {{^}}use_stack0:
; GCN: ScratchSize: 2052 ; GCN: ScratchSize: 2052
define void @use_stack0() #1 { define void @use_stack0() #1 {
%alloca = alloca [512 x i32], align 4 %alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([512 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([512 x i32] addrspace(5)* %alloca) #0
ret void ret void
} }
; GCN-LABEL: {{^}}use_stack1: ; GCN-LABEL: {{^}}use_stack1:
; GCN: ScratchSize: 404 ; GCN: ScratchSize: 404
define void @use_stack1() #1 { define void @use_stack1() #1 {
%alloca = alloca [100 x i32], align 4 %alloca = alloca [100 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([100 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([100 x i32] addrspace(5)* %alloca) #0
ret void ret void
} }
; GCN-LABEL: {{^}}indirect_use_stack: ; GCN-LABEL: {{^}}indirect_use_stack:
; GCN: ScratchSize: 2124 ; GCN: ScratchSize: 2124
define void @indirect_use_stack() #1 { define void @indirect_use_stack() #1 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([16 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([16 x i32] addrspace(5)* %alloca) #0
call void @use_stack0() call void @use_stack0()
ret void ret void
} }
; GCN-LABEL: {{^}}indirect_2_level_use_stack: ; GCN-LABEL: {{^}}indirect_2_level_use_stack:
; GCN: is_dynamic_callstack = 0 ; GCN: is_dynamic_callstack = 0
; GCN: ScratchSize: 2124 ; GCN: ScratchSize: 2124
define amdgpu_kernel void @indirect_2_level_use_stack() #0 { define amdgpu_kernel void @indirect_2_level_use_stack() #0 {
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define amdgpu_kernel void @usage_external_recurse() #0 { define amdgpu_kernel void @usage_external_recurse() #0 {
call void @external_recurse() call void @external_recurse()
ret void ret void
} }
; GCN-LABEL: {{^}}direct_recursion_use_stack: ; GCN-LABEL: {{^}}direct_recursion_use_stack:
; GCN: ScratchSize: 2056 ; GCN: ScratchSize: 2056
define void @direct_recursion_use_stack(i32 %val) #2 { define void @direct_recursion_use_stack(i32 %val) #2 {
%alloca = alloca [512 x i32], align 4 %alloca = alloca [512 x i32], align 4, addrspace(5)
call void asm sideeffect "; use $0", "v"([512 x i32]* %alloca) #0 call void asm sideeffect "; use $0", "v"([512 x i32] addrspace(5)* %alloca) #0
%cmp = icmp eq i32 %val, 0 %cmp = icmp eq i32 %val, 0
br i1 %cmp, label %ret, label %call br i1 %cmp, label %ret, label %call
call: call:
%val.sub1 = sub i32 %val, 1 %val.sub1 = sub i32 %val, 1
call void @direct_recursion_use_stack(i32 %val.sub1) call void @direct_recursion_use_stack(i32 %val.sub1)
br label %ret br label %ret
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test/CodeGen/AMDGPU/callee-frame-setup.ll

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; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_mov_b32 s5, s32 ; GCN-NEXT: s_mov_b32 s5, s32
; GCN-NEXT: v_mov_b32_e32 v0, 0{{$}} ; GCN-NEXT: v_mov_b32_e32 v0, 0{{$}}
; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s5 offset:4{{$}} ; GCN-NEXT: buffer_store_dword v0, off, s[0:3], s5 offset:4{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @callee_with_stack() #0 { define void @callee_with_stack() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
ret void ret void
} }
; GCN-LABEL: {{^}}callee_with_stack_and_call: ; GCN-LABEL: {{^}}callee_with_stack_and_call:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN: s_mov_b32 s5, s32 ; GCN: s_mov_b32 s5, s32
; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:8 ; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:8
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; GCN: s_mov_b32 s5, s33 ; GCN: s_mov_b32 s5, s33
; GCN-DAG: v_readlane_b32 s35, ; GCN-DAG: v_readlane_b32 s35,
; GCN-DAG: v_readlane_b32 s34, ; GCN-DAG: v_readlane_b32 s34,
; GCN-DAG: v_readlane_b32 s33, ; GCN-DAG: v_readlane_b32 s33,
; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:8 ; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:8
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @callee_with_stack_and_call() #0 { define void @callee_with_stack_and_call() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
call void @external_void_func_void() call void @external_void_func_void()
ret void ret void
} }
; Should be able to copy incoming stack pointer directly to inner ; Should be able to copy incoming stack pointer directly to inner
; call's stack pointer argument. ; call's stack pointer argument.
; There is stack usage only because of the need to evict a VGPR for ; There is stack usage only because of the need to evict a VGPR for
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test/CodeGen/AMDGPU/callee-special-input-sgprs.ll

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; GCN-LABEL: {{^}}use_queue_ptr_addrspacecast: ; GCN-LABEL: {{^}}use_queue_ptr_addrspacecast:
; CIVI: s_load_dword [[APERTURE_LOAD:s[0-9]+]], s[6:7], 0x10 ; CIVI: s_load_dword [[APERTURE_LOAD:s[0-9]+]], s[6:7], 0x10
; GFX9: s_getreg_b32 [[APERTURE_LOAD:s[0-9]+]] ; GFX9: s_getreg_b32 [[APERTURE_LOAD:s[0-9]+]]
; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE_LOAD]] ; GCN: v_mov_b32_e32 v[[HI:[0-9]+]], [[APERTURE_LOAD]]
; GCN: {{flat|global}}_store_dword v{{\[[0-9]+}}:[[HI]]{{\]}} ; GCN: {{flat|global}}_store_dword v{{\[[0-9]+}}:[[HI]]{{\]}}
define void @use_queue_ptr_addrspacecast() #1 { define void @use_queue_ptr_addrspacecast() #1 {
%asc = addrspacecast i32 addrspace(3)* inttoptr (i32 16 to i32 addrspace(3)*) to i32 addrspace(4)* %asc = addrspacecast i32 addrspace(3)* inttoptr (i32 16 to i32 addrspace(3)*) to i32*
store volatile i32 0, i32 addrspace(4)* %asc store volatile i32 0, i32* %asc
ret void ret void
} }
; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr_addrspacecast: ; GCN-LABEL: {{^}}kern_indirect_use_queue_ptr_addrspacecast:
; CIVI: enable_sgpr_queue_ptr = 1 ; CIVI: enable_sgpr_queue_ptr = 1
; CIVI: s_mov_b64 s[6:7], s[4:5] ; CIVI: s_mov_b64 s[6:7], s[4:5]
; GFX9-NOT: s_mov_b64 ; GFX9-NOT: s_mov_b64
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; GCN-LABEL: {{^}}use_stack_workgroup_id_x: ; GCN-LABEL: {{^}}use_stack_workgroup_id_x:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: s_mov_b32 s5, s32 ; GCN: s_mov_b32 s5, s32
; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:4 ; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:4
; GCN: ; use s6 ; GCN: ; use s6
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @use_stack_workgroup_id_x() #1 { define void @use_stack_workgroup_id_x() #1 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%val = call i32 @llvm.amdgcn.workgroup.id.x() %val = call i32 @llvm.amdgcn.workgroup.id.x()
call void asm sideeffect "; use $0", "s"(i32 %val) call void asm sideeffect "; use $0", "s"(i32 %val)
ret void ret void
} }
; GCN-LABEL: {{^}}use_workgroup_id_y: ; GCN-LABEL: {{^}}use_workgroup_id_y:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: ; use s6 ; GCN: ; use s6
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; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[6:7], 0x0
; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0
; GCN: s_load_dword s{{[0-9]+}}, s[10:11], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[10:11], 0x0
; GCN: ; use s[12:13] ; GCN: ; use s[12:13]
; GCN: ; use s14 ; GCN: ; use s14
; GCN: ; use s15 ; GCN: ; use s15
; GCN: ; use s16 ; GCN: ; use s16
define void @use_every_sgpr_input() #1 { define void @use_every_sgpr_input() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*
%val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc %val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0
%queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)*
%val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc %val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc
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} }
; GCN-LABEL: {{^}}func_use_every_sgpr_input_call_use_workgroup_id_xyz: ; GCN-LABEL: {{^}}func_use_every_sgpr_input_call_use_workgroup_id_xyz:
; GCN-DAG: s_mov_b32 s6, s14 ; GCN-DAG: s_mov_b32 s6, s14
; GCN-DAG: s_mov_b32 s7, s15 ; GCN-DAG: s_mov_b32 s7, s15
; GCN-DAG: s_mov_b32 s8, s16 ; GCN-DAG: s_mov_b32 s8, s16
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 { define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*
%val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc %val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0
%queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)*
%val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc %val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc
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; GCN: s_load_dword s{{[0-9]+}}, ; GCN: s_load_dword s{{[0-9]+}},
; GCN: s_load_dword s{{[0-9]+}}, ; GCN: s_load_dword s{{[0-9]+}},
; GCN: s_load_dword s{{[0-9]+}}, ; GCN: s_load_dword s{{[0-9]+}},
; GCN: ; use ; GCN: ; use
; GCN: ; use [[SAVE_X]] ; GCN: ; use [[SAVE_X]]
; GCN: ; use [[SAVE_Y]] ; GCN: ; use [[SAVE_Y]]
; GCN: ; use [[SAVE_Z]] ; GCN: ; use [[SAVE_Z]]
define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 { define void @func_use_every_sgpr_input_call_use_workgroup_id_xyz_spill() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
call void @use_workgroup_id_xyz() call void @use_workgroup_id_xyz()
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0 %dispatch_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #0
%dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)* %dispatch_ptr.bc = bitcast i8 addrspace(2)* %dispatch_ptr to i32 addrspace(2)*
%val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc %val0 = load volatile i32, i32 addrspace(2)* %dispatch_ptr.bc
%queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0 %queue_ptr = call noalias i8 addrspace(2)* @llvm.amdgcn.queue.ptr() #0
%queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)* %queue_ptr.bc = bitcast i8 addrspace(2)* %queue_ptr to i32 addrspace(2)*
%val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc %val1 = load volatile i32, i32 addrspace(2)* %queue_ptr.bc
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test/CodeGen/AMDGPU/callee-special-input-vgprs.ll

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; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v32 ; GCN-NEXT: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v32
; GCN: buffer_load_dword v0, off, s[0:3], s5 offset:4 ; GCN: buffer_load_dword v0, off, s[0:3], s5 offset:4
; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:12 ; 4-byte Folded Reload ; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:12 ; 4-byte Folded Reload
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @too_many_args_use_workitem_id_x_byval( define void @too_many_args_use_workitem_id_x_byval(
i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7, i32 %arg0, i32 %arg1, i32 %arg2, i32 %arg3, i32 %arg4, i32 %arg5, i32 %arg6, i32 %arg7,
i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15, i32 %arg8, i32 %arg9, i32 %arg10, i32 %arg11, i32 %arg12, i32 %arg13, i32 %arg14, i32 %arg15,
i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23, i32 %arg16, i32 %arg17, i32 %arg18, i32 %arg19, i32 %arg20, i32 %arg21, i32 %arg22, i32 %arg23,
i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32* byval %arg32) #1 { i32 %arg24, i32 %arg25, i32 %arg26, i32 %arg27, i32 %arg28, i32 %arg29, i32 %arg30, i32 %arg31, i32 addrspace(5)* byval %arg32) #1 {
%val = call i32 @llvm.amdgcn.workitem.id.x() %val = call i32 @llvm.amdgcn.workitem.id.x()
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
store volatile i32 %arg0, i32 addrspace(1)* undef store volatile i32 %arg0, i32 addrspace(1)* undef
store volatile i32 %arg1, i32 addrspace(1)* undef store volatile i32 %arg1, i32 addrspace(1)* undef
store volatile i32 %arg2, i32 addrspace(1)* undef store volatile i32 %arg2, i32 addrspace(1)* undef
store volatile i32 %arg3, i32 addrspace(1)* undef store volatile i32 %arg3, i32 addrspace(1)* undef
store volatile i32 %arg4, i32 addrspace(1)* undef store volatile i32 %arg4, i32 addrspace(1)* undef
Show All 22 Linesdefine void @too_many_args_use_workitem_id_x_byval(
store volatile i32 %arg24, i32 addrspace(1)* undef store volatile i32 %arg24, i32 addrspace(1)* undef
store volatile i32 %arg25, i32 addrspace(1)* undef store volatile i32 %arg25, i32 addrspace(1)* undef
store volatile i32 %arg26, i32 addrspace(1)* undef store volatile i32 %arg26, i32 addrspace(1)* undef
store volatile i32 %arg27, i32 addrspace(1)* undef store volatile i32 %arg27, i32 addrspace(1)* undef
store volatile i32 %arg28, i32 addrspace(1)* undef store volatile i32 %arg28, i32 addrspace(1)* undef
store volatile i32 %arg29, i32 addrspace(1)* undef store volatile i32 %arg29, i32 addrspace(1)* undef
store volatile i32 %arg30, i32 addrspace(1)* undef store volatile i32 %arg30, i32 addrspace(1)* undef
store volatile i32 %arg31, i32 addrspace(1)* undef store volatile i32 %arg31, i32 addrspace(1)* undef
%private = load volatile i32, i32* %arg32 %private = load volatile i32, i32 addrspace(5)* %arg32
ret void ret void
} }
; frame[0] = emergency stack slot ; frame[0] = emergency stack slot
; frame[1] = ; frame[1] =
; sp[0] = callee emergency stack slot reservation ; sp[0] = callee emergency stack slot reservation
; sp[1] = byval ; sp[1] = byval
Show All 11 Lines
; GCN: buffer_store_dword [[K]], off, s[0:3], s33 offset:4 ; GCN: buffer_store_dword [[K]], off, s[0:3], s33 offset:4
; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GCN: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s33 offset:4 ; GCN: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s33 offset:4
; GCN: buffer_store_dword [[RELOAD_BYVAL]], off, s[0:3], s32 offset:4{{$}} ; GCN: buffer_store_dword [[RELOAD_BYVAL]], off, s[0:3], s32 offset:4{{$}}
; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]], ; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]],
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 { define amdgpu_kernel void @kern_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 999, i32* %alloca store volatile i32 999, i32 addrspace(5)* %alloca
call void @too_many_args_use_workitem_id_x_byval( call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40, i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80, i32 50, i32 60, i32 70, i32 80,
i32 90, i32 100, i32 110, i32 120, i32 90, i32 100, i32 110, i32 120,
i32 130, i32 140, i32 150, i32 160, i32 130, i32 140, i32 150, i32 160,
i32 170, i32 180, i32 190, i32 200, i32 170, i32 180, i32 190, i32 200,
i32 210, i32 220, i32 230, i32 240, i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280, i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320, i32 290, i32 300, i32 310, i32 320,
i32* %alloca) i32 addrspace(5)* %alloca)
ret void ret void
} }
; GCN-LABEL: {{^}}func_call_too_many_args_use_workitem_id_x_byval: ; GCN-LABEL: {{^}}func_call_too_many_args_use_workitem_id_x_byval:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}} ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
; GCN: buffer_store_dword [[K]], off, s[0:3], s5 offset:4 ; GCN: buffer_store_dword [[K]], off, s[0:3], s5 offset:4
; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:12 ; GCN: buffer_store_dword v0, off, s[0:3], s32 offset:12
; GCN: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s5 offset:4 ; GCN: buffer_load_dword [[RELOAD_BYVAL:v[0-9]+]], off, s[0:3], s5 offset:4
; GCN: buffer_store_dword [[RELOAD_BYVAL]], off, s[0:3], s32 offset:4{{$}} ; GCN: buffer_store_dword [[RELOAD_BYVAL]], off, s[0:3], s32 offset:4{{$}}
; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]], ; GCN: v_mov_b32_e32 [[RELOAD_BYVAL]],
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
define void @func_call_too_many_args_use_workitem_id_x_byval() #1 { define void @func_call_too_many_args_use_workitem_id_x_byval() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 999, i32* %alloca store volatile i32 999, i32 addrspace(5)* %alloca
call void @too_many_args_use_workitem_id_x_byval( call void @too_many_args_use_workitem_id_x_byval(
i32 10, i32 20, i32 30, i32 40, i32 10, i32 20, i32 30, i32 40,
i32 50, i32 60, i32 70, i32 80, i32 50, i32 60, i32 70, i32 80,
i32 90, i32 100, i32 110, i32 120, i32 90, i32 100, i32 110, i32 120,
i32 130, i32 140, i32 150, i32 160, i32 130, i32 140, i32 150, i32 160,
i32 170, i32 180, i32 190, i32 200, i32 170, i32 180, i32 190, i32 200,
i32 210, i32 220, i32 230, i32 240, i32 210, i32 220, i32 230, i32 240,
i32 250, i32 260, i32 270, i32 280, i32 250, i32 260, i32 270, i32 280,
i32 290, i32 300, i32 310, i32 320, i32 290, i32 300, i32 310, i32 320,
i32* %alloca) i32 addrspace(5)* %alloca)
ret void ret void
} }
; GCN-LABEL: {{^}}too_many_args_use_workitem_id_xyz: ; GCN-LABEL: {{^}}too_many_args_use_workitem_id_xyz:
; GCN: s_mov_b32 s5, s32 ; GCN: s_mov_b32 s5, s32
; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:16 ; 4-byte Folded Spill ; GCN: buffer_store_dword v32, off, s[0:3], s5 offset:16 ; 4-byte Folded Spill
; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:4{{$}} ; GCN: buffer_load_dword v32, off, s[0:3], s5 offset:4{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+]}}, v32 ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+]}}, v32
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test/CodeGen/AMDGPU/captured-frame-index.ll

; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-- -mcpu=tahiti -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}store_fi_lifetime: ; GCN-LABEL: {{^}}store_fi_lifetime:
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[FI]] ; GCN: buffer_store_dword [[FI]]
define amdgpu_kernel void @store_fi_lifetime(i32 addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @store_fi_lifetime(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%b = alloca i8 %b = alloca i8, addrspace(5)
call void @llvm.lifetime.start.p0i8(i64 1, i8* %b) call void @llvm.lifetime.start.p5i8(i64 1, i8 addrspace(5)* %b)
store volatile i8* %b, i8* addrspace(1)* undef store volatile i8 addrspace(5)* %b, i8 addrspace(5)* addrspace(1)* undef
call void @llvm.lifetime.end.p0i8(i64 1, i8* %b) call void @llvm.lifetime.end.p5i8(i64 1, i8 addrspace(5)* %b)
ret void ret void
} }
; GCN-LABEL: {{^}}stored_fi_to_lds: ; GCN-LABEL: {{^}}stored_fi_to_lds:
; GCN: s_load_dword [[LDSPTR:s[0-9]+]] ; GCN: s_load_dword [[LDSPTR:s[0-9]+]]
; GCN: buffer_store_dword v{{[0-9]+}}, off, ; GCN: buffer_store_dword v{{[0-9]+}}, off,
; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[ZERO0:v[0-9]+]], 4{{$}}
; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]] ; GCN: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]] ; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO0]]
define amdgpu_kernel void @stored_fi_to_lds(float* addrspace(3)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_lds(float addrspace(5)* addrspace(3)* %ptr) #0 {
%tmp = alloca float %tmp = alloca float, addrspace(5)
store float 4.0, float *%tmp store float 4.0, float addrspace(5)*%tmp
store float* %tmp, float* addrspace(3)* %ptr store float addrspace(5)* %tmp, float addrspace(5)* addrspace(3)* %ptr
ret void ret void
} }
; Offset is applied ; Offset is applied
; GCN-LABEL: {{^}}stored_fi_to_lds_2_small_objects: ; GCN-LABEL: {{^}}stored_fi_to_lds_2_small_objects:
; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}} ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}}
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}} ; GCN-DAG: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}}
; GCN-DAG: s_load_dword [[LDSPTR:s[0-9]+]] ; GCN-DAG: s_load_dword [[LDSPTR:s[0-9]+]]
; GCN-DAG: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]] ; GCN-DAG: v_mov_b32_e32 [[VLDSPTR:v[0-9]+]], [[LDSPTR]]
; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO]] ; GCN: ds_write_b32 [[VLDSPTR]], [[ZERO]]
; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}} ; GCN-DAG: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}}
; GCN: ds_write_b32 [[VLDSPTR]], [[FI1]] ; GCN: ds_write_b32 [[VLDSPTR]], [[FI1]]
define amdgpu_kernel void @stored_fi_to_lds_2_small_objects(float* addrspace(3)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_lds_2_small_objects(float addrspace(5)* addrspace(3)* %ptr) #0 {
%tmp0 = alloca float %tmp0 = alloca float, addrspace(5)
%tmp1 = alloca float %tmp1 = alloca float, addrspace(5)
store float 4.0, float* %tmp0 store float 4.0, float addrspace(5)* %tmp0
store float 4.0, float* %tmp1 store float 4.0, float addrspace(5)* %tmp1
store volatile float* %tmp0, float* addrspace(3)* %ptr store volatile float addrspace(5)* %tmp0, float addrspace(5)* addrspace(3)* %ptr
store volatile float* %tmp1, float* addrspace(3)* %ptr store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(3)* %ptr
ret void ret void
} }
; Same frame index is used multiple times in the store ; Same frame index is used multiple times in the store
; GCN-LABEL: {{^}}stored_fi_to_self: ; GCN-LABEL: {{^}}stored_fi_to_self:
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x4d2{{$}} ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x4d2{{$}}
; GCN: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword [[K]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}} ; GCN-DAG: v_mov_b32_e32 [[ZERO:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[ZERO]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword [[ZERO]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @stored_fi_to_self() #0 { define amdgpu_kernel void @stored_fi_to_self() #0 {
%tmp = alloca i32* %tmp = alloca i32 addrspace(5)*, addrspace(5)
; Avoid optimizing everything out ; Avoid optimizing everything out
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp
%bitcast = bitcast i32** %tmp to i32* %bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp to i32 addrspace(5)*
store volatile i32* %bitcast, i32** %tmp store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp
ret void ret void
} }
; GCN-LABEL: {{^}}stored_fi_to_self_offset: ; GCN-LABEL: {{^}}stored_fi_to_self_offset:
; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 32{{$}} ; GCN-DAG: v_mov_b32_e32 [[K0:v[0-9]+]], 32{{$}}
; GCN: buffer_store_dword [[K0]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword [[K0]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x4d2{{$}} ; GCN-DAG: v_mov_b32_e32 [[K1:v[0-9]+]], 0x4d2{{$}}
; GCN: buffer_store_dword [[K1]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:2052{{$}} ; GCN: buffer_store_dword [[K1]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:2052{{$}}
; GCN: v_mov_b32_e32 [[OFFSETK:v[0-9]+]], 0x804{{$}} ; GCN: v_mov_b32_e32 [[OFFSETK:v[0-9]+]], 0x804{{$}}
; GCN: buffer_store_dword [[OFFSETK]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:2052{{$}} ; GCN: buffer_store_dword [[OFFSETK]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:2052{{$}}
define amdgpu_kernel void @stored_fi_to_self_offset() #0 { define amdgpu_kernel void @stored_fi_to_self_offset() #0 {
%tmp0 = alloca [512 x i32] %tmp0 = alloca [512 x i32], addrspace(5)
%tmp1 = alloca i32* %tmp1 = alloca i32 addrspace(5)*, addrspace(5)
; Avoid optimizing everything out ; Avoid optimizing everything out
%tmp0.cast = bitcast [512 x i32]* %tmp0 to i32* %tmp0.cast = bitcast [512 x i32] addrspace(5)* %tmp0 to i32 addrspace(5)*
store volatile i32 32, i32* %tmp0.cast store volatile i32 32, i32 addrspace(5)* %tmp0.cast
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp1 store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp1
%bitcast = bitcast i32** %tmp1 to i32* %bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp1 to i32 addrspace(5)*
store volatile i32* %bitcast, i32** %tmp1 store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp1
ret void ret void
} }
; GCN-LABEL: {{^}}stored_fi_to_fi: ; GCN-LABEL: {{^}}stored_fi_to_fi:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:12{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:12{{$}}
; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}} ; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}}
; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:12{{$}} ; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:12{{$}}
; GCN: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}} ; GCN: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}}
; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}} ; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}}
define amdgpu_kernel void @stored_fi_to_fi() #0 { define amdgpu_kernel void @stored_fi_to_fi() #0 {
%tmp0 = alloca i32* %tmp0 = alloca i32 addrspace(5)*, addrspace(5)
%tmp1 = alloca i32* %tmp1 = alloca i32 addrspace(5)*, addrspace(5)
%tmp2 = alloca i32* %tmp2 = alloca i32 addrspace(5)*, addrspace(5)
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp0 store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp0
store volatile i32* inttoptr (i32 5678 to i32*), i32** %tmp1 store volatile i32 addrspace(5)* inttoptr (i32 5678 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp1
store volatile i32* inttoptr (i32 9999 to i32*), i32** %tmp2 store volatile i32 addrspace(5)* inttoptr (i32 9999 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp2
%bitcast1 = bitcast i32** %tmp1 to i32* %bitcast1 = bitcast i32 addrspace(5)* addrspace(5)* %tmp1 to i32 addrspace(5)*
%bitcast2 = bitcast i32** %tmp2 to i32* ; at offset 8 %bitcast2 = bitcast i32 addrspace(5)* addrspace(5)* %tmp2 to i32 addrspace(5)* ; at offset 8
store volatile i32* %bitcast1, i32** %tmp2 ; store offset 4 at offset 8 store volatile i32 addrspace(5)* %bitcast1, i32 addrspace(5)* addrspace(5)* %tmp2 ; store offset 4 at offset 8
store volatile i32* %bitcast2, i32** %tmp1 ; store offset 8 at offset 4 store volatile i32 addrspace(5)* %bitcast2, i32 addrspace(5)* addrspace(5)* %tmp1 ; store offset 8 at offset 4
ret void ret void
} }
; GCN-LABEL: {{^}}stored_fi_to_global: ; GCN-LABEL: {{^}}stored_fi_to_global:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[FI]] ; GCN: buffer_store_dword [[FI]]
define amdgpu_kernel void @stored_fi_to_global(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_global(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp = alloca float %tmp = alloca float, addrspace(5)
store float 0.0, float *%tmp store float 0.0, float addrspace(5)*%tmp
store float* %tmp, float* addrspace(1)* %ptr store float addrspace(5)* %tmp, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
; Offset is applied ; Offset is applied
; GCN-LABEL: {{^}}stored_fi_to_global_2_small_objects: ; GCN-LABEL: {{^}}stored_fi_to_global_2_small_objects:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:8{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:12{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:12{{$}}
; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}} ; GCN: v_mov_b32_e32 [[FI1:v[0-9]+]], 8{{$}}
; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN: buffer_store_dword [[FI1]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
; GCN-DAG: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}} ; GCN-DAG: v_mov_b32_e32 [[FI2:v[0-9]+]], 12{{$}}
; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN: buffer_store_dword [[FI2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @stored_fi_to_global_2_small_objects(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_global_2_small_objects(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp0 = alloca float %tmp0 = alloca float, addrspace(5)
%tmp1 = alloca float %tmp1 = alloca float, addrspace(5)
%tmp2 = alloca float %tmp2 = alloca float, addrspace(5)
store volatile float 0.0, float *%tmp0 store volatile float 0.0, float addrspace(5)*%tmp0
store volatile float 0.0, float *%tmp1 store volatile float 0.0, float addrspace(5)*%tmp1
store volatile float 0.0, float *%tmp2 store volatile float 0.0, float addrspace(5)*%tmp2
store volatile float* %tmp1, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(1)* %ptr
store volatile float* %tmp2, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp2, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}stored_fi_to_global_huge_frame_offset: ; GCN-LABEL: {{^}}stored_fi_to_global_huge_frame_offset:
; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 [[BASE_0:v[0-9]+]], 0{{$}}
; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword [[BASE_0]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:4{{$}}
; FIXME: Re-initialize ; FIXME: Re-initialize
; GCN: v_mov_b32_e32 [[BASE_0_1:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[BASE_0_1:v[0-9]+]], 4{{$}}
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}} ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 0x3e7{{$}}
; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]] ; GCN-DAG: v_add_i32_e32 [[BASE_1_OFF_1:v[0-9]+]], vcc, 0x3ffc, [[BASE_0_1]]
; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]] ; GCN: v_add_i32_e32 [[BASE_1_OFF_2:v[0-9]+]], vcc, 56, [[BASE_0_1]]
; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} ; GCN: buffer_store_dword [[K]], [[BASE_1_OFF_1]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}
; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}} ; GCN: buffer_store_dword [[BASE_1_OFF_2]], off, s{{\[[0-9]+:[0-9]+\]}}, 0{{$}}
define amdgpu_kernel void @stored_fi_to_global_huge_frame_offset(i32* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_fi_to_global_huge_frame_offset(i32 addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp0 = alloca [4096 x i32] %tmp0 = alloca [4096 x i32], addrspace(5)
%tmp1 = alloca [4096 x i32] %tmp1 = alloca [4096 x i32], addrspace(5)
%gep0.tmp0 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 0 %gep0.tmp0 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 0
store volatile i32 0, i32* %gep0.tmp0 store volatile i32 0, i32 addrspace(5)* %gep0.tmp0
%gep1.tmp0 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 4095 %gep1.tmp0 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 4095
store volatile i32 999, i32* %gep1.tmp0 store volatile i32 999, i32 addrspace(5)* %gep1.tmp0
%gep0.tmp1 = getelementptr [4096 x i32], [4096 x i32]* %tmp0, i32 0, i32 14 %gep0.tmp1 = getelementptr [4096 x i32], [4096 x i32] addrspace(5)* %tmp0, i32 0, i32 14
store i32* %gep0.tmp1, i32* addrspace(1)* %ptr store i32 addrspace(5)* %gep0.tmp1, i32 addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
@g1 = external addrspace(1) global i32* @g1 = external addrspace(1) global i32 addrspace(5)*
; This was leaving a dead node around resulting in failing to select ; This was leaving a dead node around resulting in failing to select
; on the leftover AssertZext's ValueType operand. ; on the leftover AssertZext's ValueType operand.
; GCN-LABEL: {{^}}cannot_select_assertzext_valuetype: ; GCN-LABEL: {{^}}cannot_select_assertzext_valuetype:
; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}} ; GCN: s_getpc_b64 s{{\[}}[[PC_LO:[0-9]+]]:[[PC_HI:[0-9]+]]{{\]}}
; GCN: s_add_u32 s{{[0-9]+}}, s[[PC_LO]], g1@gotpcrel32@lo+4 ; GCN: s_add_u32 s{{[0-9]+}}, s[[PC_LO]], g1@gotpcrel32@lo+4
; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC_HI]], g1@gotpcrel32@hi+4 ; GCN: s_addc_u32 s{{[0-9]+}}, s[[PC_HI]], g1@gotpcrel32@hi+4
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: buffer_store_dword [[FI]] ; GCN: buffer_store_dword [[FI]]
define amdgpu_kernel void @cannot_select_assertzext_valuetype(i32 addrspace(1)* %out, i32 %idx) #0 { define amdgpu_kernel void @cannot_select_assertzext_valuetype(i32 addrspace(1)* %out, i32 %idx) #0 {
entry: entry:
%b = alloca i32, align 4 %b = alloca i32, align 4, addrspace(5)
%tmp1 = load volatile i32*, i32* addrspace(1)* @g1, align 4 %tmp1 = load volatile i32 addrspace(5)*, i32 addrspace(5)* addrspace(1)* @g1, align 4
%arrayidx = getelementptr inbounds i32, i32* %tmp1, i32 %idx %arrayidx = getelementptr inbounds i32, i32 addrspace(5)* %tmp1, i32 %idx
%tmp2 = load i32, i32* %arrayidx, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx, align 4
store volatile i32* %b, i32* addrspace(1)* undef store volatile i32 addrspace(5)* %b, i32 addrspace(5)* addrspace(1)* undef
ret void ret void
} }
declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.start.p5i8(i64, i8 addrspace(5)* nocapture) #1
declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1 declare void @llvm.lifetime.end.p5i8(i64, i8 addrspace(5)* nocapture) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }

test/CodeGen/AMDGPU/cgp-addressing-modes-flat.ll

; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-CIVI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-CIVI %s
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-CIVI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-CIVI %s
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s
; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=bonaire -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=CIVI %s
; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s ; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=CIVI %s
; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -mattr=-flat-for-global -mattr=-promote-alloca < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
; OPT-LABEL: @test_no_sink_flat_small_offset_i32( ; OPT-LABEL: @test_no_sink_flat_small_offset_i32(
; OPT-CIVI: getelementptr i32, i32 addrspace(4)* %in ; OPT-CIVI: getelementptr i32, i32* %in
; OPT-CIVI: br i1 ; OPT-CIVI: br i1
; OPT-CIVI-NOT: ptrtoint ; OPT-CIVI-NOT: ptrtoint
; OPT-GFX9: br ; OPT-GFX9: br
; OPT-GFX9: %sunkaddr = getelementptr i8, i8 addrspace(4)* %0, i64 28 ; OPT-GFX9: %sunkaddr = getelementptr i8, i8* %0, i64 28
; OPT-GFX9: %1 = bitcast i8 addrspace(4)* %sunkaddr to i32 addrspace(4)* ; OPT-GFX9: %1 = bitcast i8* %sunkaddr to i32*
; OPT-GFX9: load i32, i32 addrspace(4)* %1 ; OPT-GFX9: load i32, i32* %1
; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32: ; GCN-LABEL: {{^}}test_no_sink_flat_small_offset_i32:
; GCN: flat_load_dword ; GCN: flat_load_dword
; GCN: {{^}}BB0_2: ; GCN: {{^}}BB0_2:
define amdgpu_kernel void @test_no_sink_flat_small_offset_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) { define amdgpu_kernel void @test_no_sink_flat_small_offset_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(4)* %in.gep %tmp1 = load i32, i32* %in.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_global_i32( ; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_global_i32(
; OPT: getelementptr i32, i32 addrspace(4)* %out, ; OPT: getelementptr i32, i32* %out,
; rOPT-CI-NOT: getelementptr ; rOPT-CI-NOT: getelementptr
; OPT: br i1 ; OPT: br i1
; OPT-CI: addrspacecast ; OPT-CI: addrspacecast
; OPT-CI: getelementptr ; OPT-CI: getelementptr
; OPT-CI: bitcast ; OPT-CI: bitcast
; OPT: br label ; OPT: br label
; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_global_i32: ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_global_i32:
; CI: buffer_load_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28 ; CI: buffer_load_dword {{v[0-9]+}}, off, s{{\[[0-9]+:[0-9]+\]}}, 0 offset:28
define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_global_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) { define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_global_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%cast = addrspacecast i32 addrspace(4)* %in.gep to i32 addrspace(1)* %cast = addrspacecast i32* %in.gep to i32 addrspace(1)*
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(1)* %cast %tmp1 = load i32, i32 addrspace(1)* %cast
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_constant_i32( ; OPT-LABEL: @test_sink_noop_addrspacecast_flat_to_constant_i32(
; OPT: getelementptr i32, i32 addrspace(4)* %out, ; OPT: getelementptr i32, i32* %out,
; OPT-CI-NOT: getelementptr ; OPT-CI-NOT: getelementptr
; OPT: br i1 ; OPT: br i1
; OPT-CI: addrspacecast ; OPT-CI: addrspacecast
; OPT-CI: getelementptr ; OPT-CI: getelementptr
; OPT-CI: bitcast ; OPT-CI: bitcast
; OPT: br label ; OPT: br label
; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32: ; GCN-LABEL: {{^}}test_sink_noop_addrspacecast_flat_to_constant_i32:
; CI: s_load_dword {{s[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd ; CI: s_load_dword {{s[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_constant_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %in, i32 %cond) { define amdgpu_kernel void @test_sink_noop_addrspacecast_flat_to_constant_i32(i32* %out, i32* %in, i32 %cond) {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 999999 %out.gep = getelementptr i32, i32* %out, i64 999999
%in.gep = getelementptr i32, i32 addrspace(4)* %in, i64 7 %in.gep = getelementptr i32, i32* %in, i64 7
%cast = addrspacecast i32 addrspace(4)* %in.gep to i32 addrspace(2)* %cast = addrspacecast i32* %in.gep to i32 addrspace(2)*
%tmp0 = icmp eq i32 %cond, 0 %tmp0 = icmp eq i32 %cond, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i32, i32 addrspace(2)* %cast %tmp1 = load i32, i32 addrspace(2)* %cast
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_flat_small_max_flat_offset( ; OPT-LABEL: @test_sink_flat_small_max_flat_offset(
; OPT-CIVI: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4095 ; OPT-CIVI: %in.gep = getelementptr i8, i8* %in, i64 4095
; OPT-CIVI: br ; OPT-CIVI: br
; OPT-CIVI-NOT: getelementptr ; OPT-CIVI-NOT: getelementptr
; OPT-CIVI: load i8, i8 addrspace(4)* %in.gep ; OPT-CIVI: load i8, i8* %in.gep
; OPT-GFX9: br ; OPT-GFX9: br
; OPT-GFX9: %sunkaddr = getelementptr i8, i8 addrspace(4)* %in, i64 4095 ; OPT-GFX9: %sunkaddr = getelementptr i8, i8* %in, i64 4095
; OPT-GFX9: load i8, i8 addrspace(4)* %sunkaddr ; OPT-GFX9: load i8, i8* %sunkaddr
; GCN-LABEL: {{^}}test_sink_flat_small_max_flat_offset: ; GCN-LABEL: {{^}}test_sink_flat_small_max_flat_offset:
; GFX9: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}} ; GFX9: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
; CIVI: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} ; CIVI: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @test_sink_flat_small_max_flat_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in) #1 { define amdgpu_kernel void @test_sink_flat_small_max_flat_offset(i32* %out, i8* %in) #1 {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 %out.gep = getelementptr i32, i32* %out, i32 1024
%in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4095 %in.gep = getelementptr i8, i8* %in, i64 4095
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i8, i8 addrspace(4)* %in.gep %tmp1 = load i8, i8* %in.gep
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp2, %if ], [ 0, %entry ] %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_sink_flat_small_max_plus_1_flat_offset( ; OPT-LABEL: @test_sink_flat_small_max_plus_1_flat_offset(
; OPT: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4096 ; OPT: %in.gep = getelementptr i8, i8* %in, i64 4096
; OPT: br ; OPT: br
; OPT-NOT: getelementptr ; OPT-NOT: getelementptr
; OPT: load i8, i8 addrspace(4)* %in.gep ; OPT: load i8, i8* %in.gep
; GCN-LABEL: {{^}}test_sink_flat_small_max_plus_1_flat_offset: ; GCN-LABEL: {{^}}test_sink_flat_small_max_plus_1_flat_offset:
; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @test_sink_flat_small_max_plus_1_flat_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in) #1 { define amdgpu_kernel void @test_sink_flat_small_max_plus_1_flat_offset(i32* %out, i8* %in) #1 {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i64 99999 %out.gep = getelementptr i32, i32* %out, i64 99999
%in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 4096 %in.gep = getelementptr i8, i8* %in, i64 4096
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i8, i8 addrspace(4)* %in.gep %tmp1 = load i8, i8* %in.gep
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp2, %if ], [ 0, %entry ] %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_no_sink_flat_reg_offset( ; OPT-LABEL: @test_no_sink_flat_reg_offset(
; OPT: %in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 %reg ; OPT: %in.gep = getelementptr i8, i8* %in, i64 %reg
; OPT: br ; OPT: br
; OPT-NOT: getelementptr ; OPT-NOT: getelementptr
; OPT: load i8, i8 addrspace(4)* %in.gep ; OPT: load i8, i8* %in.gep
; GCN-LABEL: {{^}}test_no_sink_flat_reg_offset: ; GCN-LABEL: {{^}}test_no_sink_flat_reg_offset:
; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_load_sbyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @test_no_sink_flat_reg_offset(i32 addrspace(4)* %out, i8 addrspace(4)* %in, i64 %reg) #1 { define amdgpu_kernel void @test_no_sink_flat_reg_offset(i32* %out, i8* %in, i64 %reg) #1 {
entry: entry:
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 %out.gep = getelementptr i32, i32* %out, i32 1024
%in.gep = getelementptr i8, i8 addrspace(4)* %in, i64 %reg %in.gep = getelementptr i8, i8* %in, i64 %reg
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
%tmp1 = load i8, i8 addrspace(4)* %in.gep %tmp1 = load i8, i8* %in.gep
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp2, %if ], [ 0, %entry ] %x = phi i32 [ %tmp2, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(4)* %out.gep store i32 %x, i32* %out.gep
br label %done br label %done
done: done:
ret void ret void
} }
declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0 declare i32 @llvm.amdgcn.mbcnt.lo(i32, i32) #0
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }
attributes #2 = { nounwind argmemonly } attributes #2 = { nounwind argmemonly }

test/CodeGen/AMDGPU/cgp-addressing-modes.ll

; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tahiti < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-SI -check-prefix=OPT-SICIVI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tahiti < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-SI -check-prefix=OPT-SICIVI %s
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-SICIVI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=bonaire < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-CI -check-prefix=OPT-SICIVI %s
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-SICIVI %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-VI -check-prefix=OPT-SICIVI %s
; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn-unknown-unknown -mcpu=gfx900 < %s | FileCheck -check-prefix=OPT -check-prefix=OPT-GFX9 %s
; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s ; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=SI -check-prefix=SICIVI %s
; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=SICIVI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=CI -check-prefix=SICIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-scalarize-global-loads=false -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-scalarize-global-loads=false -mattr=-promote-alloca -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=VI -check-prefix=SICIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-promote-alloca -amdgpu-scalarize-global-loads=false -amdgpu-sroa=0 < %s | FileCheck -check-prefix=GCN -check-prefix=GFX9 %s
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
; OPT-LABEL: @test_sink_global_small_offset_i32( ; OPT-LABEL: @test_sink_global_small_offset_i32(
; OPT-CI-NOT: getelementptr i32, i32 addrspace(1)* %in ; OPT-CI-NOT: getelementptr i32, i32 addrspace(1)* %in
; OPT-VI: getelementptr i32, i32 addrspace(1)* %in ; OPT-VI: getelementptr i32, i32 addrspace(1)* %in
; OPT: br i1 ; OPT: br i1
; OPT-CI: getelementptr i8, ; OPT-CI: getelementptr i8,
; GCN-LABEL: {{^}}test_sink_global_small_offset_i32: ; GCN-LABEL: {{^}}test_sink_global_small_offset_i32:
▲ Show 20 Lines • Show All 113 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32: ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:4092{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:4092{{$}}
; GCN: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:4092{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, off, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offset:4092{{$}}
; GCN: {{^}}BB4_2: ; GCN: {{^}}BB4_2:
define amdgpu_kernel void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_sink_scratch_small_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4 %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1022 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1022
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
store volatile i32 123, i32* %alloca.gep store volatile i32 123, i32 addrspace(5)* %alloca.gep
%tmp1 = load volatile i32, i32* %alloca.gep %tmp1 = load volatile i32, i32 addrspace(5)* %alloca.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep.0 store i32 %x, i32 addrspace(1)* %out.gep.0
%load = load volatile i32, i32* %alloca.gep %load = load volatile i32, i32 addrspace(5)* %alloca.gep
store i32 %load, i32 addrspace(1)* %out.gep.1 store i32 %load, i32 addrspace(1)* %out.gep.1
br label %done br label %done
done: done:
ret void ret void
} }
; This ends up not fitting due to the reserved 4 bytes at offset 0 ; This ends up not fitting due to the reserved 4 bytes at offset 0
; OPT-LABEL: @test_sink_scratch_small_offset_i32_reserved( ; OPT-LABEL: @test_sink_scratch_small_offset_i32_reserved(
; OPT-NOT: getelementptr [512 x i32] ; OPT-NOT: getelementptr [512 x i32]
; OPT: br i1 ; OPT: br i1
; OPT: getelementptr i8, ; OPT: getelementptr i8,
; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32_reserved: ; GCN-LABEL: {{^}}test_sink_scratch_small_offset_i32_reserved:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: v_mov_b32_e32 [[BASE_FI0:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[BASE_FI0:v[0-9]+]], 4
; GCN: buffer_store_dword {{v[0-9]+}}, [[BASE_FI0]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, [[BASE_FI0]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}
; GCN: v_mov_b32_e32 [[BASE_FI1:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[BASE_FI1:v[0-9]+]], 4
; GCN: buffer_load_dword {{v[0-9]+}}, [[BASE_FI1]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, [[BASE_FI1]], {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen offset:4092{{$}}
; GCN: {{^BB[0-9]+}}_2: ; GCN: {{^BB[0-9]+}}_2:
define amdgpu_kernel void @test_sink_scratch_small_offset_i32_reserved(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_sink_scratch_small_offset_i32_reserved(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4 %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1023 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1023
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
store volatile i32 123, i32* %alloca.gep store volatile i32 123, i32 addrspace(5)* %alloca.gep
%tmp1 = load volatile i32, i32* %alloca.gep %tmp1 = load volatile i32, i32 addrspace(5)* %alloca.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep.0 store i32 %x, i32 addrspace(1)* %out.gep.0
%load = load volatile i32, i32* %alloca.gep %load = load volatile i32, i32 addrspace(5)* %alloca.gep
store i32 %load, i32 addrspace(1)* %out.gep.1 store i32 %load, i32 addrspace(1)* %out.gep.1
br label %done br label %done
done: done:
ret void ret void
} }
; OPT-LABEL: @test_no_sink_scratch_large_offset_i32( ; OPT-LABEL: @test_no_sink_scratch_large_offset_i32(
; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024 ; OPT: %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024
; OPT: br i1 ; OPT: br i1
; OPT-NOT: ptrtoint ; OPT-NOT: ptrtoint
; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32: ; GCN-LABEL: {{^}}test_no_sink_scratch_large_offset_i32:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}} ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen{{$}}
; GCN: {{^BB[0-9]+}}_2: ; GCN: {{^BB[0-9]+}}_2:
define amdgpu_kernel void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) { define amdgpu_kernel void @test_no_sink_scratch_large_offset_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %in, i32 %arg) {
entry: entry:
%alloca = alloca [512 x i32], align 4 %alloca = alloca [512 x i32], align 4, addrspace(5)
%out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998 %out.gep.0 = getelementptr i32, i32 addrspace(1)* %out, i64 999998
%out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999 %out.gep.1 = getelementptr i32, i32 addrspace(1)* %out, i64 999999
%add.arg = add i32 %arg, 8 %add.arg = add i32 %arg, 8
%alloca.gep = getelementptr [512 x i32], [512 x i32]* %alloca, i32 0, i32 1024 %alloca.gep = getelementptr [512 x i32], [512 x i32] addrspace(5)* %alloca, i32 0, i32 1024
%tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0 %tid = call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) #0
%tmp0 = icmp eq i32 %tid, 0 %tmp0 = icmp eq i32 %tid, 0
br i1 %tmp0, label %endif, label %if br i1 %tmp0, label %endif, label %if
if: if:
store volatile i32 123, i32* %alloca.gep store volatile i32 123, i32 addrspace(5)* %alloca.gep
%tmp1 = load volatile i32, i32* %alloca.gep %tmp1 = load volatile i32, i32 addrspace(5)* %alloca.gep
br label %endif br label %endif
endif: endif:
%x = phi i32 [ %tmp1, %if ], [ 0, %entry ] %x = phi i32 [ %tmp1, %if ], [ 0, %entry ]
store i32 %x, i32 addrspace(1)* %out.gep.0 store i32 %x, i32 addrspace(1)* %out.gep.0
%load = load volatile i32, i32* %alloca.gep %load = load volatile i32, i32 addrspace(5)* %alloca.gep
store i32 %load, i32 addrspace(1)* %out.gep.1 store i32 %load, i32 addrspace(1)* %out.gep.1
br label %done br label %done
done: done:
ret void ret void
} }
; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32: ; GCN-LABEL: {{^}}test_sink_global_vreg_sreg_i32:
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test/CodeGen/AMDGPU/collapse-endcf.ll

Show First 20 Lines • Show All 231 Lines • ▼ Show 20 Linesbb1: ; preds = %Flow1, %bb1, %bb
%tmp = icmp slt i32 %arg, 519 %tmp = icmp slt i32 %arg, 519
br i1 %tmp, label %bb2, label %bb1 br i1 %tmp, label %bb2, label %bb1
bb2: ; preds = %bb1 bb2: ; preds = %bb1
%tmp3 = icmp eq i32 %arg, 0 %tmp3 = icmp eq i32 %arg, 0
br i1 %tmp3, label %bb4, label %bb10 br i1 %tmp3, label %bb4, label %bb10
bb4: ; preds = %bb2 bb4: ; preds = %bb2
%tmp6 = load float, float* undef %tmp6 = load float, float addrspace(5)* undef
%tmp7 = fcmp olt float %tmp6, 0.0 %tmp7 = fcmp olt float %tmp6, 0.0
br i1 %tmp7, label %bb8, label %Flow br i1 %tmp7, label %bb8, label %Flow
bb8: ; preds = %bb4 bb8: ; preds = %bb4
%tmp9 = insertelement <4 x float> undef, float 0.0, i32 1 %tmp9 = insertelement <4 x float> undef, float 0.0, i32 1
br label %Flow br label %Flow
Flow: ; preds = %bb8, %bb4 Flow: ; preds = %bb8, %bb4
%tmp8 = phi <4 x float> [ %tmp9, %bb8 ], [ zeroinitializer, %bb4 ] %tmp8 = phi <4 x float> [ %tmp9, %bb8 ], [ zeroinitializer, %bb4 ]
br label %bb10 br label %bb10
bb10: ; preds = %Flow, %bb2 bb10: ; preds = %Flow, %bb2
%tmp11 = phi <4 x float> [ zeroinitializer, %bb2 ], [ %tmp8, %Flow ] %tmp11 = phi <4 x float> [ zeroinitializer, %bb2 ], [ %tmp8, %Flow ]
br i1 %tmp3, label %bb12, label %Flow1 br i1 %tmp3, label %bb12, label %Flow1
Flow1: ; preds = %bb10 Flow1: ; preds = %bb10
br label %bb1 br label %bb1
bb12: ; preds = %bb10 bb12: ; preds = %bb10
store volatile <4 x float> %tmp11, <4 x float>* undef, align 16 store volatile <4 x float> %tmp11, <4 x float> addrspace(5)* undef, align 16
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #0 declare i32 @llvm.amdgcn.workitem.id.x() #0
declare void @llvm.amdgcn.s.barrier() #1 declare void @llvm.amdgcn.s.barrier() #1
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind convergent } attributes #1 = { nounwind convergent }
attributes #2 = { nounwind } attributes #2 = { nounwind }

test/CodeGen/AMDGPU/commute-compares.ll

Show First 20 Lines • Show All 697 Lines • ▼ Show 20 Lines
; GCN-LABEL: {{^}}commute_frameindex: ; GCN-LABEL: {{^}}commute_frameindex:
; XGCN: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}} ; XGCN: v_cmp_eq_u32_e32 vcc, 0, v{{[0-9]+}}
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}} ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4{{$}}
; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]] ; GCN: v_cmp_eq_u32_e32 vcc, v{{[0-9]+}}, [[FI]]
define amdgpu_kernel void @commute_frameindex(i32 addrspace(1)* nocapture %out) #0 { define amdgpu_kernel void @commute_frameindex(i32 addrspace(1)* nocapture %out) #0 {
entry: entry:
%stack0 = alloca i32 %stack0 = alloca i32, addrspace(5)
%ptr0 = load volatile i32*, i32* addrspace(1)* undef %ptr0 = load volatile i32 addrspace(5)*, i32 addrspace(5)* addrspace(1)* undef
%eq = icmp eq i32* %ptr0, %stack0 %eq = icmp eq i32 addrspace(5)* %ptr0, %stack0
%ext = zext i1 %eq to i32 %ext = zext i1 %eq to i32
store volatile i32 %ext, i32 addrspace(1)* %out store volatile i32 %ext, i32 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind readnone } attributes #0 = { nounwind readnone }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/AMDGPU/copy-to-reg.ll

; RUN: llc -march=amdgcn -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mattr=-promote-alloca -verify-machineinstrs < %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=-promote-alloca -verify-machineinstrs < %s
; Test that CopyToReg instructions don't have non-register operands prior ; Test that CopyToReg instructions don't have non-register operands prior
; to being emitted. ; to being emitted.
; Make sure this doesn't crash ; Make sure this doesn't crash
; CHECK-LABEL: {{^}}copy_to_reg_frameindex: ; CHECK-LABEL: {{^}}copy_to_reg_frameindex:
define amdgpu_kernel void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @copy_to_reg_frameindex(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
entry: entry:
%alloca = alloca [16 x i32] %alloca = alloca [16 x i32], addrspace(5)
br label %loop br label %loop
loop: loop:
%inc = phi i32 [0, %entry], [%inc.i, %loop] %inc = phi i32 [0, %entry], [%inc.i, %loop]
%ptr = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 %inc %ptr = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %inc
store i32 %inc, i32* %ptr store i32 %inc, i32 addrspace(5)* %ptr
%inc.i = add i32 %inc, 1 %inc.i = add i32 %inc, 1
%cnd = icmp uge i32 %inc.i, 16 %cnd = icmp uge i32 %inc.i, 16
br i1 %cnd, label %done, label %loop br i1 %cnd, label %done, label %loop
done: done:
%tmp0 = getelementptr [16 x i32], [16 x i32]* %alloca, i32 0, i32 0 %tmp0 = getelementptr [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
%tmp1 = load i32, i32* %tmp0 %tmp1 = load i32, i32 addrspace(5)* %tmp0
store i32 %tmp1, i32 addrspace(1)* %out store i32 %tmp1, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/extload-private.ll

; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
; FUNC-LABEL: {{^}}load_i8_sext_private: ; FUNC-LABEL: {{^}}load_i8_sext_private:
; SI: buffer_load_sbyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_sbyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i8_sext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i8_sext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i8 %tmp0 = alloca i8, addrspace(5)
%tmp1 = load i8, i8* %tmp0 %tmp1 = load i8, i8 addrspace(5)* %tmp0
%tmp2 = sext i8 %tmp1 to i32 %tmp2 = sext i8 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}load_i8_zext_private: ; FUNC-LABEL: {{^}}load_i8_zext_private:
; SI: buffer_load_ubyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_ubyte v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i8_zext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i8_zext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i8 %tmp0 = alloca i8, addrspace(5)
%tmp1 = load i8, i8* %tmp0 %tmp1 = load i8, i8 addrspace(5)* %tmp0
%tmp2 = zext i8 %tmp1 to i32 %tmp2 = zext i8 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}load_i16_sext_private: ; FUNC-LABEL: {{^}}load_i16_sext_private:
; SI: buffer_load_sshort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_sshort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i16_sext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i16_sext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i16 %tmp0 = alloca i16, addrspace(5)
%tmp1 = load i16, i16* %tmp0 %tmp1 = load i16, i16 addrspace(5)* %tmp0
%tmp2 = sext i16 %tmp1 to i32 %tmp2 = sext i16 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}load_i16_zext_private: ; FUNC-LABEL: {{^}}load_i16_zext_private:
; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; SI: buffer_load_ushort v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
define amdgpu_kernel void @load_i16_zext_private(i32 addrspace(1)* %out) { define amdgpu_kernel void @load_i16_zext_private(i32 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca i16 %tmp0 = alloca i16, addrspace(5)
%tmp1 = load volatile i16, i16* %tmp0 %tmp1 = load volatile i16, i16 addrspace(5)* %tmp0
%tmp2 = zext i16 %tmp1 to i32 %tmp2 = zext i16 %tmp1 to i32
store i32 %tmp2, i32 addrspace(1)* %out store i32 %tmp2, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/flat-address-space.ll

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; CHECK-DAG: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]], ; CHECK-DAG: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:[[HI_SREG:[0-9]+]]],
; CHECK-DAG: s_load_dword s[[SDATA:[0-9]+]], ; CHECK-DAG: s_load_dword s[[SDATA:[0-9]+]],
; CHECK: s_waitcnt lgkmcnt(0) ; CHECK: s_waitcnt lgkmcnt(0)
; CHECK-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]] ; CHECK-DAG: v_mov_b32_e32 v[[DATA:[0-9]+]], s[[SDATA]]
; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]] ; CHECK-DAG: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG]]
; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]] ; CHECK-DAG: v_mov_b32_e32 v[[HI_VREG:[0-9]+]], s[[HI_SREG]]
; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]] ; CHECK: flat_store_dword v{{\[}}[[LO_VREG]]:[[HI_VREG]]{{\]}}, v[[DATA]]
define amdgpu_kernel void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 { define amdgpu_kernel void @store_flat_i32(i32 addrspace(1)* %gptr, i32 %x) #0 {
%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(1)* %gptr to i32*
store volatile i32 %x, i32 addrspace(4)* %fptr, align 4 store volatile i32 %x, i32* %fptr, align 4
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i64: ; CHECK-LABEL: {{^}}store_flat_i64:
; CHECK: flat_store_dwordx2 ; CHECK: flat_store_dwordx2
define amdgpu_kernel void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 { define amdgpu_kernel void @store_flat_i64(i64 addrspace(1)* %gptr, i64 %x) #0 {
%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)* %fptr = addrspacecast i64 addrspace(1)* %gptr to i64*
store volatile i64 %x, i64 addrspace(4)* %fptr, align 8 store volatile i64 %x, i64* %fptr, align 8
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_v4i32: ; CHECK-LABEL: {{^}}store_flat_v4i32:
; CHECK: flat_store_dwordx4 ; CHECK: flat_store_dwordx4
define amdgpu_kernel void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 { define amdgpu_kernel void @store_flat_v4i32(<4 x i32> addrspace(1)* %gptr, <4 x i32> %x) #0 {
%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)* %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32>*
store volatile <4 x i32> %x, <4 x i32> addrspace(4)* %fptr, align 16 store volatile <4 x i32> %x, <4 x i32>* %fptr, align 16
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_trunc_i16: ; CHECK-LABEL: {{^}}store_flat_trunc_i16:
; CHECK: flat_store_short ; CHECK: flat_store_short
define amdgpu_kernel void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 { define amdgpu_kernel void @store_flat_trunc_i16(i16 addrspace(1)* %gptr, i32 %x) #0 {
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
%y = trunc i32 %x to i16 %y = trunc i32 %x to i16
store volatile i16 %y, i16 addrspace(4)* %fptr, align 2 store volatile i16 %y, i16* %fptr, align 2
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_trunc_i8: ; CHECK-LABEL: {{^}}store_flat_trunc_i8:
; CHECK: flat_store_byte ; CHECK: flat_store_byte
define amdgpu_kernel void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 { define amdgpu_kernel void @store_flat_trunc_i8(i8 addrspace(1)* %gptr, i32 %x) #0 {
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
%y = trunc i32 %x to i8 %y = trunc i32 %x to i8
store volatile i8 %y, i8 addrspace(4)* %fptr, align 2 store volatile i8 %y, i8* %fptr, align 2
ret void ret void
} }
; CHECK-LABEL: load_flat_i32: ; CHECK-LABEL: load_flat_i32:
; CHECK: flat_load_dword ; CHECK: flat_load_dword
define amdgpu_kernel void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @load_flat_i32(i32 addrspace(1)* noalias %out, i32 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i32 addrspace(1)* %gptr to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(1)* %gptr to i32*
%fload = load volatile i32, i32 addrspace(4)* %fptr, align 4 %fload = load volatile i32, i32* %fptr, align 4
store i32 %fload, i32 addrspace(1)* %out, align 4 store i32 %fload, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; CHECK-LABEL: load_flat_i64: ; CHECK-LABEL: load_flat_i64:
; CHECK: flat_load_dwordx2 ; CHECK: flat_load_dwordx2
define amdgpu_kernel void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @load_flat_i64(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i64 addrspace(1)* %gptr to i64 addrspace(4)* %fptr = addrspacecast i64 addrspace(1)* %gptr to i64*
%fload = load volatile i64, i64 addrspace(4)* %fptr, align 8 %fload = load volatile i64, i64* %fptr, align 8
store i64 %fload, i64 addrspace(1)* %out, align 8 store i64 %fload, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; CHECK-LABEL: load_flat_v4i32: ; CHECK-LABEL: load_flat_v4i32:
; CHECK: flat_load_dwordx4 ; CHECK: flat_load_dwordx4
define amdgpu_kernel void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @load_flat_v4i32(<4 x i32> addrspace(1)* noalias %out, <4 x i32> addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32> addrspace(4)* %fptr = addrspacecast <4 x i32> addrspace(1)* %gptr to <4 x i32>*
%fload = load volatile <4 x i32>, <4 x i32> addrspace(4)* %fptr, align 32 %fload = load volatile <4 x i32>, <4 x i32>* %fptr, align 32
store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8 store <4 x i32> %fload, <4 x i32> addrspace(1)* %out, align 8
ret void ret void
} }
; CHECK-LABEL: sextload_flat_i8: ; CHECK-LABEL: sextload_flat_i8:
; CHECK: flat_load_sbyte ; CHECK: flat_load_sbyte
define amdgpu_kernel void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @sextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
%fload = load volatile i8, i8 addrspace(4)* %fptr, align 4 %fload = load volatile i8, i8* %fptr, align 4
%ext = sext i8 %fload to i32 %ext = sext i8 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; CHECK-LABEL: zextload_flat_i8: ; CHECK-LABEL: zextload_flat_i8:
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
define amdgpu_kernel void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @zextload_flat_i8(i32 addrspace(1)* noalias %out, i8 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i8 addrspace(1)* %gptr to i8 addrspace(4)* %fptr = addrspacecast i8 addrspace(1)* %gptr to i8*
%fload = load volatile i8, i8 addrspace(4)* %fptr, align 4 %fload = load volatile i8, i8* %fptr, align 4
%ext = zext i8 %fload to i32 %ext = zext i8 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; CHECK-LABEL: sextload_flat_i16: ; CHECK-LABEL: sextload_flat_i16:
; CHECK: flat_load_sshort ; CHECK: flat_load_sshort
define amdgpu_kernel void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @sextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
%fload = load volatile i16, i16 addrspace(4)* %fptr, align 4 %fload = load volatile i16, i16* %fptr, align 4
%ext = sext i16 %fload to i32 %ext = sext i16 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; CHECK-LABEL: zextload_flat_i16: ; CHECK-LABEL: zextload_flat_i16:
; CHECK: flat_load_ushort ; CHECK: flat_load_ushort
define amdgpu_kernel void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 { define amdgpu_kernel void @zextload_flat_i16(i32 addrspace(1)* noalias %out, i16 addrspace(1)* noalias %gptr) #0 {
%fptr = addrspacecast i16 addrspace(1)* %gptr to i16 addrspace(4)* %fptr = addrspacecast i16 addrspace(1)* %gptr to i16*
%fload = load volatile i16, i16 addrspace(4)* %fptr, align 4 %fload = load volatile i16, i16* %fptr, align 4
%ext = zext i16 %fload to i32 %ext = zext i16 %fload to i32
store i32 %ext, i32 addrspace(1)* %out, align 4 store i32 %ext, i32 addrspace(1)* %out, align 4
ret void ret void
} }
; CHECK-LABEL: flat_scratch_unaligned_load: ; CHECK-LABEL: flat_scratch_unaligned_load:
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
; CHECK: flat_load_ubyte ; CHECK: flat_load_ubyte
define amdgpu_kernel void @flat_scratch_unaligned_load() { define amdgpu_kernel void @flat_scratch_unaligned_load() {
%scratch = alloca i32 %scratch = alloca i32, addrspace(5)
%fptr = addrspacecast i32* %scratch to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(5)* %scratch to i32*
%ld = load volatile i32, i32 addrspace(4)* %fptr, align 1 %ld = load volatile i32, i32* %fptr, align 1
ret void ret void
} }
; CHECK-LABEL: flat_scratch_unaligned_store: ; CHECK-LABEL: flat_scratch_unaligned_store:
; CHECK: flat_store_byte ; CHECK: flat_store_byte
; CHECK: flat_store_byte ; CHECK: flat_store_byte
; CHECK: flat_store_byte ; CHECK: flat_store_byte
; CHECK: flat_store_byte ; CHECK: flat_store_byte
define amdgpu_kernel void @flat_scratch_unaligned_store() { define amdgpu_kernel void @flat_scratch_unaligned_store() {
%scratch = alloca i32 %scratch = alloca i32, addrspace(5)
%fptr = addrspacecast i32* %scratch to i32 addrspace(4)* %fptr = addrspacecast i32 addrspace(5)* %scratch to i32*
store volatile i32 0, i32 addrspace(4)* %fptr, align 1 store volatile i32 0, i32* %fptr, align 1
ret void ret void
} }
; CHECK-LABEL: flat_scratch_multidword_load: ; CHECK-LABEL: flat_scratch_multidword_load:
; HSA: flat_load_dword ; HSA: flat_load_dword
; HSA: flat_load_dword ; HSA: flat_load_dword
; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr ; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
define amdgpu_kernel void @flat_scratch_multidword_load() { define amdgpu_kernel void @flat_scratch_multidword_load() {
%scratch = alloca <2 x i32> %scratch = alloca <2 x i32>, addrspace(5)
%fptr = addrspacecast <2 x i32>* %scratch to <2 x i32> addrspace(4)* %fptr = addrspacecast <2 x i32> addrspace(5)* %scratch to <2 x i32>*
%ld = load volatile <2 x i32>, <2 x i32> addrspace(4)* %fptr %ld = load volatile <2 x i32>, <2 x i32>* %fptr
ret void ret void
} }
; CHECK-LABEL: flat_scratch_multidword_store: ; CHECK-LABEL: flat_scratch_multidword_store:
; HSA: flat_store_dword ; HSA: flat_store_dword
; HSA: flat_store_dword ; HSA: flat_store_dword
; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr ; FIXME: These tests are broken for os = mesa3d, becasue it doesn't initialize flat_scr
define amdgpu_kernel void @flat_scratch_multidword_store() { define amdgpu_kernel void @flat_scratch_multidword_store() {
%scratch = alloca <2 x i32> %scratch = alloca <2 x i32>, addrspace(5)
%fptr = addrspacecast <2 x i32>* %scratch to <2 x i32> addrspace(4)* %fptr = addrspacecast <2 x i32> addrspace(5)* %scratch to <2 x i32>*
store volatile <2 x i32> zeroinitializer, <2 x i32> addrspace(4)* %fptr store volatile <2 x i32> zeroinitializer, <2 x i32>* %fptr
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i8_max_offset: ; CHECK-LABEL: {{^}}store_flat_i8_max_offset:
; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} ; CIVI: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}} ; GFX9: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset:4095{{$}}
define amdgpu_kernel void @store_flat_i8_max_offset(i8 addrspace(4)* %fptr, i8 %x) #0 { define amdgpu_kernel void @store_flat_i8_max_offset(i8* %fptr, i8 %x) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4095 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095
store volatile i8 %x, i8 addrspace(4)* %fptr.offset store volatile i8 %x, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i8_max_offset_p1: ; CHECK-LABEL: {{^}}store_flat_i8_max_offset_p1:
; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} ; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @store_flat_i8_max_offset_p1(i8 addrspace(4)* %fptr, i8 %x) #0 { define amdgpu_kernel void @store_flat_i8_max_offset_p1(i8* %fptr, i8 %x) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4096 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096
store volatile i8 %x, i8 addrspace(4)* %fptr.offset store volatile i8 %x, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}store_flat_i8_neg_offset: ; CHECK-LABEL: {{^}}store_flat_i8_neg_offset:
; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}} ; CHECK: flat_store_byte v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @store_flat_i8_neg_offset(i8 addrspace(4)* %fptr, i8 %x) #0 { define amdgpu_kernel void @store_flat_i8_neg_offset(i8* %fptr, i8 %x) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 -2 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
store volatile i8 %x, i8 addrspace(4)* %fptr.offset store volatile i8 %x, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_max_offset: ; CHECK-LABEL: {{^}}load_flat_i8_max_offset:
; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CIVI: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}}
; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}} ; GFX9: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}} offset:4095{{$}}
define amdgpu_kernel void @load_flat_i8_max_offset(i8 addrspace(4)* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_max_offset(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4095 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4095
%val = load volatile i8, i8 addrspace(4)* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1: ; CHECK-LABEL: {{^}}load_flat_i8_max_offset_p1:
; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8 addrspace(4)* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_max_offset_p1(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 4096 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 4096
%val = load volatile i8, i8 addrspace(4)* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
; CHECK-LABEL: {{^}}load_flat_i8_neg_offset: ; CHECK-LABEL: {{^}}load_flat_i8_neg_offset:
; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}} ; CHECK: flat_load_ubyte v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @load_flat_i8_neg_offset(i8 addrspace(4)* %fptr) #0 { define amdgpu_kernel void @load_flat_i8_neg_offset(i8* %fptr) #0 {
%fptr.offset = getelementptr inbounds i8, i8 addrspace(4)* %fptr, i64 -2 %fptr.offset = getelementptr inbounds i8, i8* %fptr, i64 -2
%val = load volatile i8, i8 addrspace(4)* %fptr.offset %val = load volatile i8, i8* %fptr.offset
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind convergent } attributes #1 = { nounwind convergent }

test/CodeGen/AMDGPU/flat-for-global-subtarget-feature.ll

Show All 32 Lines
; HSA-NODEFAULT: buffer_store_dword ; HSA-NODEFAULT: buffer_store_dword
; HSA-NOADDR64: flat_store_dword ; HSA-NOADDR64: flat_store_dword
; NOHSA-DEFAULT: buffer_store_dword ; NOHSA-DEFAULT: buffer_store_dword
; NOHSA-NODEFAULT: flat_store_dword ; NOHSA-NODEFAULT: flat_store_dword
; NOHSA-NOADDR64: flat_store_dword ; NOHSA-NOADDR64: flat_store_dword
define amdgpu_kernel void @test_addr64(i32 addrspace(1)* %out) { define amdgpu_kernel void @test_addr64(i32 addrspace(1)* %out) {
entry: entry:
%out.addr = alloca i32 addrspace(1)*, align 4 %out.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %out, i32 addrspace(1)** %out.addr, align 4 store i32 addrspace(1)* %out, i32 addrspace(1)* addrspace(5)* %out.addr, align 4
%ld0 = load i32 addrspace(1)*, i32 addrspace(1)** %out.addr, align 4 %ld0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %out.addr, align 4
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %ld0, i32 0 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %ld0, i32 0
store i32 1, i32 addrspace(1)* %arrayidx, align 4 store i32 1, i32 addrspace(1)* %arrayidx, align 4
%ld1 = load i32 addrspace(1)*, i32 addrspace(1)** %out.addr, align 4 %ld1 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %out.addr, align 4
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %ld1, i32 1 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(1)* %ld1, i32 1
store i32 2, i32 addrspace(1)* %arrayidx1, align 4 store i32 2, i32 addrspace(1)* %arrayidx1, align 4
ret void ret void
} }

test/CodeGen/AMDGPU/flat_atomics.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,CIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; GCN-LABEL: {{^}}atomic_add_i32_offset: ; GCN-LABEL: {{^}}atomic_add_i32_offset:
; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_add_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_max_offset: ; GCN-LABEL: {{^}}atomic_add_i32_max_offset:
; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CIVI: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:4092{{$}} ; GFX9: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:4092{{$}}
define amdgpu_kernel void @atomic_add_i32_max_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32_max_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 1023 %gep = getelementptr i32, i32* %out, i32 1023
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_max_offset_p1: ; GCN-LABEL: {{^}}atomic_add_i32_max_offset_p1:
; GCN: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; GCN: flat_atomic_add v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_add_i32_max_offset_p1(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32_max_offset_p1(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 1024 %gep = getelementptr i32, i32* %out, i32 1024
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_add_i32_ret_offset:
; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_add_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_add_i32_addr64_offset:
; CIVI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_add_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64_offset:
; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile add i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile add i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32: ; GCN-LABEL: {{^}}atomic_add_i32:
; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_add_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_add_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile add i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile add i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_ret: ; GCN-LABEL: {{^}}atomic_add_i32_ret:
; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_add_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile add i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile add i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_addr64: ; GCN-LABEL: {{^}}atomic_add_i32_addr64:
; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_add v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_add_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile add i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile add i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_add_i32_ret_addr64:
; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_add [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile add i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile add i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_offset: ; GCN-LABEL: {{^}}atomic_and_i32_offset:
; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_and_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_and_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_and_i32_ret_offset:
; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_and_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_and_i32_addr64_offset:
; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_and_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64_offset:
; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_and [[RET:v[0-9]]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile and i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile and i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32: ; GCN-LABEL: {{^}}atomic_and_i32:
; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_and_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_and_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile and i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile and i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_ret: ; GCN-LABEL: {{^}}atomic_and_i32_ret:
; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_and_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile and i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile and i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_addr64: ; GCN-LABEL: {{^}}atomic_and_i32_addr64:
; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_and v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_and_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile and i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile and i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_and_i32_ret_addr64:
; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_and [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile and i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile and i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_offset: ; GCN-LABEL: {{^}}atomic_sub_i32_offset:
; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_sub_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_sub_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_sub_i32_ret_offset:
; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_sub_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_sub_i32_addr64_offset:
; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_sub_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64_offset:
; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile sub i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile sub i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32: ; GCN-LABEL: {{^}}atomic_sub_i32:
; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_sub_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_sub_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile sub i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile sub i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_ret: ; GCN-LABEL: {{^}}atomic_sub_i32_ret:
; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_sub_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile sub i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile sub i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_addr64: ; GCN-LABEL: {{^}}atomic_sub_i32_addr64:
; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_sub v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_sub_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile sub i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile sub i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_sub_i32_ret_addr64:
; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_sub [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile sub i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile sub i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_offset: ; GCN-LABEL: {{^}}atomic_max_i32_offset:
; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_max_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_max_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_max_i32_ret_offset:
; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_max_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_max_i32_addr64_offset:
; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_max_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64_offset:
; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile max i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile max i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32: ; GCN-LABEL: {{^}}atomic_max_i32:
; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_max_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_max_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile max i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile max i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_ret: ; GCN-LABEL: {{^}}atomic_max_i32_ret:
; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_max_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile max i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile max i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_addr64: ; GCN-LABEL: {{^}}atomic_max_i32_addr64:
; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_max_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile max i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile max i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_max_i32_ret_addr64:
; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile max i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile max i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_offset: ; GCN-LABEL: {{^}}atomic_umax_i32_offset:
; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umax_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umax_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_umax_i32_ret_offset:
; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umax_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_umax_i32_addr64_offset:
; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umax_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64_offset:
; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umax i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umax i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32: ; GCN-LABEL: {{^}}atomic_umax_i32:
; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umax_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umax_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile umax i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umax i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_ret: ; GCN-LABEL: {{^}}atomic_umax_i32_ret:
; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umax_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile umax i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umax i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_addr64: ; GCN-LABEL: {{^}}atomic_umax_i32_addr64:
; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umax v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umax_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umax i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umax i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_umax_i32_ret_addr64:
; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umax [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umax i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umax i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_offset: ; GCN-LABEL: {{^}}atomic_min_i32_offset:
; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_min_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_min_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_min_i32_ret_offset:
; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_min_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_min_i32_addr64_offset:
; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_min_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64_offset:
; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile min i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile min i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32: ; GCN-LABEL: {{^}}atomic_min_i32:
; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_min_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_min_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile min i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile min i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_ret: ; GCN-LABEL: {{^}}atomic_min_i32_ret:
; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_min_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile min i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile min i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_addr64: ; GCN-LABEL: {{^}}atomic_min_i32_addr64:
; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_smin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_min_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile min i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile min i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_min_i32_ret_addr64:
; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_smin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile min i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile min i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_offset: ; GCN-LABEL: {{^}}atomic_umin_i32_offset:
; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umin_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umin_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_umin_i32_ret_offset:
; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umin_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_umin_i32_addr64_offset:
; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_umin_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64_offset:
; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile umin i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile umin i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32: ; GCN-LABEL: {{^}}atomic_umin_i32:
; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umin_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_umin_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile umin i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umin i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_ret: ; GCN-LABEL: {{^}}atomic_umin_i32_ret:
; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_umin_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile umin i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile umin i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_addr64: ; GCN-LABEL: {{^}}atomic_umin_i32_addr64:
; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_umin v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_umin_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umin i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umin i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_umin_i32_ret_addr64:
; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_umin [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]{{$}} ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]{{$}}
define amdgpu_kernel void @atomic_umin_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile umin i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile umin i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_offset: ; GCN-LABEL: {{^}}atomic_or_i32_offset:
; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_or_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_or_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_or_i32_ret_offset:
; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_or_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_or_i32_addr64_offset:
; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_or_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64_offset:
; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile or i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile or i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32: ; GCN-LABEL: {{^}}atomic_or_i32:
; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_or_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_or_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile or i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile or i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_ret: ; GCN-LABEL: {{^}}atomic_or_i32_ret:
; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_or_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile or i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile or i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_addr64: ; GCN-LABEL: {{^}}atomic_or_i32_addr64:
; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_or v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_or_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile or i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile or i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_or_i32_ret_addr64:
; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_or [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile or i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile or i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_offset: ; GCN-LABEL: {{^}}atomic_xchg_i32_offset:
; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xchg_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_xchg_i32_ret_offset:
; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i32_addr64_offset:
; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64_offset:
; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xchg i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32: ; GCN-LABEL: {{^}}atomic_xchg_i32:
; GCN: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; GCN: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_xchg_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_ret: ; GCN-LABEL: {{^}}atomic_xchg_i32_ret:
; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xchg_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i32_addr64:
; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_swap v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_xchg_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xchg i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i32_ret_addr64:
; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_swap [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xchg i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; CMP_SWAP ; CMP_SWAP
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_offset:
; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}} ; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32 addrspace(4)* %out, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_offset(i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_offset:
; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_offset(i32* %out, i32* %out2, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset:
; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CIVI: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}} ; GFX9: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] offset:16{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(i32* %out, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64_offset:
; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; CIVI: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32:
; GCN: flat_atomic_cmpswap v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32(i32 addrspace(4)* %out, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32(i32* %out, i32 %in, i32 %old) {
entry: entry:
%val = cmpxchg volatile i32 addrspace(4)* %out, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %out, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret:
; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc ; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}] glc
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret(i32* %out, i32* %out2, i32 %in, i32 %old) {
entry: entry:
%val = cmpxchg volatile i32 addrspace(4)* %out, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %out, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_addr64:
; GCN: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(i32* %out, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = cmpxchg volatile i32 addrspace(4)* %ptr, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %ptr, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i32_ret_addr64:
; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap v[[RET:[0-9]+]], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, v[[RET]]
define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index, i32 %old) { define amdgpu_kernel void @atomic_cmpxchg_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index, i32 %old) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = cmpxchg volatile i32 addrspace(4)* %ptr, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %ptr, i32 %old, i32 %in seq_cst seq_cst
%flag = extractvalue { i32, i1 } %val, 0 %flag = extractvalue { i32, i1 } %val, 0
store i32 %flag, i32 addrspace(4)* %out2 store i32 %flag, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_offset: ; GCN-LABEL: {{^}}atomic_xor_i32_offset:
; CIVI: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CIVI: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; GFX9: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xor_i32_offset(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xor_i32_offset(i32* %out, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_ret_offset: ; GCN-LABEL: {{^}}atomic_xor_i32_ret_offset:
; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xor_i32_ret_offset(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_xor_i32_addr64_offset:
; CIVI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; CIVI: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
; GFX9: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}} ; GFX9: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_xor_i32_addr64_offset(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_addr64_offset(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64_offset:
; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; CIVI: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}} ; GFX9: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret_addr64_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_ret_addr64_offset(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = atomicrmw volatile xor i32 addrspace(4)* %gep, i32 %in seq_cst %val = atomicrmw volatile xor i32* %gep, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32: ; GCN-LABEL: {{^}}atomic_xor_i32:
; GCN: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; GCN: flat_atomic_xor v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_xor_i32(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @atomic_xor_i32(i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xor i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xor i32* %out, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_ret: ; GCN-LABEL: {{^}}atomic_xor_i32_ret:
; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in) { define amdgpu_kernel void @atomic_xor_i32_ret(i32* %out, i32* %out2, i32 %in) {
entry: entry:
%val = atomicrmw volatile xor i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xor i32* %out, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_addr64: ; GCN-LABEL: {{^}}atomic_xor_i32_addr64:
; GCN: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}} ; GCN: flat_atomic_xor v[{{[0-9]+:[0-9]+}}], v{{[0-9]+$}}
define amdgpu_kernel void @atomic_xor_i32_addr64(i32 addrspace(4)* %out, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_addr64(i32* %out, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xor i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xor i32* %ptr, i32 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64: ; GCN-LABEL: {{^}}atomic_xor_i32_ret_addr64:
; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}} ; GCN: flat_atomic_xor [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}], v{{[0-9]+}} glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i32_ret_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %out2, i32 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i32_ret_addr64(i32* %out, i32* %out2, i32 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%val = atomicrmw volatile xor i32 addrspace(4)* %ptr, i32 %in seq_cst %val = atomicrmw volatile xor i32* %ptr, i32 %in seq_cst
store i32 %val, i32 addrspace(4)* %out2 store i32 %val, i32* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i32_offset: ; GCN-LABEL: {{^}}atomic_load_i32_offset:
; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i32_offset(i32* %in, i32* %out) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %in, i32 4 %gep = getelementptr i32, i32* %in, i32 4
%val = load atomic i32, i32 addrspace(4)* %gep seq_cst, align 4 %val = load atomic i32, i32* %gep seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i32: ; GCN-LABEL: {{^}}atomic_load_i32:
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32(i32 addrspace(4)* %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i32(i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in seq_cst, align 4 %val = load atomic i32, i32* %in seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_load_i32_addr64_offset:
; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; CIVI: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}} ; GFX9: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] offset:16 glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32_addr64_offset(i32 addrspace(4)* %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i32_addr64_offset(i32* %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %in, i64 %index %ptr = getelementptr i32, i32* %in, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%val = load atomic i32, i32 addrspace(4)* %gep seq_cst, align 4 %val = load atomic i32, i32* %gep seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i32_addr64: ; GCN-LABEL: {{^}}atomic_load_i32_addr64:
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i32_addr64(i32 addrspace(4)* %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i32_addr64(i32* %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %in, i64 %index %ptr = getelementptr i32, i32* %in, i64 %index
%val = load atomic i32, i32 addrspace(4)* %ptr seq_cst, align 4 %val = load atomic i32, i32* %ptr seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32_offset: ; GCN-LABEL: {{^}}atomic_store_i32_offset:
; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}} ; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, i32* %out) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
store atomic i32 %in, i32 addrspace(4)* %gep seq_cst, align 4 store atomic i32 %in, i32* %gep seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32: ; GCN-LABEL: {{^}}atomic_store_i32:
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_store_i32(i32 %in, i32 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i32(i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out seq_cst, align 4 store atomic i32 %in, i32* %out seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32_addr64_offset: ; GCN-LABEL: {{^}}atomic_store_i32_addr64_offset:
; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; CIVI: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}} ; GFX9: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}} offset:16{{$}}
define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
store atomic i32 %in, i32 addrspace(4)* %gep seq_cst, align 4 store atomic i32 %in, i32* %gep seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i32_addr64: ; GCN-LABEL: {{^}}atomic_store_i32_addr64:
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, i32 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, i32* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i32, i32 addrspace(4)* %out, i64 %index %ptr = getelementptr i32, i32* %out, i64 %index
store atomic i32 %in, i32 addrspace(4)* %ptr seq_cst, align 4 store atomic i32 %in, i32* %ptr seq_cst, align 4
ret void ret void
} }

test/CodeGen/AMDGPU/flat_atomics_i64.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; GCN-LABEL: {{^}}atomic_add_i64_offset: ; GCN-LABEL: {{^}}atomic_add_i64_offset:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @atomic_add_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_add_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_add_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}}
define amdgpu_kernel void @atomic_add_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64: ; GCN-LABEL: {{^}}atomic_add_i64:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_add_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_add_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret: ; GCN-LABEL: {{^}}atomic_add_i64_ret:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_add_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_addr64: ; GCN-LABEL: {{^}}atomic_add_i64_addr64:
; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_add_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64:
; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_add_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_add_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile add i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile add i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_offset: ; GCN-LABEL: {{^}}atomic_and_i64_offset:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_and_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_and_i64_ret_offset:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_and_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_and_i64_addr64_offset:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64_offset:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64: ; GCN-LABEL: {{^}}atomic_and_i64:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_and_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret: ; GCN-LABEL: {{^}}atomic_and_i64_ret:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_and_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_addr64: ; GCN-LABEL: {{^}}atomic_and_i64_addr64:
; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_and_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_and_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_and_i64_ret_addr64:
; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_and_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_and_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_and_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile and i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile and i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_offset:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_sub_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_ret_offset:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_sub_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_addr64_offset:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64_offset:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64: ; GCN-LABEL: {{^}}atomic_sub_i64:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_sub_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret: ; GCN-LABEL: {{^}}atomic_sub_i64_ret:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_sub_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_addr64: ; GCN-LABEL: {{^}}atomic_sub_i64_addr64:
; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_sub_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_sub_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_sub_i64_ret_addr64:
; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_sub_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_sub_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_sub_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile sub i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile sub i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_offset: ; GCN-LABEL: {{^}}atomic_max_i64_offset:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_max_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_max_i64_ret_offset:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_max_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_max_i64_addr64_offset:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64_offset:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64: ; GCN-LABEL: {{^}}atomic_max_i64:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_max_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret: ; GCN-LABEL: {{^}}atomic_max_i64_ret:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_max_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_addr64: ; GCN-LABEL: {{^}}atomic_max_i64_addr64:
; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_max_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_max_i64_ret_addr64:
; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_max_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_max_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile max i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile max i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_offset:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umax_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_ret_offset:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umax_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_addr64_offset:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64_offset:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64: ; GCN-LABEL: {{^}}atomic_umax_i64:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umax_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret: ; GCN-LABEL: {{^}}atomic_umax_i64_ret:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umax_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_addr64: ; GCN-LABEL: {{^}}atomic_umax_i64_addr64:
; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umax_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umax_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_umax_i64_ret_addr64:
; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umax_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umax_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umax_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umax i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umax i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_offset: ; GCN-LABEL: {{^}}atomic_min_i64_offset:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_min_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_min_i64_ret_offset:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_min_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_min_i64_addr64_offset:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64_offset:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64: ; GCN-LABEL: {{^}}atomic_min_i64:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_min_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret: ; GCN-LABEL: {{^}}atomic_min_i64_ret:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_min_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_addr64: ; GCN-LABEL: {{^}}atomic_min_i64_addr64:
; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_smin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_min_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_min_i64_ret_addr64:
; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_smin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_min_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_min_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile min i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile min i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_offset:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umin_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_ret_offset:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umin_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_addr64_offset:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64_offset:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64: ; GCN-LABEL: {{^}}atomic_umin_i64:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_umin_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret: ; GCN-LABEL: {{^}}atomic_umin_i64_ret:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_umin_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_addr64: ; GCN-LABEL: {{^}}atomic_umin_i64_addr64:
; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_umin_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_umin_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_umin_i64_ret_addr64:
; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_umin_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_umin_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_umin_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile umin i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile umin i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_offset: ; GCN-LABEL: {{^}}atomic_or_i64_offset:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_or_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_or_i64_ret_offset:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_or_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_or_i64_addr64_offset:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64_offset:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64: ; GCN-LABEL: {{^}}atomic_or_i64:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_or_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret: ; GCN-LABEL: {{^}}atomic_or_i64_ret:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_or_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_addr64: ; GCN-LABEL: {{^}}atomic_or_i64_addr64:
; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_or_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_or_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_or_i64_ret_addr64:
; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_or_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_or_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_or_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile or i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile or i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_offset:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret_offset:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_addr64_offset:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64_offset:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64: ; GCN-LABEL: {{^}}atomic_xchg_i64:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xchg_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i64_addr64:
; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_swap_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xchg_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_xchg_i64_ret_addr64:
; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_swap_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xchg_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xchg i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xchg i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_offset:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64_offset(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xor_i64_offset(i64* %out, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_ret_offset:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xor_i64_ret_offset(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_addr64_offset:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_addr64_offset(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64_offset:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %gep, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %gep, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64: ; GCN-LABEL: {{^}}atomic_xor_i64:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64(i64 addrspace(4)* %out, i64 %in) { define amdgpu_kernel void @atomic_xor_i64(i64* %out, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %out, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret: ; GCN-LABEL: {{^}}atomic_xor_i64_ret:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in) { define amdgpu_kernel void @atomic_xor_i64_ret(i64* %out, i64* %out2, i64 %in) {
entry: entry:
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %out, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %out, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_addr64: ; GCN-LABEL: {{^}}atomic_xor_i64_addr64:
; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}} ; GCN: flat_atomic_xor_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]$}}
define amdgpu_kernel void @atomic_xor_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_addr64(i64* %out, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %ptr, i64 %in seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_xor_i64_ret_addr64:
; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}} ; GCN: flat_atomic_xor_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_xor_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index) { define amdgpu_kernel void @atomic_xor_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%tmp0 = atomicrmw volatile xor i64 addrspace(4)* %ptr, i64 %in seq_cst %tmp0 = atomicrmw volatile xor i64* %ptr, i64 %in seq_cst
store i64 %tmp0, i64 addrspace(4)* %out2 store i64 %tmp0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64_offset: ; GCN-LABEL: {{^}}atomic_load_i64_offset:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64_offset(i64 addrspace(4)* %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i64_offset(i64* %in, i64* %out) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %in, i64 4 %gep = getelementptr i64, i64* %in, i64 4
%val = load atomic i64, i64 addrspace(4)* %gep seq_cst, align 8 %val = load atomic i64, i64* %gep seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64: ; GCN-LABEL: {{^}}atomic_load_i64:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}] glc
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64(i64 addrspace(4)* %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_load_i64(i64* %in, i64* %out) {
entry: entry:
%val = load atomic i64, i64 addrspace(4)* %in seq_cst, align 8 %val = load atomic i64, i64* %in seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_load_i64_addr64_offset:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64_addr64_offset(i64 addrspace(4)* %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i64_addr64_offset(i64* %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %in, i64 %index %ptr = getelementptr i64, i64* %in, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = load atomic i64, i64 addrspace(4)* %gep seq_cst, align 8 %val = load atomic i64, i64* %gep seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_load_i64_addr64: ; GCN-LABEL: {{^}}atomic_load_i64_addr64:
; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_load_dwordx2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @atomic_load_i64_addr64(i64 addrspace(4)* %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_load_i64_addr64(i64* %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %in, i64 %index %ptr = getelementptr i64, i64* %in, i64 %index
%val = load atomic i64, i64 addrspace(4)* %ptr seq_cst, align 8 %val = load atomic i64, i64* %ptr seq_cst, align 8
store i64 %val, i64 addrspace(4)* %out store i64 %val, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64_offset: ; GCN-LABEL: {{^}}atomic_store_i64_offset:
; GCN: flat_store_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_store_dwordx2 [[RET:v\[[0-9]+:[0-9]\]]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_store_i64_offset(i64 %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i64_offset(i64 %in, i64* %out) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
store atomic i64 %in, i64 addrspace(4)* %gep seq_cst, align 8 store atomic i64 %in, i64* %gep seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64: ; GCN-LABEL: {{^}}atomic_store_i64:
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, v[{{[0-9]+}}:{{[0-9]+}}] ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]\]}}, v[{{[0-9]+}}:{{[0-9]+}}]
define amdgpu_kernel void @atomic_store_i64(i64 %in, i64 addrspace(4)* %out) { define amdgpu_kernel void @atomic_store_i64(i64 %in, i64* %out) {
entry: entry:
store atomic i64 %in, i64 addrspace(4)* %out seq_cst, align 8 store atomic i64 %in, i64* %out seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_store_i64_addr64_offset:
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_store_i64_addr64_offset(i64 %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i64_addr64_offset(i64 %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
store atomic i64 %in, i64 addrspace(4)* %gep seq_cst, align 8 store atomic i64 %in, i64* %gep seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_store_i64_addr64: ; GCN-LABEL: {{^}}atomic_store_i64_addr64:
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_store_i64_addr64(i64 %in, i64 addrspace(4)* %out, i64 %index) { define amdgpu_kernel void @atomic_store_i64_addr64(i64 %in, i64* %out, i64 %index) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
store atomic i64 %in, i64 addrspace(4)* %ptr seq_cst, align 8 store atomic i64 %in, i64* %ptr seq_cst, align 8
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_offset:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_offset(i64 addrspace(4)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_offset(i64* %out, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_soffset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_soffset:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+}}:{{[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64 addrspace(4)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_soffset(i64* %out, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 9000 %gep = getelementptr i64, i64* %out, i64 9000
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_offset:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]{{:[0-9]+}}], v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_offset(i64* %out, i64* %out2, i64 %in, i64 %old) {
entry: entry:
%gep = getelementptr i64, i64 addrspace(4)* %out, i64 4 %gep = getelementptr i64, i64* %out, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64_offset:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64 addrspace(4)* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64_offset(i64* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64_offset:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64_offset(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i64 4 %gep = getelementptr i64, i64* %ptr, i64 4
%val = cmpxchg volatile i64 addrspace(4)* %gep, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %gep, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64(i64 addrspace(4)* %out, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64(i64* %out, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64 addrspace(4)* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret(i64* %out, i64* %out2, i64 %in, i64 %old) {
entry: entry:
%val = cmpxchg volatile i64 addrspace(4)* %out, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %out, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_addr64:
; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}} ; GCN: flat_atomic_cmpswap_x2 v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}]{{$}}
define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64 addrspace(4)* %out, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_addr64(i64* %out, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%val = cmpxchg volatile i64 addrspace(4)* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst
ret void ret void
} }
; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64: ; GCN-LABEL: {{^}}atomic_cmpxchg_i64_ret_addr64:
; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}} ; GCN: flat_atomic_cmpswap_x2 v{{\[}}[[RET:[0-9]+]]:{{[0-9]+\]}}, v[{{[0-9]+:[0-9]+}}], v[{{[0-9]+:[0-9]+}}] glc{{$}}
; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]: ; GCN: flat_store_dwordx2 {{v\[[0-9]+:[0-9]+\]}}, v{{\[}}[[RET]]:
define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %out2, i64 %in, i64 %index, i64 %old) { define amdgpu_kernel void @atomic_cmpxchg_i64_ret_addr64(i64* %out, i64* %out2, i64 %in, i64 %index, i64 %old) {
entry: entry:
%ptr = getelementptr i64, i64 addrspace(4)* %out, i64 %index %ptr = getelementptr i64, i64* %out, i64 %index
%val = cmpxchg volatile i64 addrspace(4)* %ptr, i64 %old, i64 %in seq_cst seq_cst %val = cmpxchg volatile i64* %ptr, i64 %old, i64 %in seq_cst seq_cst
%extract0 = extractvalue { i64, i1 } %val, 0 %extract0 = extractvalue { i64, i1 } %val, 0
store i64 %extract0, i64 addrspace(4)* %out2 store i64 %extract0, i64* %out2
ret void ret void
} }

test/CodeGen/AMDGPU/frame-index-elimination.ll

Show All 12 Lines
; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] ; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]]
; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]] ; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
; GCN-NOT: v_mov ; GCN-NOT: v_mov
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
define void @func_mov_fi_i32() #0 { define void @func_mov_fi_i32() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32* %alloca, i32* addrspace(3)* undef store volatile i32 addrspace(5)* %alloca, i32 addrspace(5)* addrspace(3)* undef
ret void ret void
} }
; Materialize into an add of a constant offset from the FI. ; Materialize into an add of a constant offset from the FI.
; FIXME: Should be able to merge adds ; FIXME: Should be able to merge adds
; GCN-LABEL: {{^}}func_add_constant_to_fi_i32: ; GCN-LABEL: {{^}}func_add_constant_to_fi_i32:
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN: s_sub_u32 s6, s5, s4 ; GCN: s_sub_u32 s6, s5, s4
; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 ; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] ; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]]
; CI-NEXT: v_add_i32_e32 v0, vcc, 4, v0 ; CI-NEXT: v_add_i32_e32 v0, vcc, 4, v0
; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]] ; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
; GFX9-NEXT: v_add_u32_e32 v0, 4, v0 ; GFX9-NEXT: v_add_u32_e32 v0, 4, v0
; GCN-NOT: v_mov ; GCN-NOT: v_mov
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
define void @func_add_constant_to_fi_i32() #0 { define void @func_add_constant_to_fi_i32() #0 {
%alloca = alloca [2 x i32], align 4 %alloca = alloca [2 x i32], align 4, addrspace(5)
%gep0 = getelementptr inbounds [2 x i32], [2 x i32]* %alloca, i32 0, i32 1 %gep0 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %alloca, i32 0, i32 1
store volatile i32* %gep0, i32* addrspace(3)* undef store volatile i32 addrspace(5)* %gep0, i32 addrspace(5)* addrspace(3)* undef
ret void ret void
} }
; A user the materialized frame index can't be meaningfully folded ; A user the materialized frame index can't be meaningfully folded
; into. ; into.
; GCN-LABEL: {{^}}func_other_fi_user_i32: ; GCN-LABEL: {{^}}func_other_fi_user_i32:
; GCN: s_sub_u32 s6, s5, s4 ; GCN: s_sub_u32 s6, s5, s4
; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 ; CI-NEXT: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]] ; CI-NEXT: v_add_i32_e64 v0, s[6:7], 4, [[SCALED]]
; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 ; GFX9-NEXT: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]] ; GFX9-NEXT: v_add_u32_e32 v0, 4, [[SCALED]]
; GCN-NEXT: v_mul_lo_i32 v0, v0, 9 ; GCN-NEXT: v_mul_lo_i32 v0, v0, 9
; GCN-NOT: v_mov ; GCN-NOT: v_mov
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
define void @func_other_fi_user_i32() #0 { define void @func_other_fi_user_i32() #0 {
%alloca = alloca [2 x i32], align 4 %alloca = alloca [2 x i32], align 4, addrspace(5)
%ptrtoint = ptrtoint [2 x i32]* %alloca to i32 %ptrtoint = ptrtoint [2 x i32] addrspace(5)* %alloca to i32
%mul = mul i32 %ptrtoint, 9 %mul = mul i32 %ptrtoint, 9
store volatile i32 %mul, i32 addrspace(3)* undef store volatile i32 %mul, i32 addrspace(3)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}func_store_private_arg_i32_ptr: ; GCN-LABEL: {{^}}func_store_private_arg_i32_ptr:
; GCN: v_mov_b32_e32 v1, 15{{$}} ; GCN: v_mov_b32_e32 v1, 15{{$}}
; GCN: buffer_store_dword v1, v0, s[0:3], s4 offen{{$}} ; GCN: buffer_store_dword v1, v0, s[0:3], s4 offen{{$}}
define void @func_store_private_arg_i32_ptr(i32* %ptr) #0 { define void @func_store_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 {
store volatile i32 15, i32* %ptr store volatile i32 15, i32 addrspace(5)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}func_load_private_arg_i32_ptr: ; GCN-LABEL: {{^}}func_load_private_arg_i32_ptr:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], s4 offen{{$}} ; GCN-NEXT: buffer_load_dword v0, v0, s[0:3], s4 offen{{$}}
define void @func_load_private_arg_i32_ptr(i32* %ptr) #0 { define void @func_load_private_arg_i32_ptr(i32 addrspace(5)* %ptr) #0 {
%val = load volatile i32, i32* %ptr %val = load volatile i32, i32 addrspace(5)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr: ; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-NEXT: s_mov_b32 s5, s32 ; GCN-NEXT: s_mov_b32 s5, s32
; GCN-NEXT: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4 ; GCN-NEXT: s_sub_u32 [[SUB_OFFSET:s[0-9]+]], s5, s4
; CI-NEXT: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6 ; CI-NEXT: v_lshr_b32_e64 [[SHIFT:v[0-9]+]], [[SUB_OFFSET]], 6
; CI-NEXT: v_add_i32_e64 [[ADD:v[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]] ; CI-NEXT: v_add_i32_e64 [[ADD:v[0-9]+]], {{s\[[0-9]+:[0-9]+\]}}, 4, [[SHIFT]]
; CI-NEXT: v_add_i32_e32 v0, vcc, 4, [[ADD]] ; CI-NEXT: v_add_i32_e32 v0, vcc, 4, [[ADD]]
; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]] ; GFX9-NEXT: v_lshrrev_b32_e64 [[SHIFT:v[0-9]+]], 6, [[SUB_OFFSET]]
; GFX9-NEXT: v_add_u32_e32 [[ADD:v[0-9]+]], 4, [[SHIFT]] ; GFX9-NEXT: v_add_u32_e32 [[ADD:v[0-9]+]], 4, [[SHIFT]]
; GFX9-NEXT: v_add_u32_e32 v0, 4, [[ADD]] ; GFX9-NEXT: v_add_u32_e32 v0, 4, [[ADD]]
; GCN-NOT: v_mov ; GCN-NOT: v_mov
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 }* byval %arg0) #0 { define void @void_func_byval_struct_i8_i32_ptr({ i8, i32 } addrspace(5)* byval %arg0) #0 {
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 0 %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 1 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1
%load1 = load i32, i32* %gep1 %load1 = load i32, i32 addrspace(5)* %gep1
store volatile i32* %gep1, i32* addrspace(3)* undef store volatile i32 addrspace(5)* %gep1, i32 addrspace(5)* addrspace(3)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_value: ; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_ptr_value:
; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-NEXT: s_mov_b32 s5, s32 ; GCN-NEXT: s_mov_b32 s5, s32
; GCN-NEXT: buffer_load_ubyte v0, off, s[0:3], s5 ; GCN-NEXT: buffer_load_ubyte v0, off, s[0:3], s5
; GCN_NEXT: buffer_load_dword v1, off, s[0:3], s5 offset:4 ; GCN_NEXT: buffer_load_dword v1, off, s[0:3], s5 offset:4
define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 }* byval %arg0) #0 { define void @void_func_byval_struct_i8_i32_ptr_value({ i8, i32 } addrspace(5)* byval %arg0) #0 {
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 0 %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 1 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1
%load0 = load i8, i8* %gep0 %load0 = load i8, i8 addrspace(5)* %gep0
%load1 = load i32, i32* %gep1 %load1 = load i32, i32 addrspace(5)* %gep1
store volatile i8 %load0, i8 addrspace(3)* undef store volatile i8 %load0, i8 addrspace(3)* undef
store volatile i32 %load1, i32 addrspace(3)* undef store volatile i32 %load1, i32 addrspace(3)* undef
ret void ret void
} }
; FIXME: Should be able to see that this can use vaddr, but the ; FIXME: Should be able to see that this can use vaddr, but the
; FrameIndex is hidden behind a CopyFromReg in the second block. ; FrameIndex is hidden behind a CopyFromReg in the second block.
Show All 10 Lines
; CI: v_add_i32_e32 v0, vcc, 4, [[ADD]] ; CI: v_add_i32_e32 v0, vcc, 4, [[ADD]]
; CI: buffer_load_dword v1, v0, s[0:3], s4 offen{{$}} ; CI: buffer_load_dword v1, v0, s[0:3], s4 offen{{$}}
; GFX9: v_add_u32_e32 v0, 4, [[ADD]] ; GFX9: v_add_u32_e32 v0, 4, [[ADD]]
; GFX9: buffer_load_dword v1, v{{[0-9]+}}, s[0:3], s4 offen offset:4{{$}} ; GFX9: buffer_load_dword v1, v{{[0-9]+}}, s[0:3], s4 offen offset:4{{$}}
; GCN: ds_write_b32 ; GCN: ds_write_b32
define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 }* byval %arg0, i32 %arg2) #0 { define void @void_func_byval_struct_i8_i32_ptr_nonentry_block({ i8, i32 } addrspace(5)* byval %arg0, i32 %arg2) #0 {
%cmp = icmp eq i32 %arg2, 0 %cmp = icmp eq i32 %arg2, 0
br i1 %cmp, label %bb, label %ret br i1 %cmp, label %bb, label %ret
bb: bb:
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 0 %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %arg0, i32 0, i32 1 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %arg0, i32 0, i32 1
%load1 = load volatile i32, i32* %gep1 %load1 = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32* %gep1, i32* addrspace(3)* undef store volatile i32 addrspace(5)* %gep1, i32 addrspace(5)* addrspace(3)* undef
br label %ret br label %ret
ret: ret:
ret void ret void
} }
; Added offset can't be used with VOP3 add ; Added offset can't be used with VOP3 add
; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32: ; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32:
; GCN: s_sub_u32 s6, s5, s4 ; GCN: s_sub_u32 s6, s5, s4
; GCN-DAG: s_movk_i32 s6, 0x204 ; GCN-DAG: s_movk_i32 s6, 0x204
; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6 ; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], s6, 6
; CI: v_add_i32_e64 v0, s[6:7], s6, [[SCALED]] ; CI: v_add_i32_e64 v0, s[6:7], s6, [[SCALED]]
; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6 ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, s6
; GFX9: v_add_u32_e32 v0, s6, [[SCALED]] ; GFX9: v_add_u32_e32 v0, s6, [[SCALED]]
; GCN: v_mul_lo_i32 v0, v0, 9 ; GCN: v_mul_lo_i32 v0, v0, 9
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
define void @func_other_fi_user_non_inline_imm_offset_i32() #0 { define void @func_other_fi_user_non_inline_imm_offset_i32() #0 {
%alloca0 = alloca [128 x i32], align 4 %alloca0 = alloca [128 x i32], align 4, addrspace(5)
%alloca1 = alloca [8 x i32], align 4 %alloca1 = alloca [8 x i32], align 4, addrspace(5)
%gep0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca0, i32 0, i32 65 %gep0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca0, i32 0, i32 65
%gep1 = getelementptr inbounds [8 x i32], [8 x i32]* %alloca1, i32 0, i32 0 %gep1 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %alloca1, i32 0, i32 0
store volatile i32 7, i32* %gep0 store volatile i32 7, i32 addrspace(5)* %gep0
%ptrtoint = ptrtoint i32* %gep1 to i32 %ptrtoint = ptrtoint i32 addrspace(5)* %gep1 to i32
%mul = mul i32 %ptrtoint, 9 %mul = mul i32 %ptrtoint, 9
store volatile i32 %mul, i32 addrspace(3)* undef store volatile i32 %mul, i32 addrspace(3)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32_vcc_live: ; GCN-LABEL: {{^}}func_other_fi_user_non_inline_imm_offset_i32_vcc_live:
; GCN: s_sub_u32 [[DIFF:s[0-9]+]], s5, s4 ; GCN: s_sub_u32 [[DIFF:s[0-9]+]], s5, s4
; GCN-DAG: s_movk_i32 [[OFFSET:s[0-9]+]], 0x204 ; GCN-DAG: s_movk_i32 [[OFFSET:s[0-9]+]], 0x204
; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[DIFF]], 6 ; CI-DAG: v_lshr_b32_e64 [[SCALED:v[0-9]+]], [[DIFF]], 6
; CI: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]] ; CI: v_add_i32_e64 v0, s{{\[[0-9]+:[0-9]+\]}}, [[OFFSET]], [[SCALED]]
; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]] ; GFX9-DAG: v_lshrrev_b32_e64 [[SCALED:v[0-9]+]], 6, [[DIFF]]
; GFX9: v_add_u32_e32 v0, [[OFFSET]], [[SCALED]] ; GFX9: v_add_u32_e32 v0, [[OFFSET]], [[SCALED]]
; GCN: v_mul_lo_i32 v0, v0, 9 ; GCN: v_mul_lo_i32 v0, v0, 9
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 { define void @func_other_fi_user_non_inline_imm_offset_i32_vcc_live() #0 {
%alloca0 = alloca [128 x i32], align 4 %alloca0 = alloca [128 x i32], align 4, addrspace(5)
%alloca1 = alloca [8 x i32], align 4 %alloca1 = alloca [8 x i32], align 4, addrspace(5)
%vcc = call i64 asm sideeffect "; def $0", "={VCC}"() %vcc = call i64 asm sideeffect "; def $0", "={VCC}"()
%gep0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca0, i32 0, i32 65 %gep0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca0, i32 0, i32 65
%gep1 = getelementptr inbounds [8 x i32], [8 x i32]* %alloca1, i32 0, i32 0 %gep1 = getelementptr inbounds [8 x i32], [8 x i32] addrspace(5)* %alloca1, i32 0, i32 0
store volatile i32 7, i32* %gep0 store volatile i32 7, i32 addrspace(5)* %gep0
call void asm sideeffect "; use $0", "{VCC}"(i64 %vcc) call void asm sideeffect "; use $0", "{VCC}"(i64 %vcc)
%ptrtoint = ptrtoint i32* %gep1 to i32 %ptrtoint = ptrtoint i32 addrspace(5)* %gep1 to i32
%mul = mul i32 %ptrtoint, 9 %mul = mul i32 %ptrtoint, 9
store volatile i32 %mul, i32 addrspace(3)* undef store volatile i32 %mul, i32 addrspace(3)* undef
ret void ret void
} }
declare void @func(<4 x float>* nocapture) #0 declare void @func(<4 x float> addrspace(5)* nocapture) #0
; undef flag not preserved in eliminateFrameIndex when handling the ; undef flag not preserved in eliminateFrameIndex when handling the
; stores in the middle block. ; stores in the middle block.
; GCN-LABEL: {{^}}undefined_stack_store_reg: ; GCN-LABEL: {{^}}undefined_stack_store_reg:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_store_dword v0, off, s[0:3], s5 offset: ; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
; GCN: buffer_store_dword v0, off, s[0:3], s5 offset: ; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
; GCN: buffer_store_dword v0, off, s[0:3], s5 offset: ; GCN: buffer_store_dword v0, off, s[0:3], s5 offset:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset: ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset:
define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 { define void @undefined_stack_store_reg(float %arg, i32 %arg1) #0 {
bb: bb:
%tmp = alloca <4 x float>, align 16 %tmp = alloca <4 x float>, align 16, addrspace(5)
%tmp2 = insertelement <4 x float> undef, float %arg, i32 0 %tmp2 = insertelement <4 x float> undef, float %arg, i32 0
store <4 x float> %tmp2, <4 x float>* undef store <4 x float> %tmp2, <4 x float> addrspace(5)* undef
%tmp3 = icmp eq i32 %arg1, 0 %tmp3 = icmp eq i32 %arg1, 0
br i1 %tmp3, label %bb4, label %bb5 br i1 %tmp3, label %bb4, label %bb5
bb4: bb4:
call void @func(<4 x float>* nonnull undef) call void @func(<4 x float> addrspace(5)* nonnull undef)
store <4 x float> %tmp2, <4 x float>* %tmp, align 16 store <4 x float> %tmp2, <4 x float> addrspace(5)* %tmp, align 16
call void @func(<4 x float>* nonnull %tmp) call void @func(<4 x float> addrspace(5)* nonnull %tmp)
br label %bb5 br label %bb5
bb5: bb5:
ret void ret void
} }
; GCN-LABEL: {{^}}alloca_ptr_nonentry_block: ; GCN-LABEL: {{^}}alloca_ptr_nonentry_block:
; GCN: s_and_saveexec_b64 ; GCN: s_and_saveexec_b64
; GCN: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s5 offset:12 ; GCN: buffer_load_dword v{{[0-9]+}}, off, s[0:3], s5 offset:12
define void @alloca_ptr_nonentry_block(i32 %arg0) #0 { define void @alloca_ptr_nonentry_block(i32 %arg0) #0 {
%alloca0 = alloca { i8, i32 }, align 4 %alloca0 = alloca { i8, i32 }, align 4, addrspace(5)
%cmp = icmp eq i32 %arg0, 0 %cmp = icmp eq i32 %arg0, 0
br i1 %cmp, label %bb, label %ret br i1 %cmp, label %bb, label %ret
bb: bb:
%gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %alloca0, i32 0, i32 0 %gep0 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %alloca0, i32 0, i32 0
%gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 }* %alloca0, i32 0, i32 1 %gep1 = getelementptr inbounds { i8, i32 }, { i8, i32 } addrspace(5)* %alloca0, i32 0, i32 1
%load1 = load volatile i32, i32* %gep1 %load1 = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32* %gep1, i32* addrspace(3)* undef store volatile i32 addrspace(5)* %gep1, i32 addrspace(5)* addrspace(3)* undef
br label %ret br label %ret
ret: ret:
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/function-args.ll

Show First 20 Lines • Show All 500 Lines • ▼ Show 20 Linesdefine void @void_func_struct_i8_i32({ i8, i32 } %arg0) #0 {
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32: ; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32:
; GCN-DAG: buffer_load_ubyte v[[ELT0:[0-9]+]], off, s[0:3], s5 offset:4{{$}} ; GCN-DAG: buffer_load_ubyte v[[ELT0:[0-9]+]], off, s[0:3], s5 offset:4{{$}}
; GCN-DAG: buffer_load_dword v[[ELT1:[0-9]+]], off, s[0:3], s5 offset:8{{$}} ; GCN-DAG: buffer_load_dword v[[ELT1:[0-9]+]], off, s[0:3], s5 offset:8{{$}}
; GCN-DAG: buffer_store_dword v[[ELT1]] ; GCN-DAG: buffer_store_dword v[[ELT1]]
; GCN-DAG: buffer_store_byte v[[ELT0]] ; GCN-DAG: buffer_store_byte v[[ELT0]]
define void @void_func_byval_struct_i8_i32({ i8, i32 }* byval %arg0) #0 { define void @void_func_byval_struct_i8_i32({ i8, i32 } addrspace(5)* byval %arg0) #0 {
%arg0.load = load { i8, i32 }, { i8, i32 }* %arg0 %arg0.load = load { i8, i32 }, { i8, i32 } addrspace(5)* %arg0
store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef store { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_x2: ; GCN-LABEL: {{^}}void_func_byval_struct_i8_i32_x2:
; GCN: buffer_load_ubyte v[[ELT0_0:[0-9]+]], off, s[0:3], s5 offset:4{{$}} ; GCN: buffer_load_ubyte v[[ELT0_0:[0-9]+]], off, s[0:3], s5 offset:4{{$}}
; GCN: buffer_load_dword v[[ELT1_0:[0-9]+]], off, s[0:3], s5 offset:8{{$}} ; GCN: buffer_load_dword v[[ELT1_0:[0-9]+]], off, s[0:3], s5 offset:8{{$}}
; GCN: buffer_load_ubyte v[[ELT0_1:[0-9]+]], off, s[0:3], s5 offset:12{{$}} ; GCN: buffer_load_ubyte v[[ELT0_1:[0-9]+]], off, s[0:3], s5 offset:12{{$}}
; GCN: buffer_load_dword v[[ELT1_1:[0-9]+]], off, s[0:3], s5 offset:16{{$}} ; GCN: buffer_load_dword v[[ELT1_1:[0-9]+]], off, s[0:3], s5 offset:16{{$}}
; GCN: ds_write_b32 v0, v0 ; GCN: ds_write_b32 v0, v0
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @void_func_byval_struct_i8_i32_x2({ i8, i32 }* byval %arg0, { i8, i32 }* byval %arg1, i32 %arg2) #0 { define void @void_func_byval_struct_i8_i32_x2({ i8, i32 } addrspace(5)* byval %arg0, { i8, i32 } addrspace(5)* byval %arg1, i32 %arg2) #0 {
%arg0.load = load volatile { i8, i32 }, { i8, i32 }* %arg0 %arg0.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg0
%arg1.load = load volatile { i8, i32 }, { i8, i32 }* %arg1 %arg1.load = load volatile { i8, i32 }, { i8, i32 } addrspace(5)* %arg1
store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef store volatile { i8, i32 } %arg0.load, { i8, i32 } addrspace(1)* undef
store volatile { i8, i32 } %arg1.load, { i8, i32 } addrspace(1)* undef store volatile { i8, i32 } %arg1.load, { i8, i32 } addrspace(1)* undef
store volatile i32 %arg2, i32 addrspace(3)* undef store volatile i32 %arg2, i32 addrspace(3)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_byval_i32_byval_i64: ; GCN-LABEL: {{^}}void_func_byval_i32_byval_i64:
; GCN-DAG: buffer_load_dword v[[ARG0_LOAD:[0-9]+]], off, s[0:3], s5 offset:4{{$}} ; GCN-DAG: buffer_load_dword v[[ARG0_LOAD:[0-9]+]], off, s[0:3], s5 offset:4{{$}}
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD0:[0-9]+]], off, s[0:3], s5 offset:8{{$}} ; GCN-DAG: buffer_load_dword v[[ARG1_LOAD0:[0-9]+]], off, s[0:3], s5 offset:8{{$}}
; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s5 offset:12{{$}} ; GCN-DAG: buffer_load_dword v[[ARG1_LOAD1:[0-9]+]], off, s[0:3], s5 offset:12{{$}}
; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off ; GCN-DAG: buffer_store_dword v[[ARG0_LOAD]], off
; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off ; GCN-DAG: buffer_store_dwordx2 v{{\[}}[[ARG1_LOAD0]]:[[ARG1_LOAD1]]{{\]}}, off
define void @void_func_byval_i32_byval_i64(i32* byval %arg0, i64* byval %arg1) #0 { define void @void_func_byval_i32_byval_i64(i32 addrspace(5)* byval %arg0, i64 addrspace(5)* byval %arg1) #0 {
%arg0.load = load i32, i32* %arg0 %arg0.load = load i32, i32 addrspace(5)* %arg0
%arg1.load = load i64, i64* %arg1 %arg1.load = load i64, i64 addrspace(5)* %arg1
store i32 %arg0.load, i32 addrspace(1)* undef store i32 %arg0.load, i32 addrspace(1)* undef
store i64 %arg1.load, i64 addrspace(1)* undef store i64 %arg1.load, i64 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}void_func_v32i32_i32_i64: ; GCN-LABEL: {{^}}void_func_v32i32_i32_i64:
; GCN-DAG: buffer_store_dwordx4 v[0:3], off ; GCN-DAG: buffer_store_dwordx4 v[0:3], off
; GCN-DAG: buffer_store_dwordx4 v[4:7], off ; GCN-DAG: buffer_store_dwordx4 v[4:7], off
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test/CodeGen/AMDGPU/hsa-metadata-from-llvm-ir-full.ll

Show First 20 Lines • Show All 270 Lines • ▼ Show 20 Lines
} }
; CHECK: - Name: test_pointer ; CHECK: - Name: test_pointer
; CHECK-NEXT: SymbolName: 'test_pointer@kd' ; CHECK-NEXT: SymbolName: 'test_pointer@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - Name: a ; CHECK-NEXT: - Name: a
; CHECK-NEXT: TypeName: 'int *' ; CHECK-NEXT: TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
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; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @test_struct(%struct.A* byval %a) define amdgpu_kernel void @test_struct(%struct.A addrspace(5)* byval %a)
!kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !20 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !20
!kernel_arg_base_type !20 !kernel_arg_type_qual !4 { !kernel_arg_base_type !20 !kernel_arg_type_qual !4 {
ret void ret void
} }
; CHECK: - Name: test_i128 ; CHECK: - Name: test_i128
; CHECK-NEXT: SymbolName: 'test_i128@kd' ; CHECK-NEXT: SymbolName: 'test_i128@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
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} }
; CHECK: - Name: test_addr_space ; CHECK: - Name: test_addr_space
; CHECK-NEXT: SymbolName: 'test_addr_space@kd' ; CHECK-NEXT: SymbolName: 'test_addr_space@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - Name: g ; CHECK-NEXT: - Name: g
; CHECK-NEXT: TypeName: 'int *' ; CHECK-NEXT: TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: c ; CHECK-NEXT: - Name: c
; CHECK-NEXT: TypeName: 'int *' ; CHECK-NEXT: TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Constant ; CHECK-NEXT: AddrSpaceQual: Constant
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: l ; CHECK-NEXT: - Name: l
; CHECK-NEXT: TypeName: 'int *' ; CHECK-NEXT: TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: PointeeAlign: 4 ; CHECK-NEXT: PointeeAlign: 4
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
Show All 22 Lines
} }
; CHECK: - Name: test_type_qual ; CHECK: - Name: test_type_qual
; CHECK-NEXT: SymbolName: 'test_type_qual@kd' ; CHECK-NEXT: SymbolName: 'test_type_qual@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - Name: a ; CHECK-NEXT: - Name: a
; CHECK-NEXT: TypeName: 'int *' ; CHECK-NEXT: TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: IsVolatile: true ; CHECK-NEXT: IsVolatile: true
; CHECK-NEXT: - Name: b ; CHECK-NEXT: - Name: b
; CHECK-NEXT: TypeName: 'int *' ; CHECK-NEXT: TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: IsConst: true ; CHECK-NEXT: IsConst: true
; CHECK-NEXT: IsRestrict: true ; CHECK-NEXT: IsRestrict: true
; CHECK-NEXT: - Name: c ; CHECK-NEXT: - Name: c
; CHECK-NEXT: TypeName: 'int *' ; CHECK-NEXT: TypeName: 'int addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: Pipe ; CHECK-NEXT: ValueKind: Pipe
; CHECK-NEXT: ValueType: Struct ; CHECK-NEXT: ValueType: Struct
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: IsPipe: true ; CHECK-NEXT: IsPipe: true
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
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} }
; CHECK: - Name: test_arg_ptr_to_ptr ; CHECK: - Name: test_arg_ptr_to_ptr
; CHECK-NEXT: SymbolName: 'test_arg_ptr_to_ptr@kd' ; CHECK-NEXT: SymbolName: 'test_arg_ptr_to_ptr@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - Name: a ; CHECK-NEXT: - Name: a
; CHECK-NEXT: TypeName: 'int **' ; CHECK-NEXT: TypeName: 'int addrspace(5)* addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenGlobalOffsetX ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetX
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenGlobalOffsetY ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetY
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @test_arg_ptr_to_ptr(i32* addrspace(1)* %a) define amdgpu_kernel void @test_arg_ptr_to_ptr(i32 addrspace(5)* addrspace(1)* %a)
!kernel_arg_addr_space !81 !kernel_arg_access_qual !2 !kernel_arg_type !80 !kernel_arg_addr_space !81 !kernel_arg_access_qual !2 !kernel_arg_type !80
!kernel_arg_base_type !80 !kernel_arg_type_qual !4 { !kernel_arg_base_type !80 !kernel_arg_type_qual !4 {
ret void ret void
} }
; CHECK: - Name: test_arg_struct_contains_ptr ; CHECK: - Name: test_arg_struct_contains_ptr
; CHECK-NEXT: SymbolName: 'test_arg_struct_contains_ptr@kd' ; CHECK-NEXT: SymbolName: 'test_arg_struct_contains_ptr@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
Show All 19 Lines
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @test_arg_struct_contains_ptr(%struct.B* byval %a) define amdgpu_kernel void @test_arg_struct_contains_ptr(%struct.B addrspace(5)* byval %a)
!kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !82 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !82
!kernel_arg_base_type !82 !kernel_arg_type_qual !4 { !kernel_arg_base_type !82 !kernel_arg_type_qual !4 {
ret void ret void
} }
; CHECK: - Name: test_arg_vector_of_ptr ; CHECK: - Name: test_arg_vector_of_ptr
; CHECK-NEXT: SymbolName: 'test_arg_vector_of_ptr@kd' ; CHECK-NEXT: SymbolName: 'test_arg_vector_of_ptr@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - Name: a ; CHECK-NEXT: - Name: a
; CHECK-NEXT: TypeName: 'global int* __attribute__((ext_vector_type(2)))' ; CHECK-NEXT: TypeName: 'global int addrspace(5)* __attribute__((ext_vector_type(2)))'
; CHECK-NEXT: Size: 16 ; CHECK-NEXT: Size: 16
; CHECK-NEXT: Align: 16 ; CHECK-NEXT: Align: 16
; CHECK-NEXT: ValueKind: ByValue ; CHECK-NEXT: ValueKind: ByValue
; CHECK-NEXT: ValueType: I32 ; CHECK-NEXT: ValueType: I32
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenGlobalOffsetX ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetX
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} }
; CHECK: - Name: test_pointee_align ; CHECK: - Name: test_pointee_align
; CHECK-NEXT: SymbolName: 'test_pointee_align@kd' ; CHECK-NEXT: SymbolName: 'test_pointee_align@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
; CHECK-NEXT: LanguageVersion: [ 2, 0 ] ; CHECK-NEXT: LanguageVersion: [ 2, 0 ]
; CHECK-NEXT: Args: ; CHECK-NEXT: Args:
; CHECK-NEXT: - Name: a ; CHECK-NEXT: - Name: a
; CHECK-NEXT: TypeName: 'long *' ; CHECK-NEXT: TypeName: 'long addrspace(5)*'
; CHECK-NEXT: Size: 8 ; CHECK-NEXT: Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: GlobalBuffer ; CHECK-NEXT: ValueKind: GlobalBuffer
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: b ; CHECK-NEXT: - Name: b
; CHECK-NEXT: TypeName: 'char *' ; CHECK-NEXT: TypeName: 'char addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: PointeeAlign: 1 ; CHECK-NEXT: PointeeAlign: 1
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: c ; CHECK-NEXT: - Name: c
; CHECK-NEXT: TypeName: 'char2 *' ; CHECK-NEXT: TypeName: 'char2 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: PointeeAlign: 2 ; CHECK-NEXT: PointeeAlign: 2
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: d ; CHECK-NEXT: - Name: d
; CHECK-NEXT: TypeName: 'char3 *' ; CHECK-NEXT: TypeName: 'char3 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: PointeeAlign: 4 ; CHECK-NEXT: PointeeAlign: 4
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: e ; CHECK-NEXT: - Name: e
; CHECK-NEXT: TypeName: 'char4 *' ; CHECK-NEXT: TypeName: 'char4 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: PointeeAlign: 4 ; CHECK-NEXT: PointeeAlign: 4
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: f ; CHECK-NEXT: - Name: f
; CHECK-NEXT: TypeName: 'char8 *' ; CHECK-NEXT: TypeName: 'char8 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: PointeeAlign: 8 ; CHECK-NEXT: PointeeAlign: 8
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Name: g ; CHECK-NEXT: - Name: g
; CHECK-NEXT: TypeName: 'char16 *' ; CHECK-NEXT: TypeName: 'char16 addrspace(5)*'
; CHECK-NEXT: Size: 4 ; CHECK-NEXT: Size: 4
; CHECK-NEXT: Align: 4 ; CHECK-NEXT: Align: 4
; CHECK-NEXT: ValueKind: DynamicSharedPointer ; CHECK-NEXT: ValueKind: DynamicSharedPointer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: PointeeAlign: 16 ; CHECK-NEXT: PointeeAlign: 16
; CHECK-NEXT: AddrSpaceQual: Local ; CHECK-NEXT: AddrSpaceQual: Local
; CHECK-NEXT: AccQual: Default ; CHECK-NEXT: AccQual: Default
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
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; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ ; CHECK-NEXT: ValueKind: HiddenGlobalOffsetZ
; CHECK-NEXT: ValueType: I64 ; CHECK-NEXT: ValueType: I64
; CHECK-NEXT: - Size: 8 ; CHECK-NEXT: - Size: 8
; CHECK-NEXT: Align: 8 ; CHECK-NEXT: Align: 8
; CHECK-NEXT: ValueKind: HiddenPrintfBuffer ; CHECK-NEXT: ValueKind: HiddenPrintfBuffer
; CHECK-NEXT: ValueType: I8 ; CHECK-NEXT: ValueType: I8
; CHECK-NEXT: AddrSpaceQual: Global ; CHECK-NEXT: AddrSpaceQual: Global
define amdgpu_kernel void @__test_block_invoke_kernel( define amdgpu_kernel void @__test_block_invoke_kernel(
<{ i32, i32, i8 addrspace(4)*, i8 addrspace(1)*, i8 }> %arg) #0 <{ i32, i32, i8*, i8 addrspace(1)*, i8 }> %arg) #0
!kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !110 !kernel_arg_addr_space !1 !kernel_arg_access_qual !2 !kernel_arg_type !110
!kernel_arg_base_type !110 !kernel_arg_type_qual !4 { !kernel_arg_base_type !110 !kernel_arg_type_qual !4 {
ret void ret void
} }
; CHECK: - Name: test_enqueue_kernel_caller ; CHECK: - Name: test_enqueue_kernel_caller
; CHECK-NEXT: SymbolName: 'test_enqueue_kernel_caller@kd' ; CHECK-NEXT: SymbolName: 'test_enqueue_kernel_caller@kd'
; CHECK-NEXT: Language: OpenCL C ; CHECK-NEXT: Language: OpenCL C
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!8 = !{i32 8, i32 16, i32 32} !8 = !{i32 8, i32 16, i32 32}
!9 = !{!"char"} !9 = !{!"char"}
!10 = !{!"ushort2"} !10 = !{!"ushort2"}
!11 = !{!"int3"} !11 = !{!"int3"}
!12 = !{!"ulong4"} !12 = !{!"ulong4"}
!13 = !{!"half8"} !13 = !{!"half8"}
!14 = !{!"float16"} !14 = !{!"float16"}
!15 = !{!"double16"} !15 = !{!"double16"}
!16 = !{!"int *"} !16 = !{!"int addrspace(5)*"}
!17 = !{!"image2d_t"} !17 = !{!"image2d_t"}
!18 = !{!"sampler_t"} !18 = !{!"sampler_t"}
!19 = !{!"queue_t"} !19 = !{!"queue_t"}
!20 = !{!"struct A"} !20 = !{!"struct A"}
!21 = !{!"i128"} !21 = !{!"i128"}
!22 = !{i32 0, i32 0, i32 0} !22 = !{i32 0, i32 0, i32 0}
!23 = !{!"none", !"none", !"none"} !23 = !{!"none", !"none", !"none"}
!24 = !{!"int", !"short2", !"char3"} !24 = !{!"int", !"short2", !"char3"}
!25 = !{!"", !"", !""} !25 = !{!"", !"", !""}
!26 = !{half undef, i32 1} !26 = !{half undef, i32 1}
!27 = !{float undef, i32 1} !27 = !{float undef, i32 1}
!28 = !{double undef, i32 1} !28 = !{double undef, i32 1}
!29 = !{i8 undef, i32 1} !29 = !{i8 undef, i32 1}
!30 = !{i16 undef, i32 1} !30 = !{i16 undef, i32 1}
!31 = !{i64 undef, i32 1} !31 = !{i64 undef, i32 1}
!32 = !{i32 *undef, i32 1} !32 = !{i32 addrspace(5)*undef, i32 1}
!50 = !{i32 1, i32 2, i32 3} !50 = !{i32 1, i32 2, i32 3}
!51 = !{!"int *", !"int *", !"int *"} !51 = !{!"int addrspace(5)*", !"int addrspace(5)*", !"int addrspace(5)*"}
!60 = !{i32 1, i32 1, i32 1} !60 = !{i32 1, i32 1, i32 1}
!61 = !{!"read_only", !"write_only", !"read_write"} !61 = !{!"read_only", !"write_only", !"read_write"}
!62 = !{!"image1d_t", !"image2d_t", !"image3d_t"} !62 = !{!"image1d_t", !"image2d_t", !"image3d_t"}
!70 = !{!"volatile", !"const restrict", !"pipe"} !70 = !{!"volatile", !"const restrict", !"pipe"}
!80 = !{!"int **"} !80 = !{!"int addrspace(5)* addrspace(5)*"}
!81 = !{i32 1} !81 = !{i32 1}
!82 = !{!"struct B"} !82 = !{!"struct B"}
!83 = !{!"global int* __attribute__((ext_vector_type(2)))"} !83 = !{!"global int addrspace(5)* __attribute__((ext_vector_type(2)))"}
!84 = !{!"clk_event_t"} !84 = !{!"clk_event_t"}
!opencl.ocl.version = !{!90} !opencl.ocl.version = !{!90}
!90 = !{i32 2, i32 0} !90 = !{i32 2, i32 0}
!91 = !{i32 0, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3} !91 = !{i32 0, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3}
!92 = !{!"none", !"none", !"none", !"none", !"none", !"none", !"none"} !92 = !{!"none", !"none", !"none", !"none", !"none", !"none", !"none"}
!93 = !{!"long *", !"char *", !"char2 *", !"char3 *", !"char4 *", !"char8 *", !"char16 *"} !93 = !{!"long addrspace(5)*", !"char addrspace(5)*", !"char2 addrspace(5)*", !"char3 addrspace(5)*", !"char4 addrspace(5)*", !"char8 addrspace(5)*", !"char16 addrspace(5)*"}
!94 = !{!"", !"", !"", !"", !"", !"", !""} !94 = !{!"", !"", !"", !"", !"", !"", !""}
!100 = !{!"1:1:4:%d\5Cn"} !100 = !{!"1:1:4:%d\5Cn"}
!101 = !{!"2:1:8:%g\5Cn"} !101 = !{!"2:1:8:%g\5Cn"}
!110 = !{!"__block_literal"} !110 = !{!"__block_literal"}
; PARSER: AMDGPU HSA Metadata Parser Test: PASS ; PARSER: AMDGPU HSA Metadata Parser Test: PASS

test/CodeGen/AMDGPU/huge-private-buffer.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; GCN-LABEL: {{^}}scratch_buffer_known_high_bit_small: ; GCN-LABEL: {{^}}scratch_buffer_known_high_bit_small:
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4
; GCN-NOT: [[FI]] ; GCN-NOT: [[FI]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FI]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[FI]]
define amdgpu_kernel void @scratch_buffer_known_high_bit_small() #0 { define amdgpu_kernel void @scratch_buffer_known_high_bit_small() #0 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%toint = ptrtoint i32* %alloca to i32 %toint = ptrtoint i32 addrspace(5)* %alloca to i32
%masked = and i32 %toint, 2147483647 %masked = and i32 %toint, 2147483647
store volatile i32 %masked, i32 addrspace(1)* undef store volatile i32 %masked, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}scratch_buffer_known_high_bit_huge: ; GCN-LABEL: {{^}}scratch_buffer_known_high_bit_huge:
; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4 ; GCN: v_mov_b32_e32 [[FI:v[0-9]+]], 4
; GCN-DAG: buffer_store_dword ; GCN-DAG: buffer_store_dword
; GCN-DAG: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x7ffffffc, [[FI]] ; GCN-DAG: v_and_b32_e32 [[MASKED:v[0-9]+]], 0x7ffffffc, [[FI]]
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MASKED]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[MASKED]]
define amdgpu_kernel void @scratch_buffer_known_high_bit_huge() #1 { define amdgpu_kernel void @scratch_buffer_known_high_bit_huge() #1 {
%alloca = alloca i32, align 4 %alloca = alloca i32, align 4, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%toint = ptrtoint i32* %alloca to i32 %toint = ptrtoint i32 addrspace(5)* %alloca to i32
%masked = and i32 %toint, 2147483647 %masked = and i32 %toint, 2147483647
store volatile i32 %masked, i32 addrspace(1)* undef store volatile i32 %masked, i32 addrspace(1)* undef
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind "target-features"="+huge-private-buffer" } attributes #1 = { nounwind "target-features"="+huge-private-buffer" }

test/CodeGen/AMDGPU/indirect-private-64.ll

Show All 16 Lines
; SI-ALLOCA4: buffer_load_dword v ; SI-ALLOCA4: buffer_load_dword v
; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64
; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64
; CI-PROMOTE: ds_write_b64 ; CI-PROMOTE: ds_write_b64
; CI-PROMOTE: ds_read_b64 ; CI-PROMOTE: ds_read_b64
define amdgpu_kernel void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_f64_alloca(double addrspace(1)* noalias %out, double addrspace(1)* noalias %in, i32 %b) #1 {
%val = load double, double addrspace(1)* %in, align 8 %val = load double, double addrspace(1)* %in, align 8
%array = alloca [8 x double], align 8 %array = alloca [8 x double], align 8, addrspace(5)
%ptr = getelementptr inbounds [8 x double], [8 x double]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [8 x double], [8 x double] addrspace(5)* %array, i32 0, i32 %b
store double %val, double* %ptr, align 8 store double %val, double addrspace(5)* %ptr, align 8
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load double, double* %ptr, align 8 %result = load double, double addrspace(5)* %ptr, align 8
store double %result, double addrspace(1)* %out, align 8 store double %result, double addrspace(1)* %out, align 8
ret void ret void
} }
; SI-LABEL: {{^}}private_access_v2f64_alloca: ; SI-LABEL: {{^}}private_access_v2f64_alloca:
; SI-ALLOCA16: buffer_store_dwordx4 ; SI-ALLOCA16: buffer_store_dwordx4
; SI-ALLOCA16: buffer_load_dwordx4 ; SI-ALLOCA16: buffer_load_dwordx4
Show All 10 Lines
; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64
; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64
; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64
; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64
; CI-PROMOTE: ds_write2_b64 ; CI-PROMOTE: ds_write2_b64
; CI-PROMOTE: ds_read2_b64 ; CI-PROMOTE: ds_read2_b64
define amdgpu_kernel void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_v2f64_alloca(<2 x double> addrspace(1)* noalias %out, <2 x double> addrspace(1)* noalias %in, i32 %b) #1 {
%val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16 %val = load <2 x double>, <2 x double> addrspace(1)* %in, align 16
%array = alloca [4 x <2 x double>], align 16 %array = alloca [4 x <2 x double>], align 16, addrspace(5)
%ptr = getelementptr inbounds [4 x <2 x double>], [4 x <2 x double>]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [4 x <2 x double>], [4 x <2 x double>] addrspace(5)* %array, i32 0, i32 %b
store <2 x double> %val, <2 x double>* %ptr, align 16 store <2 x double> %val, <2 x double> addrspace(5)* %ptr, align 16
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load <2 x double>, <2 x double>* %ptr, align 16 %result = load <2 x double>, <2 x double> addrspace(5)* %ptr, align 16
store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16 store <2 x double> %result, <2 x double> addrspace(1)* %out, align 16
ret void ret void
} }
; SI-LABEL: {{^}}private_access_i64_alloca: ; SI-LABEL: {{^}}private_access_i64_alloca:
; SI-ALLOCA16: buffer_store_dwordx2 ; SI-ALLOCA16: buffer_store_dwordx2
; SI-ALLOCA16: buffer_load_dwordx2 ; SI-ALLOCA16: buffer_load_dwordx2
; SI-ALLOCA4: buffer_store_dword v ; SI-ALLOCA4: buffer_store_dword v
; SI-ALLOCA4: buffer_store_dword v ; SI-ALLOCA4: buffer_store_dword v
; SI-ALLOCA4: buffer_load_dword v ; SI-ALLOCA4: buffer_load_dword v
; SI-ALLOCA4: buffer_load_dword v ; SI-ALLOCA4: buffer_load_dword v
; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64
; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64
; CI-PROMOTE: ds_write_b64 ; CI-PROMOTE: ds_write_b64
; CI-PROMOTE: ds_read_b64 ; CI-PROMOTE: ds_read_b64
define amdgpu_kernel void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_i64_alloca(i64 addrspace(1)* noalias %out, i64 addrspace(1)* noalias %in, i32 %b) #1 {
%val = load i64, i64 addrspace(1)* %in, align 8 %val = load i64, i64 addrspace(1)* %in, align 8
%array = alloca [8 x i64], align 8 %array = alloca [8 x i64], align 8, addrspace(5)
%ptr = getelementptr inbounds [8 x i64], [8 x i64]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [8 x i64], [8 x i64] addrspace(5)* %array, i32 0, i32 %b
store i64 %val, i64* %ptr, align 8 store i64 %val, i64 addrspace(5)* %ptr, align 8
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load i64, i64* %ptr, align 8 %result = load i64, i64 addrspace(5)* %ptr, align 8
store i64 %result, i64 addrspace(1)* %out, align 8 store i64 %result, i64 addrspace(1)* %out, align 8
ret void ret void
} }
; SI-LABEL: {{^}}private_access_v2i64_alloca: ; SI-LABEL: {{^}}private_access_v2i64_alloca:
; SI-ALLOCA16: buffer_store_dwordx4 ; SI-ALLOCA16: buffer_store_dwordx4
; SI-ALLOCA16: buffer_load_dwordx4 ; SI-ALLOCA16: buffer_load_dwordx4
Show All 11 Lines
; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64
; SI-PROMOTE: ds_write_b64 ; SI-PROMOTE: ds_write_b64
; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64
; SI-PROMOTE: ds_read_b64 ; SI-PROMOTE: ds_read_b64
; CI-PROMOTE: ds_write2_b64 ; CI-PROMOTE: ds_write2_b64
; CI-PROMOTE: ds_read2_b64 ; CI-PROMOTE: ds_read2_b64
define amdgpu_kernel void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) #1 { define amdgpu_kernel void @private_access_v2i64_alloca(<2 x i64> addrspace(1)* noalias %out, <2 x i64> addrspace(1)* noalias %in, i32 %b) #1 {
%val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16 %val = load <2 x i64>, <2 x i64> addrspace(1)* %in, align 16
%array = alloca [4 x <2 x i64>], align 16 %array = alloca [4 x <2 x i64>], align 16, addrspace(5)
%ptr = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>]* %array, i32 0, i32 %b %ptr = getelementptr inbounds [4 x <2 x i64>], [4 x <2 x i64>] addrspace(5)* %array, i32 0, i32 %b
store <2 x i64> %val, <2 x i64>* %ptr, align 16 store <2 x i64> %val, <2 x i64> addrspace(5)* %ptr, align 16
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%result = load <2 x i64>, <2 x i64>* %ptr, align 16 %result = load <2 x i64>, <2 x i64> addrspace(5)* %ptr, align 16
store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16 store <2 x i64> %result, <2 x i64> addrspace(1)* %out, align 16
ret void ret void
} }
attributes #0 = { convergent nounwind } attributes #0 = { convergent nounwind }
attributes #1 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="64,128" } attributes #1 = { nounwind "amdgpu-waves-per-eu"="1,2" "amdgpu-flat-work-group-size"="64,128" }

test/CodeGen/AMDGPU/insert_subreg.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mcpu=tahiti -mattr=-promote-alloca -verify-machineinstrs < %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-promote-alloca -verify-machineinstrs < %s
; Test that INSERT_SUBREG instructions don't have non-register operands after ; Test that INSERT_SUBREG instructions don't have non-register operands after
; instruction selection. ; instruction selection.
; Make sure this doesn't crash ; Make sure this doesn't crash
; CHECK-LABEL: test: ; CHECK-LABEL: test:
define amdgpu_kernel void @test(i64 addrspace(1)* %out) { define amdgpu_kernel void @test(i64 addrspace(1)* %out) {
entry: entry:
%tmp0 = alloca [16 x i32] %tmp0 = alloca [16 x i32], addrspace(5)
%tmp1 = ptrtoint [16 x i32]* %tmp0 to i32 %tmp1 = ptrtoint [16 x i32] addrspace(5)* %tmp0 to i32
%tmp2 = sext i32 %tmp1 to i64 %tmp2 = sext i32 %tmp1 to i64
store i64 %tmp2, i64 addrspace(1)* %out store i64 %tmp2, i64 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/inserted-wait-states.mir

Show All 11 Lines--- |
define amdgpu_kernel void @rfe() { ret void } define amdgpu_kernel void @rfe() { ret void }
define amdgpu_kernel void @s_mov_fed_b32() { ret void } define amdgpu_kernel void @s_mov_fed_b32() { ret void }
define amdgpu_kernel void @s_movrel() { ret void } define amdgpu_kernel void @s_movrel() { ret void }
define amdgpu_kernel void @v_interp() { ret void } define amdgpu_kernel void @v_interp() { ret void }
define amdgpu_kernel void @dpp() { ret void } define amdgpu_kernel void @dpp() { ret void }
define amdgpu_kernel void @mov_fed_hazard_crash_on_dbg_value(i32 addrspace(1)* %A) { define amdgpu_kernel void @mov_fed_hazard_crash_on_dbg_value(i32 addrspace(1)* %A) {
entry: entry:
%A.addr = alloca i32 addrspace(1)*, align 4 %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !5, metadata !11), !dbg !12 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !5, metadata !11), !dbg !12
ret void ret void
} }
declare void @llvm.dbg.declare(metadata, metadata, metadata) #1 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!llvm.module.flags = !{!3, !4} !llvm.module.flags = !{!3, !4}
▲ Show 20 Lines • Show All 532 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/kernarg-stack-alignment.ll

; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck %s
; Test that the alignment of kernel arguments does not impact the ; Test that the alignment of kernel arguments does not impact the
; alignment of the stack ; alignment of the stack
; CHECK-LABEL: {{^}}no_args: ; CHECK-LABEL: {{^}}no_args:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @no_args() { define amdgpu_kernel void @no_args() {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align32: ; CHECK-LABEL: {{^}}force_align32:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align32(<8 x i32>) { define amdgpu_kernel void @force_align32(<8 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align64: ; CHECK-LABEL: {{^}}force_align64:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align64(<16 x i32>) { define amdgpu_kernel void @force_align64(<16 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align128: ; CHECK-LABEL: {{^}}force_align128:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align128(<32 x i32>) { define amdgpu_kernel void @force_align128(<32 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }
; CHECK-LABEL: {{^}}force_align256: ; CHECK-LABEL: {{^}}force_align256:
; CHECK: ScratchSize: 5{{$}} ; CHECK: ScratchSize: 5{{$}}
define amdgpu_kernel void @force_align256(<64 x i32>) { define amdgpu_kernel void @force_align256(<64 x i32>) {
%alloca = alloca i8 %alloca = alloca i8, addrspace(5)
store volatile i8 0, i8* %alloca store volatile i8 0, i8 addrspace(5)* %alloca
ret void ret void
} }

test/CodeGen/AMDGPU/large-alloca-compute.ll

Show All 40 Lines
; GCNHSA: workitem_private_segment_byte_size = 32772 ; GCNHSA: workitem_private_segment_byte_size = 32772
; GCNHSA: private_segment_alignment = 4 ; GCNHSA: private_segment_alignment = 4
; GCNHSA: .end_amd_kernel_code_t ; GCNHSA: .end_amd_kernel_code_t
; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen ; GCNHSA: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen
; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen ; GCNHSA: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[0:3], s9 offen
; Scratch size = alloca size + emergency stack slot ; Scratch size = alloca size + emergency stack slot, align {{.*}}, addrspace(5)
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 { define amdgpu_kernel void @large_alloca_compute_shader(i32 %x, i32 %y) #0 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32 addrspace(5)* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/large-alloca-graphics.ll

Show All 9 Lines
; VI-DAG: s_mov_b32 s11, 0xe80000 ; VI-DAG: s_mov_b32 s11, 0xe80000
; GFX9-DAG: s_mov_b32 s11, 0xe00000 ; GFX9-DAG: s_mov_b32 s11, 0xe00000
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s0 offen
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 { define amdgpu_ps void @large_alloca_pixel_shader(i32 %x, i32 %y) #0 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32 addrspace(5)* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
; ALL-LABEL: {{^}}large_alloca_pixel_shader_inreg: ; ALL-LABEL: {{^}}large_alloca_pixel_shader_inreg:
; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s8, SCRATCH_RSRC_DWORD0
; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 ; GCN-DAG: s_mov_b32 s9, SCRATCH_RSRC_DWORD1
; GCN-DAG: s_mov_b32 s10, -1 ; GCN-DAG: s_mov_b32 s10, -1
; CI-DAG: s_mov_b32 s11, 0xe8f000 ; CI-DAG: s_mov_b32 s11, 0xe8f000
; VI-DAG: s_mov_b32 s11, 0xe80000 ; VI-DAG: s_mov_b32 s11, 0xe80000
; GFX9-DAG: s_mov_b32 s11, 0xe00000 ; GFX9-DAG: s_mov_b32 s11, 0xe00000
; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen ; GCN: buffer_store_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen
; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen ; GCN: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, s[8:11], s2 offen
; ALL: ; ScratchSize: 32772 ; ALL: ; ScratchSize: 32772
define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 { define amdgpu_ps void @large_alloca_pixel_shader_inreg(i32 inreg %x, i32 inreg %y) #0 {
%large = alloca [8192 x i32], align 4 %large = alloca [8192 x i32], align 4, addrspace(5)
%gep = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 8191 %gep = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 8191
store volatile i32 %x, i32* %gep store volatile i32 %x, i32 addrspace(5)* %gep
%gep1 = getelementptr [8192 x i32], [8192 x i32]* %large, i32 0, i32 %y %gep1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %large, i32 0, i32 %y
%val = load volatile i32, i32* %gep1 %val = load volatile i32, i32 addrspace(5)* %gep1
store volatile i32 %val, i32 addrspace(1)* undef store volatile i32 %val, i32 addrspace(1)* undef
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/llvm.amdgcn.atomic.dec.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,CIVI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9 %s
declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* nocapture, i64, i32, i32, i1) #2
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
; Make sure no crash on invalid non-constant ; Make sure no crash on invalid non-constant
; GCN-LABEL: {{^}}invalid_variable_order_lds_atomic_dec_ret_i32: ; GCN-LABEL: {{^}}invalid_variable_order_lds_atomic_dec_ret_i32:
; CIVI-DAG: s_mov_b32 m0 ; CIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
define amdgpu_kernel void @invalid_variable_order_lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %order.var) #0 { define amdgpu_kernel void @invalid_variable_order_lds_atomic_dec_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr, i32 %order.var) #0 {
▲ Show 20 Lines • Show All 134 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @global_atomic_dec_noret_i32_offset_addr64(i32 addrspace(1)* %ptr) #0 {
%gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i32, i32 addrspace(1)* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i32(i32* %out, i32* %ptr) #0 {
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; CIVI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
; GFX9: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16 glc{{$}} ; GFX9: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16 glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset(i32* %out, i32* %ptr) #0 {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i32(i32* %ptr) nounwind {
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; CIVI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
; GFX9: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16{{$}} ; GFX9: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset(i32* %ptr) nounwind {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; CIVI: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
; GFX9: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20 glc{{$}} ; GFX9: flat_atomic_dec v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20 glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 %id %out.gep = getelementptr i32, i32* %out, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out.gep store i32 %result, i32* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; CIVI: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
; GFX9: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20{{$}} ; GFX9: flat_atomic_dec v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_noret_i32_offset_addr64(i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64(i64* %out, i64* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset(i64* %out, i64* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i64(i64* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset(i64* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_ret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}}
define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%out.gep = getelementptr i64, i64 addrspace(4)* %out, i32 %id %out.gep = getelementptr i64, i64* %out, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_dec_noret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}} ; GFX9: flat_atomic_dec_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}}
define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_dec_noret_i64_offset_addr64(i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
@lds0 = addrspace(3) global [512 x i32] undef @lds0 = addrspace(3) global [512 x i32] undef
; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0: ; GCN-LABEL: {{^}}atomic_dec_shl_base_lds_0:
; CIVI-DAG: s_mov_b32 m0 ; CIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
▲ Show 20 Lines • Show All 160 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll

; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* nocapture, i64, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* nocapture, i64, i32, i32, i1) #2
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32: ; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32:
; CIVI-DAG: s_mov_b32 m0 ; CIVI-DAG: s_mov_b32 m0
; GFX9-NOT: m0 ; GFX9-NOT: m0
; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
▲ Show 20 Lines • Show All 236 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @global_atomic_inc_noret_i64_offset_addr64(i64 addrspace(1)* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5 %gep = getelementptr i64, i64 addrspace(1)* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; GCN: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i32(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i32(i32* %out, i32* %ptr) #0 {
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; CIVI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
; GFX9: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16 glc{{$}} ; GFX9: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16 glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset(i32* %out, i32* %ptr) #0 {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out store i32 %result, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; GCN: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i32(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i32(i32* %ptr) nounwind {
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %ptr, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %ptr, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; CIVI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
; GFX9: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16{{$}} ; GFX9: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:16{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(i32 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset(i32* %ptr) nounwind {
%gep = getelementptr i32, i32 addrspace(4)* %ptr, i32 4 %gep = getelementptr i32, i32* %ptr, i32 4
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}} ; CIVI: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] glc{{$}}
; GFX9: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20 glc{{$}} ; GFX9: flat_atomic_inc v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20 glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32 addrspace(4)* %out, i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i32_offset_addr64(i32* %out, i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%out.gep = getelementptr i32, i32 addrspace(4)* %out, i32 %id %out.gep = getelementptr i32, i32* %out, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
store i32 %result, i32 addrspace(4)* %out.gep store i32 %result, i32* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i32_offset_addr64:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; CIVI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}} ; CIVI: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]]{{$}}
; GFX9: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20{{$}} ; GFX9: flat_atomic_inc v{{\[[0-9]+:[0-9]+\]}}, [[K]] offset:20{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_noret_i32_offset_addr64(i32* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i32, i32 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i32, i32* %ptr, i32 %id
%gep = getelementptr i32, i32 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i32, i32* %gep.tid, i32 5
%result = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %gep, i32 42, i32 0, i32 0, i1 false) %result = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %gep, i32 42, i32 0, i32 0, i1 false)
ret void ret void
} }
@lds1 = addrspace(3) global [512 x i64] undef, align 8 @lds1 = addrspace(3) global [512 x i64] undef, align 8
; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i64: ; GCN-LABEL: {{^}}atomic_inc_shl_base_lds_0_i64:
; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 3, {{v[0-9]+}} ; GCN: v_lshlrev_b32_e32 [[PTR:v[0-9]+]], 3, {{v[0-9]+}}
; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]], v{{\[[0-9]+:[0-9]+\]}} offset:16 ; GCN: ds_inc_rtn_u64 v{{\[[0-9]+:[0-9]+\]}}, [[PTR]], v{{\[[0-9]+:[0-9]+\]}} offset:16
define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 { define amdgpu_kernel void @atomic_inc_shl_base_lds_0_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %add_use) #0 {
%tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %tid.x = tail call i32 @llvm.amdgcn.workitem.id.x() #1
%idx.0 = add nsw i32 %tid.x, 2 %idx.0 = add nsw i32 %tid.x, 2
%arrayidx0 = getelementptr inbounds [512 x i64], [512 x i64] addrspace(3)* @lds1, i32 0, i32 %idx.0 %arrayidx0 = getelementptr inbounds [512 x i64], [512 x i64] addrspace(3)* @lds1, i32 0, i32 %idx.0
%val0 = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %arrayidx0, i64 9, i32 0, i32 0, i1 false) %val0 = call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %arrayidx0, i64 9, i32 0, i32 0, i1 false)
store i32 %idx.0, i32 addrspace(1)* %add_use store i32 %idx.0, i32 addrspace(1)* %add_use
store i64 %val0, i64 addrspace(1)* %out store i64 %val0, i64 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64(i64* %out, i64* %ptr) #0 {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32 glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset(i64* %out, i64* %ptr) #0 {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out store i64 %result, i64* %out
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; GCN: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i64(i64* %ptr) nounwind {
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %ptr, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %ptr, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset:
; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN-DAG: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN-DAG: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:32{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64 addrspace(4)* %ptr) nounwind { define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset(i64* %ptr) nounwind {
%gep = getelementptr i64, i64 addrspace(4)* %ptr, i32 4 %gep = getelementptr i64, i64* %ptr, i32 4
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_ret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} glc{{$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40 glc{{$}}
define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64 addrspace(4)* %out, i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_ret_i64_offset_addr64(i64* %out, i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%out.gep = getelementptr i64, i64 addrspace(4)* %out, i32 %id %out.gep = getelementptr i64, i64* %out, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
store i64 %result, i64 addrspace(4)* %out.gep store i64 %result, i64* %out.gep
ret void ret void
} }
; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset_addr64: ; GCN-LABEL: {{^}}flat_atomic_inc_noret_i64_offset_addr64:
; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42 ; GCN: v_mov_b32_e32 v[[KLO:[0-9]+]], 42
; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}} ; GCN: v_mov_b32_e32 v[[KHI:[0-9]+]], 0{{$}}
; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}} ; CIVI: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]$}}
; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}} ; GFX9: flat_atomic_inc_x2 v{{\[[0-9]+:[0-9]+\]}}, v{{\[}}[[KLO]]:[[KHI]]{{\]}} offset:40{{$}}
define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64 addrspace(4)* %ptr) #0 { define amdgpu_kernel void @flat_atomic_inc_noret_i64_offset_addr64(i64* %ptr) #0 {
%id = call i32 @llvm.amdgcn.workitem.id.x() %id = call i32 @llvm.amdgcn.workitem.id.x()
%gep.tid = getelementptr i64, i64 addrspace(4)* %ptr, i32 %id %gep.tid = getelementptr i64, i64* %ptr, i32 %id
%gep = getelementptr i64, i64 addrspace(4)* %gep.tid, i32 5 %gep = getelementptr i64, i64* %gep.tid, i32 5
%result = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %gep, i64 42, i32 0, i32 0, i1 false) %result = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %gep, i64 42, i32 0, i32 0, i1 false)
ret void ret void
} }
; GCN-LABEL: {{^}}nocse_lds_atomic_inc_ret_i32: ; GCN-LABEL: {{^}}nocse_lds_atomic_inc_ret_i32:
; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42 ; GCN: v_mov_b32_e32 [[K:v[0-9]+]], 42
; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] ; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]] ; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(3)* %ptr) #0 { define amdgpu_kernel void @nocse_lds_atomic_inc_ret_i32(i32 addrspace(1)* %out0, i32 addrspace(1)* %out1, i32 addrspace(3)* %ptr) #0 {
Show All 11 Lines

test/CodeGen/AMDGPU/llvm.amdgcn.implicit.buffer.ptr.ll

; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-mesa-mesa3d -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; FIXME: Requires stack object to not assert ; FIXME: Requires stack object to not assert
; GCN-LABEL: {{^}}test_ps: ; GCN-LABEL: {{^}}test_ps:
; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0 ; GCN: s_load_dwordx2 s[4:5], s[0:1], 0x0
; GCN: buffer_store_dword v0, off, s[4:7], s2 offset:4 ; GCN: buffer_store_dword v0, off, s[4:7], s2 offset:4
; GCN: s_load_dword s{{[0-9]+}}, s[0:1], 0x0 ; GCN: s_load_dword s{{[0-9]+}}, s[0:1], 0x0
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: ; return ; GCN-NEXT: ; return
define amdgpu_ps i32 @test_ps() #1 { define amdgpu_ps i32 @test_ps() #1 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr()
%buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)*
%value = load volatile i32, i32 addrspace(2)* %buffer_ptr %value = load volatile i32, i32 addrspace(2)* %buffer_ptr
ret i32 %value ret i32 %value
} }
; GCN-LABEL: {{^}}test_cs: ; GCN-LABEL: {{^}}test_cs:
; GCN: s_mov_b64 s[4:5], s[0:1] ; GCN: s_mov_b64 s[4:5], s[0:1]
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:4 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:4
; GCN: s_load_dword s0, s[0:1], 0x0 ; GCN: s_load_dword s0, s[0:1], 0x0
define amdgpu_cs i32 @test_cs() #1 { define amdgpu_cs i32 @test_cs() #1 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
store volatile i32 0, i32* %alloca store volatile i32 0, i32 addrspace(5)* %alloca
%implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() %implicit_buffer_ptr = call i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr()
%buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)* %buffer_ptr = bitcast i8 addrspace(2)* %implicit_buffer_ptr to i32 addrspace(2)*
%value = load volatile i32, i32 addrspace(2)* %buffer_ptr %value = load volatile i32, i32 addrspace(2)* %buffer_ptr
ret i32 %value ret i32 %value
} }
declare i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() #0 declare i8 addrspace(2)* @llvm.amdgcn.implicit.buffer.ptr() #0
attributes #0 = { nounwind readnone speculatable } attributes #0 = { nounwind readnone speculatable }
attributes #1 = { nounwind } attributes #1 = { nounwind }

test/CodeGen/AMDGPU/load-hi16.ll

Show First 20 Lines • Show All 215 Lines • ▼ Show 20 Lines
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort v{{[0-9]+}} ; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2i16_reglo_vreg(i16 addrspace(4)* %in, i16 %reg) #0 { define void @load_flat_hi_v2i16_reglo_vreg(i16* %in, i16 %reg) #0 {
entry: entry:
%load = load i16, i16 addrspace(4)* %in %load = load i16, i16* %in
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_flat_hi_v2f16_reglo_vreg: ; GCN-LABEL: {{^}}load_flat_hi_v2f16_reglo_vreg:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_load_short_d16_hi v2, v[0:1] ; GFX9-NEXT: flat_load_short_d16_hi v2, v[0:1]
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort v{{[0-9]+}} ; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2f16_reglo_vreg(half addrspace(4)* %in, half %reg) #0 { define void @load_flat_hi_v2f16_reglo_vreg(half* %in, half %reg) #0 {
entry: entry:
%load = load half, half addrspace(4)* %in %load = load half, half* %in
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_flat_hi_v2i16_reglo_vreg_zexti8: ; GCN-LABEL: {{^}}load_flat_hi_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_load_ubyte_d16_hi v2, v[0:1] ; GFX9-NEXT: flat_load_ubyte_d16_hi v2, v[0:1]
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ubyte v{{[0-9]+}} ; VI: flat_load_ubyte v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(4)* %in, i16 %reg) #0 { define void @load_flat_hi_v2i16_reglo_vreg_zexti8(i8* %in, i16 %reg) #0 {
entry: entry:
%load = load i8, i8 addrspace(4)* %in %load = load i8, i8* %in
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_flat_hi_v2i16_reglo_vreg_sexti8: ; GCN-LABEL: {{^}}load_flat_hi_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_load_sbyte_d16_hi v2, v[0:1] ; GFX9-NEXT: flat_load_sbyte_d16_hi v2, v[0:1]
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_sbyte v{{[0-9]+}} ; VI: flat_load_sbyte v{{[0-9]+}}
; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16, ; VI: v_lshlrev_b32_e32 v{{[0-9]+}}, 16,
; VI: v_or_b32_sdwa ; VI: v_or_b32_sdwa
define void @load_flat_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(4)* %in, i16 %reg) #0 { define void @load_flat_hi_v2i16_reglo_vreg_sexti8(i8* %in, i16 %reg) #0 {
entry: entry:
%load = load i8, i8 addrspace(4)* %in %load = load i8, i8* %in
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}} ; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg(i16* byval %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16* %in, i64 2045 %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2045
%load = load i16, i16* %gep %load = load i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg: ; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}} ; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg(half* byval %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg(half addrspace(5)* byval %in, half %reg) #0 {
entry: entry:
%gep = getelementptr inbounds half, half* %in, i64 2045 %gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2045
%load = load half, half* %gep %load = load half, half addrspace(5)* %gep
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s4 offset:4094{{$}} ; GFX9: buffer_load_short_d16_hi v0, off, s[0:3], s4 offset:4094{{$}}
; GFX9: s_waitcnt ; GFX9: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff(i16* byval %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff(i16 addrspace(5)* byval %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i16, i16* inttoptr (i32 4094 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff: ; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_short_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff(half* %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, half %reg) #0 {
entry: entry:
%load = load volatile half, half* inttoptr (i32 4094 to half*) %load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %load, i32 1 %build1 = insertelement <2 x half> %build0, half %load, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_ubyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}} ; GFX9: buffer_load_ubyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}} ; VI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8* byval %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i8, i8* %in, i64 4091 %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_sbyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}} ; GFX9: buffer_load_sbyte_d16_hi v0, off, s[0:3], s5 offset:4095{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}} ; VI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8* byval %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i8, i8* %in, i64 4091 %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_zexti8: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_sexti8: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_nooff_sexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_sbyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_sbyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8* %in, i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i16 %reg) #0 {
entry: entry:
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff_zexti8: ; GCN-LABEL: {{^}}load_private_hi_v2f16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_ubyte_d16_hi v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8* %in, half %reg) #0 { define void @load_private_hi_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, half %reg) #0 {
entry: entry:
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%bc.ext = bitcast i16 %ext to half %bc.ext = bitcast i16 %ext to half
%build0 = insertelement <2 x half> undef, half %reg, i32 0 %build0 = insertelement <2 x half> undef, half %reg, i32 0
%build1 = insertelement <2 x half> %build0, half %bc.ext, i32 1 %build1 = insertelement <2 x half> %build0, half %bc.ext, i32 1
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
Show All 38 Lines
; Local object gives known offset, so requires converting from offen ; Local object gives known offset, so requires converting from offen
; to offset variant. ; to offset variant.
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_to_offset: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_to_offset:
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4094 ; GFX9-NEXT: buffer_load_short_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4094
define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i16], align 2 %obj1 = alloca [4096 x i16], align 2, addrspace(5)
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i16], [4096 x i16]* %obj1, i32 0, i32 2025 %gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2025
%load = load i16, i16* %gep %load = load i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8_to_offset: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_sexti8_to_offset:
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095 ; GFX9-NEXT: buffer_load_sbyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
define void @load_private_hi_v2i16_reglo_vreg_sexti8_to_offset(i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_sexti8_to_offset(i16 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2 %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4051
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8_to_offset: ; GCN-LABEL: {{^}}load_private_hi_v2i16_reglo_vreg_zexti8_to_offset:
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095 ; GFX9-NEXT: buffer_load_ubyte_d16_hi v{{[0-9]+}}, off, s[0:3], s5 offset:4095
define void @load_private_hi_v2i16_reglo_vreg_zexti8_to_offset(i16 %reg) #0 { define void @load_private_hi_v2i16_reglo_vreg_zexti8_to_offset(i16 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2 %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4051
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 0 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %ext, i32 1
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; FIXME: Remove m0 init and waitcnt between reads ; FIXME: Remove m0 init and waitcnt between reads
Show All 39 Lines
; GCN-LABEL: {{^}}load_flat_v2i16_split: ; GCN-LABEL: {{^}}load_flat_v2i16_split:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_load_ushort v2 ; GFX9-NEXT: flat_load_ushort v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: flat_load_short_d16_hi v2 ; GFX9-NEXT: flat_load_short_d16_hi v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: v_mov_b32_e32 v0, v2 ; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define <2 x i16> @load_flat_v2i16_split(i16 addrspace(4)* %in) #0 { define <2 x i16> @load_flat_v2i16_split(i16* %in) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16 addrspace(4)* %in, i64 1 %gep = getelementptr inbounds i16, i16* %in, i64 1
%load0 = load volatile i16, i16 addrspace(4)* %in %load0 = load volatile i16, i16* %in
%load1 = load volatile i16, i16 addrspace(4)* %gep %load1 = load volatile i16, i16* %gep
%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1 ret <2 x i16> %build1
} }
; FIXME: Remove waitcnt between reads ; FIXME: Remove waitcnt between reads
; GCN-LABEL: {{^}}load_constant_v2i16_split: ; GCN-LABEL: {{^}}load_constant_v2i16_split:
; GCN: s_waitcnt ; GCN: s_waitcnt
Show All 17 Lines
; FIXME: Is there a cost to using the extload over not? ; FIXME: Is there a cost to using the extload over not?
; GCN-LABEL: {{^}}load_private_v2i16_split: ; GCN-LABEL: {{^}}load_private_v2i16_split:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_ushort v0, off, s[0:3], s5 offset:4{{$}} ; GFX9: buffer_load_ushort v0, off, s[0:3], s5 offset:4{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:6 ; GFX9-NEXT: buffer_load_short_d16_hi v0, off, s[0:3], s5 offset:6
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
define <2 x i16> @load_private_v2i16_split(i16* byval %in) #0 { define <2 x i16> @load_private_v2i16_split(i16 addrspace(5)* byval %in) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16* %in, i32 1 %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i32 1
%load0 = load volatile i16, i16* %in %load0 = load volatile i16, i16 addrspace(5)* %in
%load1 = load volatile i16, i16* %gep %load1 = load volatile i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %load0, i32 0 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
%build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1 %build1 = insertelement <2 x i16> %build0, i16 %load1, i32 1
ret <2 x i16> %build1 ret <2 x i16> %build1
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/load-lo16.ll

Show First 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
; GFX9-NEXT: flat_load_short_d16 v2, v[0:1] ; GFX9-NEXT: flat_load_short_d16 v2, v[0:1]
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort v{{[0-9]+}} ; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_or_b32_e32 ; VI: v_or_b32_e32
define void @load_flat_lo_v2i16_reghi_vreg(i16 addrspace(4)* %in, i32 %reg) #0 { define void @load_flat_lo_v2i16_reghi_vreg(i16* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i16, i16 addrspace(4)* %in %load = load i16, i16* %in
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_flat_lo_v2f16_reghi_vreg: ; GCN-LABEL: {{^}}load_flat_lo_v2f16_reghi_vreg:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_load_short_d16 v2, v[0:1] ; GFX9-NEXT: flat_load_short_d16 v2, v[0:1]
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ushort v{{[0-9]+}} ; VI: flat_load_ushort v{{[0-9]+}}
; VI: v_or_b32_e32 ; VI: v_or_b32_e32
define void @load_flat_lo_v2f16_reghi_vreg(half addrspace(4)* %in, i32 %reg) #0 { define void @load_flat_lo_v2f16_reghi_vreg(half* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%load = load half, half addrspace(4)* %in %load = load half, half* %in
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0 %build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_zexti8: ; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_load_ubyte_d16 v2, v[0:1] ; GFX9-NEXT: flat_load_ubyte_d16 v2, v[0:1]
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_ubyte v{{[0-9]+}} ; VI: flat_load_ubyte v{{[0-9]+}}
; VI: v_or_b32_e32 ; VI: v_or_b32_e32
define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(4)* %in, i32 %reg) #0 { define void @load_flat_lo_v2i16_reglo_vreg_zexti8(i8* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8 addrspace(4)* %in %load = load i8, i8* %in
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_sexti8: ; GCN-LABEL: {{^}}load_flat_lo_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_load_sbyte_d16 v2, v[0:1] ; GFX9-NEXT: flat_load_sbyte_d16 v2, v[0:1]
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v[0:1], v2 ; GFX9-NEXT: global_store_dword v[0:1], v2
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: flat_load_sbyte v{{[0-9]+}} ; VI: flat_load_sbyte v{{[0-9]+}}
; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI: v_or_b32_sdwa v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
define void @load_flat_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(4)* %in, i32 %reg) #0 { define void @load_flat_lo_v2i16_reglo_vreg_sexti8(i8* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load i8, i8 addrspace(4)* %in %load = load i8, i8* %in
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094{{$}} ; GFX9: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg(i16* byval %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg(i16 addrspace(5)* byval %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i16, i16* %in, i64 2045 %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2045
%load = load i16, i16* %gep %load = load i16, i16 addrspace(5)* %gep
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_ushort v1, off, s[0:3], s5 offset:4094{{$}} ; GFX9: buffer_load_ushort v1, off, s[0:3], s5 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9: v_and_b32 ; GFX9: v_and_b32
; GFX9: v_lshl_or_b32 ; GFX9: v_lshl_or_b32
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
define void @load_private_lo_v2i16_reghi_vreg(i16* byval %in, i16 %reg) #0 { define void @load_private_lo_v2i16_reghi_vreg(i16 addrspace(5)* byval %in, i16 %reg) #0 {
entry: entry:
%gep = getelementptr inbounds i16, i16* %in, i64 2045 %gep = getelementptr inbounds i16, i16 addrspace(5)* %in, i64 2045
%load = load i16, i16* %gep %load = load i16, i16 addrspace(5)* %gep
%build0 = insertelement <2 x i16> undef, i16 %reg, i32 1 %build0 = insertelement <2 x i16> undef, i16 %reg, i32 1
%build1 = insertelement <2 x i16> %build0, i16 %load, i32 0 %build1 = insertelement <2 x i16> %build0, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg: ; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094{{$}} ; GFX9: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s5 offset:4094{{$}}
define void @load_private_lo_v2f16_reglo_vreg(half* byval %in, i32 %reg) #0 { define void @load_private_lo_v2f16_reglo_vreg(half addrspace(5)* byval %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%gep = getelementptr inbounds half, half* %in, i64 2045 %gep = getelementptr inbounds half, half addrspace(5)* %in, i64 2045
%load = load half, half* %gep %load = load half, half addrspace(5)* %gep
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0 %build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg_nooff(i16* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i16, i16* inttoptr (i32 4094 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg_nooff: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reghi_vreg_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_lo_v2i16_reghi_vreg_nooff(i16* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reghi_vreg_nooff(i16 addrspace(5)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i16, i16* inttoptr (i32 4094 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 4094 to i16 addrspace(5)*)
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff: ; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_short_d16 v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ushort v{{[0-9]+}}, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_lo_v2f16_reglo_vreg_nooff(half* %in, i32 %reg) #0 { define void @load_private_lo_v2f16_reglo_vreg_nooff(half addrspace(5)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%load = load volatile half, half* inttoptr (i32 4094 to half*) %load = load volatile half, half addrspace(5)* inttoptr (i32 4094 to half addrspace(5)*)
%build1 = insertelement <2 x half> %reg.bc, half %load, i32 0 %build1 = insertelement <2 x half> %reg.bc, half %load, i32 0
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_ubyte_d16 v0, off, s[0:3], s5 offset:4095{{$}} ; GFX9: buffer_load_ubyte_d16 v0, off, s[0:3], s5 offset:4095{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}} ; VI: buffer_load_ubyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8* byval %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_zexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i8, i8* %in, i64 4091 %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_load_sbyte_d16 v0, off, s[0:3], s5 offset:4095{{$}} ; GFX9: buffer_load_sbyte_d16 v0, off, s[0:3], s5 offset:4095{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v0
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}} ; VI: buffer_load_sbyte v{{[0-9]+}}, off, s[0:3], s5 offset:4095{{$}}
define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8* byval %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_sexti8(i8 addrspace(5)* byval %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%gep = getelementptr inbounds i8, i8* %in, i64 4091 %gep = getelementptr inbounds i8, i8 addrspace(5)* %in, i64 4091
%load = load i8, i8* %gep %load = load i8, i8 addrspace(5)* %gep
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_zexti8: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg_nooff_zexti8(i8* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_sexti8: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_nooff_sexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_sbyte_d16 v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_sbyte_d16 v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_sbyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_lo_v2i16_reglo_vreg_nooff_sexti8(i8* %in, i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_nooff_sexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = sext i8 %load to i16 %ext = sext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff_zexti8: ; GCN-LABEL: {{^}}load_private_lo_v2f16_reglo_vreg_nooff_zexti8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s4 offset:4094{{$}} ; GFX9-NEXT: buffer_load_ubyte_d16 v1, off, s[0:3], s4 offset:4094{{$}}
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1 ; GFX9-NEXT: global_store_dword v{{\[[0-9]+:[0-9]+\]}}, v1
; GFX9-NEXT: s_waitcnt ; GFX9-NEXT: s_waitcnt
; GFX9-NEXT: s_setpc_b64 ; GFX9-NEXT: s_setpc_b64
; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}} ; VI: buffer_load_ubyte v0, off, s[0:3], s4 offset:4094{{$}}
define void @load_private_lo_v2f16_reglo_vreg_nooff_zexti8(i8* %in, i32 %reg) #0 { define void @load_private_lo_v2f16_reglo_vreg_nooff_zexti8(i8 addrspace(5)* %in, i32 %reg) #0 {
entry: entry:
%reg.bc = bitcast i32 %reg to <2 x half> %reg.bc = bitcast i32 %reg to <2 x half>
%load = load volatile i8, i8* inttoptr (i32 4094 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 4094 to i8 addrspace(5)*)
%ext = zext i8 %load to i16 %ext = zext i8 %load to i16
%bc.ext = bitcast i16 %ext to half %bc.ext = bitcast i16 %ext to half
%build1 = insertelement <2 x half> %reg.bc, half %bc.ext, i32 0 %build1 = insertelement <2 x half> %reg.bc, half %bc.ext, i32 0
store <2 x half> %build1, <2 x half> addrspace(1)* undef store <2 x half> %build1, <2 x half> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_constant_lo_v2i16_reglo_vreg: ; GCN-LABEL: {{^}}load_constant_lo_v2i16_reglo_vreg:
Show All 36 Lines
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_to_offset: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_to_offset:
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094 ; GFX9-NEXT: buffer_load_short_d16 v0, off, s[0:3], s5 offset:4094
; VI: buffer_load_ushort v ; VI: buffer_load_ushort v
define void @load_private_lo_v2i16_reglo_vreg_to_offset(i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_to_offset(i32 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i16], align 2 %obj1 = alloca [4096 x i16], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i16], [4096 x i16]* %obj1, i32 0, i32 2025 %gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2025
%load = load volatile i16, i16* %gep %load = load volatile i16, i16 addrspace(5)* %gep
%build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8_to_offset: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_sexti8_to_offset:
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s5 offset:4095 ; GFX9-NEXT: buffer_load_sbyte_d16 v0, off, s[0:3], s5 offset:4095
; VI: buffer_load_sbyte v ; VI: buffer_load_sbyte v
define void @load_private_lo_v2i16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_sexti8_to_offset(i32 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2 %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4051
%load = load volatile i8, i8* %gep %load = load volatile i8, i8 addrspace(5)* %gep
%load.ext = sext i8 %load to i16 %load.ext = sext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8_to_offset: ; GCN-LABEL: {{^}}load_private_lo_v2i16_reglo_vreg_zexti8_to_offset:
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s5 offset:4095 ; GFX9-NEXT: buffer_load_ubyte_d16 v0, off, s[0:3], s5 offset:4095
; VI: buffer_load_ubyte v ; VI: buffer_load_ubyte v
define void @load_private_lo_v2i16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 { define void @load_private_lo_v2i16_reglo_vreg_zexti8_to_offset(i32 %reg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2 %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%reg.bc = bitcast i32 %reg to <2 x i16> %reg.bc = bitcast i32 %reg to <2 x i16>
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4051
%load = load volatile i8, i8* %gep %load = load volatile i8, i8 addrspace(5)* %gep
%load.ext = zext i8 %load to i16 %load.ext = zext i8 %load to i16
%build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0 %build1 = insertelement <2 x i16> %reg.bc, i16 %load.ext, i32 0
store <2 x i16> %build1, <2 x i16> addrspace(1)* undef store <2 x i16> %build1, <2 x i16> addrspace(1)* undef
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/local-stack-slot-offset.ll

;RUN: llc < %s -march=amdgcn -mcpu=verde -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ;RUN: llc < %s -march=amdgcn -mcpu=verde -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
;RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK ;RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -mattr=+vgpr-spilling -mattr=-promote-alloca -verify-machineinstrs | FileCheck %s -check-prefix=CHECK
; Allocate two stack slots of 2052 bytes each requiring a total of 4104 bytes. ; Allocate two stack slots of 2052 bytes each requiring a total of 4104 bytes.
; Extracting the last element of each does not fit into the offset field of ; Extracting the last element of each does not fit into the offset field of
; MUBUF instructions, so a new base register is needed. This used to not ; MUBUF instructions, so a new base register is needed. This used to not
; happen, leading to an assertion. ; happen, leading to an assertion.
; CHECK-LABEL: {{^}}main: ; CHECK-LABEL: {{^}}main:
; CHECK: buffer_store_dword ; CHECK: buffer_store_dword
; CHECK: buffer_store_dword ; CHECK: buffer_store_dword
; CHECK: buffer_load_dword ; CHECK: buffer_load_dword
; CHECK: buffer_load_dword ; CHECK: buffer_load_dword
define amdgpu_gs float @main(float %v1, float %v2, i32 %idx1, i32 %idx2) { define amdgpu_gs float @main(float %v1, float %v2, i32 %idx1, i32 %idx2) {
main_body: main_body:
%m1 = alloca [513 x float] %m1 = alloca [513 x float], addrspace(5)
%m2 = alloca [513 x float] %m2 = alloca [513 x float], addrspace(5)
%gep1.store = getelementptr [513 x float], [513 x float]* %m1, i32 0, i32 %idx1 %gep1.store = getelementptr [513 x float], [513 x float] addrspace(5)* %m1, i32 0, i32 %idx1
store float %v1, float* %gep1.store store float %v1, float addrspace(5)* %gep1.store
%gep2.store = getelementptr [513 x float], [513 x float]* %m2, i32 0, i32 %idx2 %gep2.store = getelementptr [513 x float], [513 x float] addrspace(5)* %m2, i32 0, i32 %idx2
store float %v2, float* %gep2.store store float %v2, float addrspace(5)* %gep2.store
; This used to use a base reg equal to 0. ; This used to use a base reg equal to 0.
%gep1.load = getelementptr [513 x float], [513 x float]* %m1, i32 0, i32 0 %gep1.load = getelementptr [513 x float], [513 x float] addrspace(5)* %m1, i32 0, i32 0
%out1 = load float, float* %gep1.load %out1 = load float, float addrspace(5)* %gep1.load
; This used to attempt to re-use the base reg at 0, generating an out-of-bounds instruction offset. ; This used to attempt to re-use the base reg at 0, generating an out-of-bounds instruction offset.
%gep2.load = getelementptr [513 x float], [513 x float]* %m2, i32 0, i32 512 %gep2.load = getelementptr [513 x float], [513 x float] addrspace(5)* %m2, i32 0, i32 512
%out2 = load float, float* %gep2.load %out2 = load float, float addrspace(5)* %gep2.load
%r = fadd float %out1, %out2 %r = fadd float %out1, %out2
ret float %r ret float %r
} }

test/CodeGen/AMDGPU/memory-legalizer-atomic-cmpxchg.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}system_monotonic_monotonic ; CHECK-LABEL: {{^}}system_monotonic_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_monotonic_monotonic( define amdgpu_kernel void @system_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in monotonic monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}system_acquire_monotonic ; CHECK-LABEL: {{^}}system_acquire_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acquire_monotonic( define amdgpu_kernel void @system_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acquire monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}system_release_monotonic ; CHECK-LABEL: {{^}}system_release_monotonic
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_release_monotonic( define amdgpu_kernel void @system_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in release monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}system_acq_rel_monotonic ; CHECK-LABEL: {{^}}system_acq_rel_monotonic
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acq_rel_monotonic( define amdgpu_kernel void @system_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acq_rel monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}system_seq_cst_monotonic ; CHECK-LABEL: {{^}}system_seq_cst_monotonic
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst_monotonic( define amdgpu_kernel void @system_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}system_acquire_acquire ; CHECK-LABEL: {{^}}system_acquire_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acquire_acquire( define amdgpu_kernel void @system_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acquire acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}system_release_acquire ; CHECK-LABEL: {{^}}system_release_acquire
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_release_acquire( define amdgpu_kernel void @system_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in release acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}system_acq_rel_acquire ; CHECK-LABEL: {{^}}system_acq_rel_acquire
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acq_rel_acquire( define amdgpu_kernel void @system_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in acq_rel acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}system_seq_cst_acquire ; CHECK-LABEL: {{^}}system_seq_cst_acquire
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst_acquire( define amdgpu_kernel void @system_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}system_seq_cst_seq_cst ; CHECK-LABEL: {{^}}system_seq_cst_seq_cst
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst_seq_cst( define amdgpu_kernel void @system_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in seq_cst seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_monotonic_monotonic ; CHECK-LABEL: {{^}}singlethread_monotonic_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_monotonic_monotonic( define amdgpu_kernel void @singlethread_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") monotonic monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_acquire_monotonic ; CHECK-LABEL: {{^}}singlethread_acquire_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acquire_monotonic( define amdgpu_kernel void @singlethread_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acquire monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_release_monotonic ; CHECK-LABEL: {{^}}singlethread_release_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_release_monotonic( define amdgpu_kernel void @singlethread_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") release monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_acq_rel_monotonic ; CHECK-LABEL: {{^}}singlethread_acq_rel_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acq_rel_monotonic( define amdgpu_kernel void @singlethread_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_seq_cst_monotonic ; CHECK-LABEL: {{^}}singlethread_seq_cst_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst_monotonic( define amdgpu_kernel void @singlethread_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_acquire_acquire ; CHECK-LABEL: {{^}}singlethread_acquire_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acquire_acquire( define amdgpu_kernel void @singlethread_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acquire acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_release_acquire ; CHECK-LABEL: {{^}}singlethread_release_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_release_acquire( define amdgpu_kernel void @singlethread_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") release acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_acq_rel_acquire ; CHECK-LABEL: {{^}}singlethread_acq_rel_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acq_rel_acquire( define amdgpu_kernel void @singlethread_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") acq_rel acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_seq_cst_acquire ; CHECK-LABEL: {{^}}singlethread_seq_cst_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst_acquire( define amdgpu_kernel void @singlethread_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_seq_cst_seq_cst ; CHECK-LABEL: {{^}}singlethread_seq_cst_seq_cst
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst_seq_cst( define amdgpu_kernel void @singlethread_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("singlethread") seq_cst seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_monotonic_monotonic ; CHECK-LABEL: {{^}}agent_monotonic_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_monotonic_monotonic( define amdgpu_kernel void @agent_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") monotonic monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_acquire_monotonic ; CHECK-LABEL: {{^}}agent_acquire_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acquire_monotonic( define amdgpu_kernel void @agent_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acquire monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_release_monotonic ; CHECK-LABEL: {{^}}agent_release_monotonic
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_release_monotonic( define amdgpu_kernel void @agent_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") release monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_acq_rel_monotonic ; CHECK-LABEL: {{^}}agent_acq_rel_monotonic
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acq_rel_monotonic( define amdgpu_kernel void @agent_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acq_rel monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_seq_cst_monotonic ; CHECK-LABEL: {{^}}agent_seq_cst_monotonic
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst_monotonic( define amdgpu_kernel void @agent_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") seq_cst monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_acquire_acquire ; CHECK-LABEL: {{^}}agent_acquire_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acquire_acquire( define amdgpu_kernel void @agent_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acquire acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_release_acquire ; CHECK-LABEL: {{^}}agent_release_acquire
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_release_acquire( define amdgpu_kernel void @agent_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") release acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_acq_rel_acquire ; CHECK-LABEL: {{^}}agent_acq_rel_acquire
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acq_rel_acquire( define amdgpu_kernel void @agent_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") acq_rel acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_seq_cst_acquire ; CHECK-LABEL: {{^}}agent_seq_cst_acquire
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst_acquire( define amdgpu_kernel void @agent_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") seq_cst acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_seq_cst_seq_cst ; CHECK-LABEL: {{^}}agent_seq_cst_seq_cst
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK-NEXT: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst_seq_cst( define amdgpu_kernel void @agent_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("agent") seq_cst seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_monotonic_monotonic ; CHECK-LABEL: {{^}}workgroup_monotonic_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_monotonic_monotonic( define amdgpu_kernel void @workgroup_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") monotonic monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_acquire_monotonic ; CHECK-LABEL: {{^}}workgroup_acquire_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acquire_monotonic( define amdgpu_kernel void @workgroup_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acquire monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_release_monotonic ; CHECK-LABEL: {{^}}workgroup_release_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_release_monotonic( define amdgpu_kernel void @workgroup_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") release monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_acq_rel_monotonic ; CHECK-LABEL: {{^}}workgroup_acq_rel_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acq_rel_monotonic( define amdgpu_kernel void @workgroup_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_seq_cst_monotonic ; CHECK-LABEL: {{^}}workgroup_seq_cst_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst_monotonic( define amdgpu_kernel void @workgroup_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_acquire_acquire ; CHECK-LABEL: {{^}}workgroup_acquire_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acquire_acquire( define amdgpu_kernel void @workgroup_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acquire acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_release_acquire ; CHECK-LABEL: {{^}}workgroup_release_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_release_acquire( define amdgpu_kernel void @workgroup_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") release acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_acq_rel_acquire ; CHECK-LABEL: {{^}}workgroup_acq_rel_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acq_rel_acquire( define amdgpu_kernel void @workgroup_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") acq_rel acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_seq_cst_acquire ; CHECK-LABEL: {{^}}workgroup_seq_cst_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst_acquire( define amdgpu_kernel void @workgroup_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_seq_cst_seq_cst ; CHECK-LABEL: {{^}}workgroup_seq_cst_seq_cst
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst_seq_cst( define amdgpu_kernel void @workgroup_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("workgroup") seq_cst seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_monotonic_monotonic ; CHECK-LABEL: {{^}}wavefront_monotonic_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_monotonic_monotonic( define amdgpu_kernel void @wavefront_monotonic_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") monotonic monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") monotonic monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_acquire_monotonic ; CHECK-LABEL: {{^}}wavefront_acquire_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acquire_monotonic( define amdgpu_kernel void @wavefront_acquire_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acquire monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acquire monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_release_monotonic ; CHECK-LABEL: {{^}}wavefront_release_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_release_monotonic( define amdgpu_kernel void @wavefront_release_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") release monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") release monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_acq_rel_monotonic ; CHECK-LABEL: {{^}}wavefront_acq_rel_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acq_rel_monotonic( define amdgpu_kernel void @wavefront_acq_rel_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_seq_cst_monotonic ; CHECK-LABEL: {{^}}wavefront_seq_cst_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst_monotonic( define amdgpu_kernel void @wavefront_seq_cst_monotonic(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst monotonic %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_acquire_acquire ; CHECK-LABEL: {{^}}wavefront_acquire_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acquire_acquire( define amdgpu_kernel void @wavefront_acquire_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acquire acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acquire acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_release_acquire ; CHECK-LABEL: {{^}}wavefront_release_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_release_acquire( define amdgpu_kernel void @wavefront_release_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") release acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") release acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_acq_rel_acquire ; CHECK-LABEL: {{^}}wavefront_acq_rel_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acq_rel_acquire( define amdgpu_kernel void @wavefront_acq_rel_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") acq_rel acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_seq_cst_acquire ; CHECK-LABEL: {{^}}wavefront_seq_cst_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst_acquire( define amdgpu_kernel void @wavefront_seq_cst_acquire(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst acquire %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_seq_cst_seq_cst ; CHECK-LABEL: {{^}}wavefront_seq_cst_seq_cst
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; CHECK: flat_atomic_cmpswap v[{{[0-9]+\:[0-9]+}}], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst_seq_cst( define amdgpu_kernel void @wavefront_seq_cst_seq_cst(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("wavefront") seq_cst seq_cst
ret void ret void
} }

test/CodeGen/AMDGPU/memory-legalizer-atomic-rmw.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck %s
; CHECK-LABEL: {{^}}system_monotonic ; CHECK-LABEL: {{^}}system_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_monotonic( define amdgpu_kernel void @system_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}system_acquire ; CHECK-LABEL: {{^}}system_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acquire( define amdgpu_kernel void @system_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in acquire %val = atomicrmw volatile xchg i32* %out, i32 %in acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}system_release ; CHECK-LABEL: {{^}}system_release
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_release( define amdgpu_kernel void @system_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in release %val = atomicrmw volatile xchg i32* %out, i32 %in release
ret void ret void
} }
; CHECK-LABEL: {{^}}system_acq_rel ; CHECK-LABEL: {{^}}system_acq_rel
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_acq_rel( define amdgpu_kernel void @system_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in acq_rel
ret void ret void
} }
; CHECK-LABEL: {{^}}system_seq_cst ; CHECK-LABEL: {{^}}system_seq_cst
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @system_seq_cst( define amdgpu_kernel void @system_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_monotonic ; CHECK-LABEL: {{^}}singlethread_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_monotonic( define amdgpu_kernel void @singlethread_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_acquire ; CHECK-LABEL: {{^}}singlethread_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acquire( define amdgpu_kernel void @singlethread_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_release ; CHECK-LABEL: {{^}}singlethread_release
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_release( define amdgpu_kernel void @singlethread_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") release
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_acq_rel ; CHECK-LABEL: {{^}}singlethread_acq_rel
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_acq_rel( define amdgpu_kernel void @singlethread_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") acq_rel
ret void ret void
} }
; CHECK-LABEL: {{^}}singlethread_seq_cst ; CHECK-LABEL: {{^}}singlethread_seq_cst
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @singlethread_seq_cst( define amdgpu_kernel void @singlethread_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("singlethread") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("singlethread") seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_monotonic ; CHECK-LABEL: {{^}}agent_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_monotonic( define amdgpu_kernel void @agent_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_acquire ; CHECK-LABEL: {{^}}agent_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acquire( define amdgpu_kernel void @agent_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_release ; CHECK-LABEL: {{^}}agent_release
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_release( define amdgpu_kernel void @agent_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") release
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_acq_rel ; CHECK-LABEL: {{^}}agent_acq_rel
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_acq_rel( define amdgpu_kernel void @agent_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") acq_rel
ret void ret void
} }
; CHECK-LABEL: {{^}}agent_seq_cst ; CHECK-LABEL: {{^}}agent_seq_cst
; CHECK: s_waitcnt vmcnt(0){{$}} ; CHECK: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK-NEXT: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NEXT: s_waitcnt vmcnt(0){{$}} ; CHECK-NEXT: s_waitcnt vmcnt(0){{$}}
; CHECK-NEXT: buffer_wbinvl1_vol ; CHECK-NEXT: buffer_wbinvl1_vol
define amdgpu_kernel void @agent_seq_cst( define amdgpu_kernel void @agent_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("agent") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("agent") seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_monotonic ; CHECK-LABEL: {{^}}workgroup_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_monotonic( define amdgpu_kernel void @workgroup_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_acquire ; CHECK-LABEL: {{^}}workgroup_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acquire( define amdgpu_kernel void @workgroup_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_release ; CHECK-LABEL: {{^}}workgroup_release
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_release( define amdgpu_kernel void @workgroup_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") release
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_acq_rel ; CHECK-LABEL: {{^}}workgroup_acq_rel
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_acq_rel( define amdgpu_kernel void @workgroup_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") acq_rel
ret void ret void
} }
; CHECK-LABEL: {{^}}workgroup_seq_cst ; CHECK-LABEL: {{^}}workgroup_seq_cst
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @workgroup_seq_cst( define amdgpu_kernel void @workgroup_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("workgroup") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("workgroup") seq_cst
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_monotonic ; CHECK-LABEL: {{^}}wavefront_monotonic
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_monotonic( define amdgpu_kernel void @wavefront_monotonic(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") monotonic %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") monotonic
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_acquire ; CHECK-LABEL: {{^}}wavefront_acquire
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acquire( define amdgpu_kernel void @wavefront_acquire(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") acquire %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") acquire
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_release ; CHECK-LABEL: {{^}}wavefront_release
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_release( define amdgpu_kernel void @wavefront_release(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") release %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") release
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_acq_rel ; CHECK-LABEL: {{^}}wavefront_acq_rel
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_acq_rel( define amdgpu_kernel void @wavefront_acq_rel(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") acq_rel %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") acq_rel
ret void ret void
} }
; CHECK-LABEL: {{^}}wavefront_seq_cst ; CHECK-LABEL: {{^}}wavefront_seq_cst
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}} ; CHECK: flat_atomic_swap v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}{{$}}
; CHECK-NOT: s_waitcnt vmcnt(0){{$}} ; CHECK-NOT: s_waitcnt vmcnt(0){{$}}
; CHECK-NOT: buffer_wbinvl1_vol ; CHECK-NOT: buffer_wbinvl1_vol
define amdgpu_kernel void @wavefront_seq_cst( define amdgpu_kernel void @wavefront_seq_cst(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("wavefront") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("wavefront") seq_cst
ret void ret void
} }

test/CodeGen/AMDGPU/memory-legalizer-invalid-syncscope.ll

; RUN: not llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s
; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s ; RUN: not llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s 2>&1 | FileCheck %s
; CHECK: error: <unknown>:0:0: in function invalid_fence void (): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_fence void (): Unsupported synchronization scope
define amdgpu_kernel void @invalid_fence() { define amdgpu_kernel void @invalid_fence() {
entry: entry:
fence syncscope("invalid") seq_cst fence syncscope("invalid") seq_cst
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_load void (i32 addrspace(4)*, i32 addrspace(4)*): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_load void (i32*, i32*): Unsupported synchronization scope
define amdgpu_kernel void @invalid_load( define amdgpu_kernel void @invalid_load(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("invalid") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("invalid") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_store void (i32, i32 addrspace(4)*): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_store void (i32, i32*): Unsupported synchronization scope
define amdgpu_kernel void @invalid_store( define amdgpu_kernel void @invalid_store(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("invalid") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("invalid") seq_cst, align 4
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_cmpxchg void (i32 addrspace(4)*, i32, i32): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_cmpxchg void (i32*, i32, i32): Unsupported synchronization scope
define amdgpu_kernel void @invalid_cmpxchg( define amdgpu_kernel void @invalid_cmpxchg(
i32 addrspace(4)* %out, i32 %in, i32 %old) { i32* %out, i32 %in, i32 %old) {
entry: entry:
%gep = getelementptr i32, i32 addrspace(4)* %out, i32 4 %gep = getelementptr i32, i32* %out, i32 4
%val = cmpxchg volatile i32 addrspace(4)* %gep, i32 %old, i32 %in syncscope("invalid") seq_cst seq_cst %val = cmpxchg volatile i32* %gep, i32 %old, i32 %in syncscope("invalid") seq_cst seq_cst
ret void ret void
} }
; CHECK: error: <unknown>:0:0: in function invalid_rmw void (i32 addrspace(4)*, i32): Unsupported synchronization scope ; CHECK: error: <unknown>:0:0: in function invalid_rmw void (i32*, i32): Unsupported synchronization scope
define amdgpu_kernel void @invalid_rmw( define amdgpu_kernel void @invalid_rmw(
i32 addrspace(4)* %out, i32 %in) { i32* %out, i32 %in) {
entry: entry:
%val = atomicrmw volatile xchg i32 addrspace(4)* %out, i32 %in syncscope("invalid") seq_cst %val = atomicrmw volatile xchg i32* %out, i32 %in syncscope("invalid") seq_cst
ret void ret void
} }

test/CodeGen/AMDGPU/memory-legalizer-load.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
; GCN-LABEL: {{^}}system_unordered ; GCN-LABEL: {{^}}system_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_unordered( define amdgpu_kernel void @system_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in unordered, align 4 %val = load atomic i32, i32* %in unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}system_monotonic ; GCN-LABEL: {{^}}system_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_monotonic( define amdgpu_kernel void @system_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in monotonic, align 4 %val = load atomic i32, i32* %in monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}system_acquire ; GCN-LABEL: {{^}}system_acquire
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GCN-NEXT: s_waitcnt vmcnt(0){{$}} ; GCN-NEXT: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_acquire( define amdgpu_kernel void @system_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in acquire, align 4 %val = load atomic i32, i32* %in acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}system_seq_cst ; GCN-LABEL: {{^}}system_seq_cst
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; GCN-NEXT: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GCN-NEXT: s_waitcnt vmcnt(0){{$}} ; GCN-NEXT: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @system_seq_cst( define amdgpu_kernel void @system_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in seq_cst, align 4 %val = load atomic i32, i32* %in seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_unordered ; GCN-LABEL: {{^}}singlethread_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_unordered( define amdgpu_kernel void @singlethread_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") unordered, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_monotonic ; GCN-LABEL: {{^}}singlethread_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_monotonic( define amdgpu_kernel void @singlethread_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_acquire ; GCN-LABEL: {{^}}singlethread_acquire
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_acquire( define amdgpu_kernel void @singlethread_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") acquire, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_seq_cst ; GCN-LABEL: {{^}}singlethread_seq_cst
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @singlethread_seq_cst( define amdgpu_kernel void @singlethread_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("singlethread") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("singlethread") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}agent_unordered ; GCN-LABEL: {{^}}agent_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_unordered( define amdgpu_kernel void @agent_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") unordered, align 4 %val = load atomic i32, i32* %in syncscope("agent") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}agent_monotonic ; GCN-LABEL: {{^}}agent_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_monotonic( define amdgpu_kernel void @agent_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("agent") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}agent_acquire ; GCN-LABEL: {{^}}agent_acquire
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GCN-NEXT: s_waitcnt vmcnt(0){{$}} ; GCN-NEXT: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_acquire( define amdgpu_kernel void @agent_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") acquire, align 4 %val = load atomic i32, i32* %in syncscope("agent") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}agent_seq_cst ; GCN-LABEL: {{^}}agent_seq_cst
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}} ; GCN-NEXT: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}] glc{{$}}
; GCN-NEXT: s_waitcnt vmcnt(0){{$}} ; GCN-NEXT: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: buffer_wbinvl1_vol ; GCN-NEXT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @agent_seq_cst( define amdgpu_kernel void @agent_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("agent") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("agent") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_unordered ; GCN-LABEL: {{^}}workgroup_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_unordered( define amdgpu_kernel void @workgroup_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") unordered, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_monotonic ; GCN-LABEL: {{^}}workgroup_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_monotonic( define amdgpu_kernel void @workgroup_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_acquire ; GCN-LABEL: {{^}}workgroup_acquire
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_acquire( define amdgpu_kernel void @workgroup_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") acquire, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_seq_cst ; GCN-LABEL: {{^}}workgroup_seq_cst
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @workgroup_seq_cst( define amdgpu_kernel void @workgroup_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("workgroup") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("workgroup") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_unordered ; GCN-LABEL: {{^}}wavefront_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_unordered( define amdgpu_kernel void @wavefront_unordered(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") unordered, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") unordered, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_monotonic ; GCN-LABEL: {{^}}wavefront_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_monotonic( define amdgpu_kernel void @wavefront_monotonic(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") monotonic, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") monotonic, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_acquire ; GCN-LABEL: {{^}}wavefront_acquire
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_acquire( define amdgpu_kernel void @wavefront_acquire(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") acquire, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") acquire, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_seq_cst ; GCN-LABEL: {{^}}wavefront_seq_cst
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}} ; GCN: flat_load_dword [[RET:v[0-9]+]], v[{{[0-9]+}}:{{[0-9]+}}]{{$}}
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN-NOT: buffer_wbinvl1_vol ; GCN-NOT: buffer_wbinvl1_vol
; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]] ; GCN: flat_store_dword v{{\[[0-9]+:[0-9]+\]}}, [[RET]]
define amdgpu_kernel void @wavefront_seq_cst( define amdgpu_kernel void @wavefront_seq_cst(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load atomic i32, i32 addrspace(4)* %in syncscope("wavefront") seq_cst, align 4 %val = load atomic i32, i32* %in syncscope("wavefront") seq_cst, align 4
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_0 ; GCN-LABEL: {{^}}nontemporal_private_0
; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_0( define amdgpu_kernel void @nontemporal_private_0(
i32* %in, i32 addrspace(4)* %out) { i32 addrspace(5)* %in, i32* %out) {
entry: entry:
%val = load i32, i32* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(5)* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_1 ; GCN-LABEL: {{^}}nontemporal_private_1
; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_1( define amdgpu_kernel void @nontemporal_private_1(
i32* %in, i32 addrspace(4)* %out) { i32 addrspace(5)* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(5)* %in, i32 %tid
%val = load i32, i32* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(5)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_0 ; GCN-LABEL: {{^}}nontemporal_global_0
; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0x0{{$}} ; GCN: s_load_dword s{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], 0x0{{$}}
define amdgpu_kernel void @nontemporal_global_0( define amdgpu_kernel void @nontemporal_global_0(
i32 addrspace(1)* %in, i32 addrspace(4)* %out) { i32 addrspace(1)* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(1)* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_1 ; GCN-LABEL: {{^}}nontemporal_global_1
; GFX8: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GFX8: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
; GFX9: global_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], off glc slc{{$}} ; GFX9: global_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}], off glc slc{{$}}
define amdgpu_kernel void @nontemporal_global_1( define amdgpu_kernel void @nontemporal_global_1(
i32 addrspace(1)* %in, i32 addrspace(4)* %out) { i32 addrspace(1)* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 %tid
%val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(1)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_0 ; GCN-LABEL: {{^}}nontemporal_local_0
; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_0( define amdgpu_kernel void @nontemporal_local_0(
i32 addrspace(3)* %in, i32 addrspace(4)* %out) { i32 addrspace(3)* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0 %val = load i32, i32 addrspace(3)* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_1 ; GCN-LABEL: {{^}}nontemporal_local_1
; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_read_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_1( define amdgpu_kernel void @nontemporal_local_1(
i32 addrspace(3)* %in, i32 addrspace(4)* %out) { i32 addrspace(3)* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32 addrspace(3)* %in, i32 %tid
%val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32 addrspace(3)* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_0 ; GCN-LABEL: {{^}}nontemporal_flat_0
; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_0( define amdgpu_kernel void @nontemporal_flat_0(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4, !nontemporal !0 %val = load i32, i32* %in, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_1 ; GCN-LABEL: {{^}}nontemporal_flat_1
; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}} ; GCN: flat_load_dword v{{[0-9]+}}, v[{{[0-9]+}}:{{[0-9]+}}] glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_1( define amdgpu_kernel void @nontemporal_flat_1(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val.gep = getelementptr inbounds i32, i32 addrspace(4)* %in, i32 %tid %val.gep = getelementptr inbounds i32, i32* %in, i32 %tid
%val = load i32, i32 addrspace(4)* %val.gep, align 4, !nontemporal !0 %val = load i32, i32* %val.gep, align 4, !nontemporal !0
store i32 %val, i32 addrspace(4)* %out store i32 %val, i32* %out
ret void ret void
} }
!0 = !{i32 1} !0 = !{i32 1}

test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-atomics.mir

# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
--- | --- |
; ModuleID = 'memory-legalizer-multiple-mem-operands.ll' ; ModuleID = 'memory-legalizer-multiple-mem-operands.ll'
source_filename = "memory-legalizer-multiple-mem-operands.ll" source_filename = "memory-legalizer-multiple-mem-operands.ll"
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 { define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
entry: entry:
%scratch0 = alloca [8192 x i32] %scratch0 = alloca [8192 x i32], addrspace(5)
%scratch1 = alloca [8192 x i32] %scratch1 = alloca [8192 x i32], addrspace(5)
%scratchptr01 = bitcast [8192 x i32]* %scratch0 to i32* %scratchptr01 = bitcast [8192 x i32] addrspace(5)* %scratch0 to i32 addrspace(5)*
store i32 1, i32* %scratchptr01 store i32 1, i32 addrspace(5)* %scratchptr01
%scratchptr12 = bitcast [8192 x i32]* %scratch1 to i32* %scratchptr12 = bitcast [8192 x i32] addrspace(5)* %scratch1 to i32 addrspace(5)*
store i32 2, i32* %scratchptr12 store i32 2, i32 addrspace(5)* %scratchptr12
%cmp = icmp eq i32 %cond, 0 %cmp = icmp eq i32 %cond, 0
br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0 br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
if: ; preds = %entry if: ; preds = %entry
%if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0 %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
%if_value = load atomic i32, i32* %if_ptr syncscope("workgroup") seq_cst, align 4 %if_value = load atomic i32, i32 addrspace(5)* %if_ptr syncscope("workgroup") seq_cst, align 4
br label %done, !structurizecfg.uniform !0 br label %done, !structurizecfg.uniform !0
else: ; preds = %entry else: ; preds = %entry
%else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0 %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
%else_value = load atomic i32, i32* %else_ptr syncscope("agent") unordered, align 4 %else_value = load atomic i32, i32 addrspace(5)* %else_ptr syncscope("agent") unordered, align 4
br label %done, !structurizecfg.uniform !0 br label %done, !structurizecfg.uniform !0
done: ; preds = %else, %if done: ; preds = %else, %if
%value = phi i32 [ %if_value, %if ], [ %else_value, %else ] %value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
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test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-1.mir

# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
--- | --- |
; ModuleID = 'memory-legalizer-multiple-mem-operands.ll' ; ModuleID = 'memory-legalizer-multiple-mem-operands.ll'
source_filename = "memory-legalizer-multiple-mem-operands.ll" source_filename = "memory-legalizer-multiple-mem-operands.ll"
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 { define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
entry: entry:
%scratch0 = alloca [8192 x i32] %scratch0 = alloca [8192 x i32], addrspace(5)
%scratch1 = alloca [8192 x i32] %scratch1 = alloca [8192 x i32], addrspace(5)
%scratchptr01 = bitcast [8192 x i32]* %scratch0 to i32* %scratchptr01 = bitcast [8192 x i32] addrspace(5)* %scratch0 to i32 addrspace(5)*
store i32 1, i32* %scratchptr01 store i32 1, i32 addrspace(5)* %scratchptr01
%scratchptr12 = bitcast [8192 x i32]* %scratch1 to i32* %scratchptr12 = bitcast [8192 x i32] addrspace(5)* %scratch1 to i32 addrspace(5)*
store i32 2, i32* %scratchptr12 store i32 2, i32 addrspace(5)* %scratchptr12
%cmp = icmp eq i32 %cond, 0 %cmp = icmp eq i32 %cond, 0
br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0 br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
if: ; preds = %entry if: ; preds = %entry
%if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0 %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
%if_value = load i32, i32* %if_ptr, align 4, !nontemporal !1 %if_value = load i32, i32 addrspace(5)* %if_ptr, align 4, !nontemporal !1
br label %done, !structurizecfg.uniform !0 br label %done, !structurizecfg.uniform !0
else: ; preds = %entry else: ; preds = %entry
%else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0 %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
%else_value = load i32, i32* %else_ptr, align 4, !nontemporal !1 %else_value = load i32, i32 addrspace(5)* %else_ptr, align 4, !nontemporal !1
br label %done, !structurizecfg.uniform !0 br label %done, !structurizecfg.uniform !0
done: ; preds = %else, %if done: ; preds = %else, %if
%value = phi i32 [ %if_value, %if ], [ %else_value, %else ] %value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
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test/CodeGen/AMDGPU/memory-legalizer-multiple-mem-operands-nontemporal-2.mir

# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass si-memory-legalizer %s -o - | FileCheck %s
--- | --- |
; ModuleID = 'memory-legalizer-multiple-mem-operands.ll' ; ModuleID = 'memory-legalizer-multiple-mem-operands.ll'
source_filename = "memory-legalizer-multiple-mem-operands.ll" source_filename = "memory-legalizer-multiple-mem-operands.ll"
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64" target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 { define amdgpu_kernel void @multiple_mem_operands(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) #0 {
entry: entry:
%scratch0 = alloca [8192 x i32] %scratch0 = alloca [8192 x i32], addrspace(5)
%scratch1 = alloca [8192 x i32] %scratch1 = alloca [8192 x i32], addrspace(5)
%scratchptr01 = bitcast [8192 x i32]* %scratch0 to i32* %scratchptr01 = bitcast [8192 x i32] addrspace(5)* %scratch0 to i32 addrspace(5)*
store i32 1, i32* %scratchptr01 store i32 1, i32 addrspace(5)* %scratchptr01
%scratchptr12 = bitcast [8192 x i32]* %scratch1 to i32* %scratchptr12 = bitcast [8192 x i32] addrspace(5)* %scratch1 to i32 addrspace(5)*
store i32 2, i32* %scratchptr12 store i32 2, i32 addrspace(5)* %scratchptr12
%cmp = icmp eq i32 %cond, 0 %cmp = icmp eq i32 %cond, 0
br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0 br i1 %cmp, label %if, label %else, !structurizecfg.uniform !0, !amdgpu.uniform !0
if: ; preds = %entry if: ; preds = %entry
%if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0 %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset, !amdgpu.uniform !0
%if_value = load i32, i32* %if_ptr, align 4, !nontemporal !1 %if_value = load i32, i32 addrspace(5)* %if_ptr, align 4, !nontemporal !1
br label %done, !structurizecfg.uniform !0 br label %done, !structurizecfg.uniform !0
else: ; preds = %entry else: ; preds = %entry
%else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0 %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset, !amdgpu.uniform !0
%else_value = load i32, i32* %else_ptr, align 4 %else_value = load i32, i32 addrspace(5)* %else_ptr, align 4
br label %done, !structurizecfg.uniform !0 br label %done, !structurizecfg.uniform !0
done: ; preds = %else, %if done: ; preds = %else, %if
%value = phi i32 [ %if_value, %if ], [ %else_value, %else ] %value = phi i32 [ %if_value, %if ], [ %else_value, %else ]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
▲ Show 20 Lines • Show All 127 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/memory-legalizer-store.ll

; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX8 %s
; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd- -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck --check-prefix=GCN --check-prefix=GFX9 %s
declare i32 @llvm.amdgcn.workitem.id.x() declare i32 @llvm.amdgcn.workitem.id.x()
; GCN-LABEL: {{^}}system_unordered ; GCN-LABEL: {{^}}system_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_unordered( define amdgpu_kernel void @system_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out unordered, align 4 store atomic i32 %in, i32* %out unordered, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}system_monotonic ; GCN-LABEL: {{^}}system_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_monotonic( define amdgpu_kernel void @system_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out monotonic, align 4 store atomic i32 %in, i32* %out monotonic, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}system_release ; GCN-LABEL: {{^}}system_release
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_release( define amdgpu_kernel void @system_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out release, align 4 store atomic i32 %in, i32* %out release, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}system_seq_cst ; GCN-LABEL: {{^}}system_seq_cst
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @system_seq_cst( define amdgpu_kernel void @system_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out seq_cst, align 4 store atomic i32 %in, i32* %out seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_unordered ; GCN-LABEL: {{^}}singlethread_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_unordered( define amdgpu_kernel void @singlethread_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") unordered, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") unordered, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_monotonic ; GCN-LABEL: {{^}}singlethread_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_monotonic( define amdgpu_kernel void @singlethread_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") monotonic, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_release ; GCN-LABEL: {{^}}singlethread_release
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_release( define amdgpu_kernel void @singlethread_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") release, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") release, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}singlethread_seq_cst ; GCN-LABEL: {{^}}singlethread_seq_cst
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @singlethread_seq_cst( define amdgpu_kernel void @singlethread_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("singlethread") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("singlethread") seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}agent_unordered ; GCN-LABEL: {{^}}agent_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_unordered( define amdgpu_kernel void @agent_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") unordered, align 4 store atomic i32 %in, i32* %out syncscope("agent") unordered, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}agent_monotonic ; GCN-LABEL: {{^}}agent_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_monotonic( define amdgpu_kernel void @agent_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("agent") monotonic, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}agent_release ; GCN-LABEL: {{^}}agent_release
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_release( define amdgpu_kernel void @agent_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") release, align 4 store atomic i32 %in, i32* %out syncscope("agent") release, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}agent_seq_cst ; GCN-LABEL: {{^}}agent_seq_cst
; GCN: s_waitcnt vmcnt(0){{$}} ; GCN: s_waitcnt vmcnt(0){{$}}
; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN-NEXT: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @agent_seq_cst( define amdgpu_kernel void @agent_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("agent") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("agent") seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_unordered ; GCN-LABEL: {{^}}workgroup_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_unordered( define amdgpu_kernel void @workgroup_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") unordered, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") unordered, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_monotonic ; GCN-LABEL: {{^}}workgroup_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_monotonic( define amdgpu_kernel void @workgroup_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") monotonic, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_release ; GCN-LABEL: {{^}}workgroup_release
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_release( define amdgpu_kernel void @workgroup_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") release, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") release, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}workgroup_seq_cst ; GCN-LABEL: {{^}}workgroup_seq_cst
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @workgroup_seq_cst( define amdgpu_kernel void @workgroup_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("workgroup") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("workgroup") seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_unordered ; GCN-LABEL: {{^}}wavefront_unordered
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_unordered( define amdgpu_kernel void @wavefront_unordered(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") unordered, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") unordered, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_monotonic ; GCN-LABEL: {{^}}wavefront_monotonic
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_monotonic( define amdgpu_kernel void @wavefront_monotonic(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") monotonic, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") monotonic, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_release ; GCN-LABEL: {{^}}wavefront_release
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_release( define amdgpu_kernel void @wavefront_release(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") release, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") release, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}wavefront_seq_cst ; GCN-LABEL: {{^}}wavefront_seq_cst
; GCN-NOT: s_waitcnt vmcnt(0){{$}} ; GCN-NOT: s_waitcnt vmcnt(0){{$}}
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], {{v[0-9]+}}{{$}}
define amdgpu_kernel void @wavefront_seq_cst( define amdgpu_kernel void @wavefront_seq_cst(
i32 %in, i32 addrspace(4)* %out) { i32 %in, i32* %out) {
entry: entry:
store atomic i32 %in, i32 addrspace(4)* %out syncscope("wavefront") seq_cst, align 4 store atomic i32 %in, i32* %out syncscope("wavefront") seq_cst, align 4
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_0 ; GCN-LABEL: {{^}}nontemporal_private_0
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_0( define amdgpu_kernel void @nontemporal_private_0(
i32 addrspace(4)* %in, i32* %out) { i32* %in, i32 addrspace(5)* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32* %out, !nontemporal !0 store i32 %val, i32 addrspace(5)* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_private_1 ; GCN-LABEL: {{^}}nontemporal_private_1
; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen glc slc{{$}}
define amdgpu_kernel void @nontemporal_private_1( define amdgpu_kernel void @nontemporal_private_1(
i32 addrspace(4)* %in, i32* %out) { i32* %in, i32 addrspace(5)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(5)* %out, i32 %tid
store i32 %val, i32* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(5)* %out.gep, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_0 ; GCN-LABEL: {{^}}nontemporal_global_0
; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}} ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
define amdgpu_kernel void @nontemporal_global_0( define amdgpu_kernel void @nontemporal_global_0(
i32 addrspace(4)* %in, i32 addrspace(1)* %out) { i32* %in, i32 addrspace(1)* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32 addrspace(1)* %out, !nontemporal !0 store i32 %val, i32 addrspace(1)* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_global_1 ; GCN-LABEL: {{^}}nontemporal_global_1
; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GFX8: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}} ; GFX9: global_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}}, off glc slc{{$}}
define amdgpu_kernel void @nontemporal_global_1( define amdgpu_kernel void @nontemporal_global_1(
i32 addrspace(4)* %in, i32 addrspace(1)* %out) { i32* %in, i32 addrspace(1)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 %tid
store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(1)* %out.gep, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_0 ; GCN-LABEL: {{^}}nontemporal_local_0
; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_0( define amdgpu_kernel void @nontemporal_local_0(
i32 addrspace(4)* %in, i32 addrspace(3)* %out) { i32* %in, i32 addrspace(3)* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32 addrspace(3)* %out, !nontemporal !0 store i32 %val, i32 addrspace(3)* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_local_1 ; GCN-LABEL: {{^}}nontemporal_local_1
; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}} ; GCN: ds_write_b32 v{{[0-9]+}}, v{{[0-9]+}}{{$}}
define amdgpu_kernel void @nontemporal_local_1( define amdgpu_kernel void @nontemporal_local_1(
i32 addrspace(4)* %in, i32 addrspace(3)* %out) { i32* %in, i32 addrspace(3)* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32 addrspace(3)* %out, i32 %tid
store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0 store i32 %val, i32 addrspace(3)* %out.gep, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_0 ; GCN-LABEL: {{^}}nontemporal_flat_0
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_0( define amdgpu_kernel void @nontemporal_flat_0(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
store i32 %val, i32 addrspace(4)* %out, !nontemporal !0 store i32 %val, i32* %out, !nontemporal !0
ret void ret void
} }
; GCN-LABEL: {{^}}nontemporal_flat_1 ; GCN-LABEL: {{^}}nontemporal_flat_1
; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}} ; GCN: flat_store_dword v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} glc slc{{$}}
define amdgpu_kernel void @nontemporal_flat_1( define amdgpu_kernel void @nontemporal_flat_1(
i32 addrspace(4)* %in, i32 addrspace(4)* %out) { i32* %in, i32* %out) {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%val = load i32, i32 addrspace(4)* %in, align 4 %val = load i32, i32* %in, align 4
%out.gep = getelementptr inbounds i32, i32 addrspace(4)* %out, i32 %tid %out.gep = getelementptr inbounds i32, i32* %out, i32 %tid
store i32 %val, i32 addrspace(4)* %out.gep, !nontemporal !0 store i32 %val, i32* %out.gep, !nontemporal !0
ret void ret void
} }
!0 = !{i32 1} !0 = !{i32 1}

test/CodeGen/AMDGPU/move-to-valu-worklist.ll

; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck --check-prefix=GCN %s
; In moveToVALU(), move to vector ALU is performed, all instrs in ; In moveToVALU(), move to vector ALU is performed, all instrs in
; the use chain will be visited. We do not want the same node to be ; the use chain will be visited. We do not want the same node to be
; pushed to the visit worklist more than once. ; pushed to the visit worklist more than once.
; GCN-LABEL: {{^}}in_worklist_once: ; GCN-LABEL: {{^}}in_worklist_once:
; GCN: buffer_load_dword ; GCN: buffer_load_dword
; GCN: BB0_1: ; GCN: BB0_1:
; GCN: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NEXT: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN-NEXT: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN-NEXT: v_and_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @in_worklist_once() #0 { define amdgpu_kernel void @in_worklist_once() #0 {
bb: bb:
%tmp = load i64, i64* undef %tmp = load i64, i64 addrspace(5)* undef
br label %bb1 br label %bb1
bb1: ; preds = %bb1, %bb bb1: ; preds = %bb1, %bb
%tmp2 = phi i64 [ undef, %bb ], [ %tmp16, %bb1 ] %tmp2 = phi i64 [ undef, %bb ], [ %tmp16, %bb1 ]
%tmp3 = phi i64 [ %tmp, %bb ], [ undef, %bb1 ] %tmp3 = phi i64 [ %tmp, %bb ], [ undef, %bb1 ]
%tmp11 = shl i64 %tmp2, 14 %tmp11 = shl i64 %tmp2, 14
%tmp13 = xor i64 %tmp11, %tmp2 %tmp13 = xor i64 %tmp11, %tmp2
%tmp15 = and i64 %tmp3, %tmp13 %tmp15 = and i64 %tmp3, %tmp13
%tmp16 = xor i64 %tmp15, %tmp3 %tmp16 = xor i64 %tmp15, %tmp3
br label %bb1 br label %bb1
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/mubuf-offset-private.ll

; RUN: llc -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s ; RUN: llc -march=amdgcn -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s ; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SICIVI %s
; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=+max-private-element-size-16 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; Test addressing modes when the scratch base is not a frame index. ; Test addressing modes when the scratch base is not a frame index.
; GCN-LABEL: {{^}}store_private_offset_i8: ; GCN-LABEL: {{^}}store_private_offset_i8:
; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_i8() #0 { define amdgpu_kernel void @store_private_offset_i8() #0 {
store volatile i8 5, i8* inttoptr (i32 8 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i16: ; GCN-LABEL: {{^}}store_private_offset_i16:
; GCN: buffer_store_short v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_short v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_i16() #0 { define amdgpu_kernel void @store_private_offset_i16() #0 {
store volatile i16 5, i16* inttoptr (i32 8 to i16*) store volatile i16 5, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i32: ; GCN-LABEL: {{^}}store_private_offset_i32:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_i32() #0 { define amdgpu_kernel void @store_private_offset_i32() #0 {
store volatile i32 5, i32* inttoptr (i32 8 to i32*) store volatile i32 5, i32 addrspace(5)* inttoptr (i32 8 to i32 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_v2i32: ; GCN-LABEL: {{^}}store_private_offset_v2i32:
; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_v2i32() #0 { define amdgpu_kernel void @store_private_offset_v2i32() #0 {
store volatile <2 x i32> <i32 5, i32 10>, <2 x i32>* inttoptr (i32 8 to <2 x i32>*) store volatile <2 x i32> <i32 5, i32 10>, <2 x i32> addrspace(5)* inttoptr (i32 8 to <2 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_v4i32: ; GCN-LABEL: {{^}}store_private_offset_v4i32:
; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_store_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @store_private_offset_v4i32() #0 { define amdgpu_kernel void @store_private_offset_v4i32() #0 {
store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, <4 x i32>* inttoptr (i32 8 to <4 x i32>*) store volatile <4 x i32> <i32 5, i32 10, i32 15, i32 0>, <4 x i32> addrspace(5)* inttoptr (i32 8 to <4 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_i8: ; GCN-LABEL: {{^}}load_private_offset_i8:
; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_i8() #0 { define amdgpu_kernel void @load_private_offset_i8() #0 {
%load = load volatile i8, i8* inttoptr (i32 8 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}sextload_private_offset_i8: ; GCN-LABEL: {{^}}sextload_private_offset_i8:
; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_sbyte v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @sextload_private_offset_i8(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @sextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
%load = load volatile i8, i8* inttoptr (i32 8 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
%sextload = sext i8 %load to i32 %sextload = sext i8 %load to i32
store i32 %sextload, i32 addrspace(1)* undef store i32 %sextload, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}zextload_private_offset_i8: ; GCN-LABEL: {{^}}zextload_private_offset_i8:
; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_ubyte v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @zextload_private_offset_i8(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @zextload_private_offset_i8(i32 addrspace(1)* %out) #0 {
%load = load volatile i8, i8* inttoptr (i32 8 to i8*) %load = load volatile i8, i8 addrspace(5)* inttoptr (i32 8 to i8 addrspace(5)*)
%zextload = zext i8 %load to i32 %zextload = zext i8 %load to i32
store i32 %zextload, i32 addrspace(1)* undef store i32 %zextload, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_i16: ; GCN-LABEL: {{^}}load_private_offset_i16:
; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_i16() #0 { define amdgpu_kernel void @load_private_offset_i16() #0 {
%load = load volatile i16, i16* inttoptr (i32 8 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}sextload_private_offset_i16: ; GCN-LABEL: {{^}}sextload_private_offset_i16:
; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_sshort v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @sextload_private_offset_i16(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @sextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
%load = load volatile i16, i16* inttoptr (i32 8 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
%sextload = sext i16 %load to i32 %sextload = sext i16 %load to i32
store i32 %sextload, i32 addrspace(1)* undef store i32 %sextload, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}zextload_private_offset_i16: ; GCN-LABEL: {{^}}zextload_private_offset_i16:
; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s8 offset:8 ; GCN: buffer_load_ushort v{{[0-9]+}}, off, s[4:7], s8 offset:8
define amdgpu_kernel void @zextload_private_offset_i16(i32 addrspace(1)* %out) #0 { define amdgpu_kernel void @zextload_private_offset_i16(i32 addrspace(1)* %out) #0 {
%load = load volatile i16, i16* inttoptr (i32 8 to i16*) %load = load volatile i16, i16 addrspace(5)* inttoptr (i32 8 to i16 addrspace(5)*)
%zextload = zext i16 %load to i32 %zextload = zext i16 %load to i32
store i32 %zextload, i32 addrspace(1)* undef store i32 %zextload, i32 addrspace(1)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_i32: ; GCN-LABEL: {{^}}load_private_offset_i32:
; GCN: buffer_load_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_dword v{{[0-9]+}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_i32() #0 { define amdgpu_kernel void @load_private_offset_i32() #0 {
%load = load volatile i32, i32* inttoptr (i32 8 to i32*) %load = load volatile i32, i32 addrspace(5)* inttoptr (i32 8 to i32 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_v2i32: ; GCN-LABEL: {{^}}load_private_offset_v2i32:
; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_v2i32() #0 { define amdgpu_kernel void @load_private_offset_v2i32() #0 {
%load = load volatile <2 x i32>, <2 x i32>* inttoptr (i32 8 to <2 x i32>*) %load = load volatile <2 x i32>, <2 x i32> addrspace(5)* inttoptr (i32 8 to <2 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_private_offset_v4i32: ; GCN-LABEL: {{^}}load_private_offset_v4i32:
; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8 ; GCN: buffer_load_dwordx4 v{{\[[0-9]+:[0-9]+\]}}, off, s[4:7], s2 offset:8
define amdgpu_kernel void @load_private_offset_v4i32() #0 { define amdgpu_kernel void @load_private_offset_v4i32() #0 {
%load = load volatile <4 x i32>, <4 x i32>* inttoptr (i32 8 to <4 x i32>*) %load = load volatile <4 x i32>, <4 x i32> addrspace(5)* inttoptr (i32 8 to <4 x i32> addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset: ; GCN-LABEL: {{^}}store_private_offset_i8_max_offset:
; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:4095 ; GCN: buffer_store_byte v{{[0-9]+}}, off, s[4:7], s2 offset:4095
define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 { define amdgpu_kernel void @store_private_offset_i8_max_offset() #0 {
store volatile i8 5, i8* inttoptr (i32 4095 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4095 to i8 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus1: ; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus1:
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000 ; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen{{$}} ; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen{{$}}
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 { define amdgpu_kernel void @store_private_offset_i8_max_offset_plus1() #0 {
store volatile i8 5, i8* inttoptr (i32 4096 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4096 to i8 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus2: ; GCN-LABEL: {{^}}store_private_offset_i8_max_offset_plus2:
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000 ; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x1000
; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen offset:1{{$}} ; GCN: buffer_store_byte v{{[0-9]+}}, [[OFFSET]], s[4:7], s2 offen offset:1{{$}}
define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 { define amdgpu_kernel void @store_private_offset_i8_max_offset_plus2() #0 {
store volatile i8 5, i8* inttoptr (i32 4097 to i8*) store volatile i8 5, i8 addrspace(5)* inttoptr (i32 4097 to i8 addrspace(5)*)
ret void ret void
} }
; MUBUF used for stack access has bounds checking enabled before gfx9, ; MUBUF used for stack access has bounds checking enabled before gfx9,
; so a possibly negative base index can't be used for the vgpr offset. ; so a possibly negative base index can't be used for the vgpr offset.
; GCN-LABEL: {{^}}store_private_unknown_bits_vaddr: ; GCN-LABEL: {{^}}store_private_unknown_bits_vaddr:
; SICIVI: v_add_{{i|u}}32_e32 [[ADDR0:v[0-9]+]], vcc, 4 ; SICIVI: v_add_{{i|u}}32_e32 [[ADDR0:v[0-9]+]], vcc, 4
; SICIVI: v_add_{{i|u}}32_e32 [[ADDR1:v[0-9]+]], vcc, 32, [[ADDR0]] ; SICIVI: v_add_{{i|u}}32_e32 [[ADDR1:v[0-9]+]], vcc, 32, [[ADDR0]]
; SICIVI: buffer_store_dword v{{[0-9]+}}, [[ADDR1]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}} ; SICIVI: buffer_store_dword v{{[0-9]+}}, [[ADDR1]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen{{$}}
; GFX9: v_add_u32_e32 [[ADDR:v[0-9]+]], 4, ; GFX9: v_add_u32_e32 [[ADDR:v[0-9]+]], 4,
; GFX9: buffer_store_dword v{{[0-9]+}}, [[ADDR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:32 ; GFX9: buffer_store_dword v{{[0-9]+}}, [[ADDR]], s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offen offset:32
define amdgpu_kernel void @store_private_unknown_bits_vaddr() #0 { define amdgpu_kernel void @store_private_unknown_bits_vaddr() #0 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
%vaddr = load volatile i32, i32 addrspace(1)* undef %vaddr = load volatile i32, i32 addrspace(1)* undef
%vaddr.off = add i32 %vaddr, 8 %vaddr.off = add i32 %vaddr, 8
%gep = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 %vaddr.off %gep = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 %vaddr.off
store volatile i32 9, i32* %gep store volatile i32 9, i32 addrspace(5)* %gep
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/nested-calls.ll

Show All 33 Lines
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: s_mov_b32 s5, s32 ; GCN: s_mov_b32 s5, s32
; GCN: s_add_u32 s32, s32, 0x1200{{$}} ; GCN: s_add_u32 s32, s32, 0x1200{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[0:3], s5 offset
; GCN: s_swappc_b64 ; GCN: s_swappc_b64
; GCN: s_sub_u32 s32, s32, 0x1200{{$}} ; GCN: s_sub_u32 s32, s32, 0x1200{{$}}
; GCN: s_setpc_b64 ; GCN: s_setpc_b64
define void @test_func_call_external_void_func_i32_imm_stack_use() #0 { define void @test_func_call_external_void_func_i32_imm_stack_use() #0 {
%alloca = alloca [16 x i32], align 4 %alloca = alloca [16 x i32], align 4, addrspace(5)
%gep0 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 0
%gep15 = getelementptr inbounds [16 x i32], [16 x i32]* %alloca, i32 0, i32 16 %gep15 = getelementptr inbounds [16 x i32], [16 x i32] addrspace(5)* %alloca, i32 0, i32 16
store volatile i32 0, i32* %gep0 store volatile i32 0, i32 addrspace(5)* %gep0
store volatile i32 0, i32* %gep15 store volatile i32 0, i32 addrspace(5)* %gep15
call void @external_void_func_i32(i32 42) call void @external_void_func_i32(i32 42)
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind noinline } attributes #2 = { nounwind noinline }

test/CodeGen/AMDGPU/parallelandifcollapse.ll

; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -march=r600 -mcpu=redwood -mattr=-promote-alloca -amdgpu-sroa=0 -verify-machineinstrs < %s | FileCheck %s
; ;
; CFG flattening should use parallel-and mode to generate branch conditions and ; CFG flattening should use parallel-and mode to generate branch conditions and
; then merge if-regions with the same bodies. ; then merge if-regions with the same bodies.
; ;
; CHECK: AND_INT ; CHECK: AND_INT
; CHECK-NEXT: AND_INT ; CHECK-NEXT: AND_INT
; CHECK-NEXT: OR_INT ; CHECK-NEXT: OR_INT
; FIXME: For some reason having the allocas here allowed the flatten cfg pass ; FIXME: For some reason having the allocas here allowed the flatten cfg pass
; to do its transformation, however now that we are using local memory for ; to do its transformation, however now that we are using local memory for
; allocas, the transformation isn't happening. ; allocas, the transformation isn't happening.
define amdgpu_kernel void @_Z9chk1D_512v() #0 { define amdgpu_kernel void @_Z9chk1D_512v() #0 {
entry: entry:
%a0 = alloca i32, align 4 %a0 = alloca i32, align 4, addrspace(5)
%b0 = alloca i32, align 4 %b0 = alloca i32, align 4, addrspace(5)
%c0 = alloca i32, align 4 %c0 = alloca i32, align 4, addrspace(5)
%d0 = alloca i32, align 4 %d0 = alloca i32, align 4, addrspace(5)
%a1 = alloca i32, align 4 %a1 = alloca i32, align 4, addrspace(5)
%b1 = alloca i32, align 4 %b1 = alloca i32, align 4, addrspace(5)
%c1 = alloca i32, align 4 %c1 = alloca i32, align 4, addrspace(5)
%d1 = alloca i32, align 4 %d1 = alloca i32, align 4, addrspace(5)
%data = alloca i32, align 4 %data = alloca i32, align 4, addrspace(5)
%0 = load i32, i32* %a0, align 4 %0 = load i32, i32 addrspace(5)* %a0, align 4
%1 = load i32, i32* %b0, align 4 %1 = load i32, i32 addrspace(5)* %b0, align 4
%cmp = icmp ne i32 %0, %1 %cmp = icmp ne i32 %0, %1
br i1 %cmp, label %land.lhs.true, label %if.end br i1 %cmp, label %land.lhs.true, label %if.end
land.lhs.true: ; preds = %entry land.lhs.true: ; preds = %entry
%2 = load i32, i32* %c0, align 4 %2 = load i32, i32 addrspace(5)* %c0, align 4
%3 = load i32, i32* %d0, align 4 %3 = load i32, i32 addrspace(5)* %d0, align 4
%cmp1 = icmp ne i32 %2, %3 %cmp1 = icmp ne i32 %2, %3
br i1 %cmp1, label %if.then, label %if.end br i1 %cmp1, label %if.then, label %if.end
if.then: ; preds = %land.lhs.true if.then: ; preds = %land.lhs.true
store i32 1, i32* %data, align 4 store i32 1, i32 addrspace(5)* %data, align 4
br label %if.end br label %if.end
if.end: ; preds = %if.then, %land.lhs.true, %entry if.end: ; preds = %if.then, %land.lhs.true, %entry
%4 = load i32, i32* %a1, align 4 %4 = load i32, i32 addrspace(5)* %a1, align 4
%5 = load i32, i32* %b1, align 4 %5 = load i32, i32 addrspace(5)* %b1, align 4
%cmp2 = icmp ne i32 %4, %5 %cmp2 = icmp ne i32 %4, %5
br i1 %cmp2, label %land.lhs.true3, label %if.end6 br i1 %cmp2, label %land.lhs.true3, label %if.end6
land.lhs.true3: ; preds = %if.end land.lhs.true3: ; preds = %if.end
%6 = load i32, i32* %c1, align 4 %6 = load i32, i32 addrspace(5)* %c1, align 4
%7 = load i32, i32* %d1, align 4 %7 = load i32, i32 addrspace(5)* %d1, align 4
%cmp4 = icmp ne i32 %6, %7 %cmp4 = icmp ne i32 %6, %7
br i1 %cmp4, label %if.then5, label %if.end6 br i1 %cmp4, label %if.then5, label %if.end6
if.then5: ; preds = %land.lhs.true3 if.then5: ; preds = %land.lhs.true3
store i32 1, i32* %data, align 4 store i32 1, i32 addrspace(5)* %data, align 4
br label %if.end6 br label %if.end6
if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end if.end6: ; preds = %if.then5, %land.lhs.true3, %if.end
ret void ret void
} }

test/CodeGen/AMDGPU/private-access-no-objects.ll

Show All 13 Lines
; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}} ; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
; -O0 should assume spilling, so the input scratch resource descriptor ; -O0 should assume spilling, so the input scratch resource descriptor
; -should be used directly without any copies. ; -should be used directly without any copies.
; OPTNONE-NOT: s_mov_b32 ; OPTNONE-NOT: s_mov_b32
; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s5 offen{{$}} ; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], s5 offen{{$}}
define amdgpu_kernel void @store_to_undef() #0 { define amdgpu_kernel void @store_to_undef() #0 {
store volatile i32 0, i32* undef store volatile i32 0, i32 addrspace(5)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}store_to_inttoptr: ; GCN-LABEL: {{^}}store_to_inttoptr:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}} ; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}} ; OPT: buffer_store_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
define amdgpu_kernel void @store_to_inttoptr() #0 { define amdgpu_kernel void @store_to_inttoptr() #0 {
store volatile i32 0, i32* inttoptr (i32 124 to i32*) store volatile i32 0, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
; GCN-LABEL: {{^}}load_from_undef: ; GCN-LABEL: {{^}}load_from_undef:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}} ; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offen{{$}}
define amdgpu_kernel void @load_from_undef() #0 { define amdgpu_kernel void @load_from_undef() #0 {
%ld = load volatile i32, i32* undef %ld = load volatile i32, i32 addrspace(5)* undef
ret void ret void
} }
; GCN-LABEL: {{^}}load_from_inttoptr: ; GCN-LABEL: {{^}}load_from_inttoptr:
; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1] ; OPT-DAG: s_mov_b64 s{{\[}}[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]
; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3] ; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]{{\]}}, s[2:3]
; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}} ; OPT-DAG: s_mov_b32 [[SOFFSET:s[0-9]+]], s5{{$}}
; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}} ; OPT: buffer_load_dword v{{[0-9]+}}, off, s{{\[}}[[RSRC_LO]]:[[RSRC_HI]]{{\]}}, [[SOFFSET]] offset:124{{$}}
define amdgpu_kernel void @load_from_inttoptr() #0 { define amdgpu_kernel void @load_from_inttoptr() #0 {
%ld = load volatile i32, i32* inttoptr (i32 124 to i32*) %ld = load volatile i32, i32 addrspace(5)* inttoptr (i32 124 to i32 addrspace(5)*)
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/private-element-size.ll

Show All 37 Lines
; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}}
define amdgpu_kernel void @private_elt_size_v4i32(<4 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_v4i32(<4 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%idxprom = sext i32 %tid to i64 %idxprom = sext i32 %tid to i64
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x <4 x i32>], align 16 %alloca = alloca [2 x <4 x i32>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>] addrspace(5)* %alloca, i32 0, i32 1
store <4 x i32> zeroinitializer, <4 x i32>* %gep0 store <4 x i32> zeroinitializer, <4 x i32> addrspace(5)* %gep0
store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32>* %gep1 store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x <4 x i32>], [2 x <4 x i32>] addrspace(5)* %alloca, i32 0, i32 %index
%load = load <4 x i32>, <4 x i32>* %gep2 %load = load <4 x i32>, <4 x i32> addrspace(5)* %gep2
store <4 x i32> %load, <4 x i32> addrspace(1)* %out store <4 x i32> %load, <4 x i32> addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}private_elt_size_v8i32: ; ALL-LABEL: {{^}}private_elt_size_v8i32:
; HSA-ELT16: private_element_size = 3 ; HSA-ELT16: private_element_size = 3
; HSA-ELT8: private_element_size = 2 ; HSA-ELT8: private_element_size = 2
; HSA-ELT4: private_element_size = 1 ; HSA-ELT4: private_element_size = 1
▲ Show 20 Lines • Show All 47 Lines • ▼ Show 20 Lines
; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:28{{$}} ; HSA-ELT4-DAG: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:28{{$}}
define amdgpu_kernel void @private_elt_size_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_v8i32(<8 x i32> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%idxprom = sext i32 %tid to i64 %idxprom = sext i32 %tid to i64
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x <8 x i32>], align 16 %alloca = alloca [2 x <8 x i32>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>] addrspace(5)* %alloca, i32 0, i32 1
store <8 x i32> zeroinitializer, <8 x i32>* %gep0 store <8 x i32> zeroinitializer, <8 x i32> addrspace(5)* %gep0
store <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>, <8 x i32>* %gep1 store <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8>, <8 x i32> addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x <8 x i32>], [2 x <8 x i32>] addrspace(5)* %alloca, i32 0, i32 %index
%load = load <8 x i32>, <8 x i32>* %gep2 %load = load <8 x i32>, <8 x i32> addrspace(5)* %gep2
store <8 x i32> %load, <8 x i32> addrspace(1)* %out store <8 x i32> %load, <8 x i32> addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}private_elt_size_i64: ; ALL-LABEL: {{^}}private_elt_size_i64:
; HSA-ELT16: private_element_size = 3 ; HSA-ELT16: private_element_size = 3
; HSA-ELT8: private_element_size = 2 ; HSA-ELT8: private_element_size = 2
Show All 14 Lines
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}}
define amdgpu_kernel void @private_elt_size_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_i64(i64 addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%idxprom = sext i32 %tid to i64 %idxprom = sext i32 %tid to i64
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x i64], align 16 %alloca = alloca [2 x i64], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x i64], [2 x i64] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x i64], [2 x i64] addrspace(5)* %alloca, i32 0, i32 1
store i64 0, i64* %gep0 store i64 0, i64 addrspace(5)* %gep0
store i64 34359738602, i64* %gep1 store i64 34359738602, i64 addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x i64], [2 x i64]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x i64], [2 x i64] addrspace(5)* %alloca, i32 0, i32 %index
%load = load i64, i64* %gep2 %load = load i64, i64 addrspace(5)* %gep2
store i64 %load, i64 addrspace(1)* %out store i64 %load, i64 addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}private_elt_size_f64: ; ALL-LABEL: {{^}}private_elt_size_f64:
; HSA-ELT16: private_element_size = 3 ; HSA-ELT16: private_element_size = 3
; HSA-ELT8: private_element_size = 2 ; HSA-ELT8: private_element_size = 2
; HSA-ELT4: private_element_size = 1 ; HSA-ELT4: private_element_size = 1
Show All 13 Lines
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}} ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:4{{$}}
define amdgpu_kernel void @private_elt_size_f64(double addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_f64(double addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%idxprom = sext i32 %tid to i64 %idxprom = sext i32 %tid to i64
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x double], align 16 %alloca = alloca [2 x double], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x double], [2 x double] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x double], [2 x double] addrspace(5)* %alloca, i32 0, i32 1
store double 0.0, double* %gep0 store double 0.0, double addrspace(5)* %gep0
store double 4.0, double* %gep1 store double 4.0, double addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x double], [2 x double]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x double], [2 x double] addrspace(5)* %alloca, i32 0, i32 %index
%load = load double, double* %gep2 %load = load double, double addrspace(5)* %gep2
store double %load, double addrspace(1)* %out store double %load, double addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}private_elt_size_v2i64: ; ALL-LABEL: {{^}}private_elt_size_v2i64:
; HSA-ELT16: private_element_size = 3 ; HSA-ELT16: private_element_size = 3
; HSA-ELT8: private_element_size = 2 ; HSA-ELT8: private_element_size = 2
; HSA-ELT4: private_element_size = 1 ; HSA-ELT4: private_element_size = 1
Show All 26 Lines
; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}} ; HSA-ELT4: buffer_load_dword {{v[0-9]+}}, v{{[0-9]+}}, s[0:3], s9 offen offset:12{{$}}
define amdgpu_kernel void @private_elt_size_v2i64(<2 x i64> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 { define amdgpu_kernel void @private_elt_size_v2i64(<2 x i64> addrspace(1)* %out, i32 addrspace(1)* %index.array) #0 {
entry: entry:
%tid = call i32 @llvm.amdgcn.workitem.id.x() %tid = call i32 @llvm.amdgcn.workitem.id.x()
%idxprom = sext i32 %tid to i64 %idxprom = sext i32 %tid to i64
%gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom %gep.index = getelementptr inbounds i32, i32 addrspace(1)* %index.array, i64 %idxprom
%index.load = load i32, i32 addrspace(1)* %gep.index %index.load = load i32, i32 addrspace(1)* %gep.index
%index = and i32 %index.load, 2 %index = and i32 %index.load, 2
%alloca = alloca [2 x <2 x i64>], align 16 %alloca = alloca [2 x <2 x i64>], align 16, addrspace(5)
%gep0 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>] addrspace(5)* %alloca, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>] addrspace(5)* %alloca, i32 0, i32 1
store <2 x i64> zeroinitializer, <2 x i64>* %gep0 store <2 x i64> zeroinitializer, <2 x i64> addrspace(5)* %gep0
store <2 x i64> <i64 1, i64 2>, <2 x i64>* %gep1 store <2 x i64> <i64 1, i64 2>, <2 x i64> addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>]* %alloca, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x <2 x i64>], [2 x <2 x i64>] addrspace(5)* %alloca, i32 0, i32 %index
%load = load <2 x i64>, <2 x i64>* %gep2 %load = load <2 x i64>, <2 x i64> addrspace(5)* %gep2
store <2 x i64> %load, <2 x i64> addrspace(1)* %out store <2 x i64> %load, <2 x i64> addrspace(1)* %out
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/private-memory-atomics.ll

; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tahiti < %s
; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga < %s
; This works because promote allocas pass replaces these with LDS atomics. ; This works because promote allocas pass replaces these with LDS atomics.
; Private atomics have no real use, but at least shouldn't crash on it. ; Private atomics have no real use, but at least shouldn't crash on it.
define amdgpu_kernel void @atomicrmw_private(i32 addrspace(1)* %out, i32 %in) nounwind { define amdgpu_kernel void @atomicrmw_private(i32 addrspace(1)* %out, i32 %in) nounwind {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%tmp4 = atomicrmw add i32* %tmp3, i32 7 acq_rel %tmp4 = atomicrmw add i32 addrspace(5)* %tmp3, i32 7 acq_rel
store i32 %tmp4, i32 addrspace(1)* %out store i32 %tmp4, i32 addrspace(1)* %out
ret void ret void
} }
define amdgpu_kernel void @cmpxchg_private(i32 addrspace(1)* %out, i32 %in) nounwind { define amdgpu_kernel void @cmpxchg_private(i32 addrspace(1)* %out, i32 %in) nounwind {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr inbounds [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr inbounds [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%tmp4 = cmpxchg i32* %tmp3, i32 0, i32 1 acq_rel monotonic %tmp4 = cmpxchg i32 addrspace(5)* %tmp3, i32 0, i32 1 acq_rel monotonic
%val = extractvalue { i32, i1 } %tmp4, 0 %val = extractvalue { i32, i1 } %tmp4, 0
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/promote-alloca-bitcast-function.ll

; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck %s ; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck %s
; FIXME: Error is misleading because it's not an indirect call. ; FIXME: Error is misleading because it's not an indirect call.
; CHECK: error: <unknown>:0:0: in function crash_call_constexpr_cast void (): unsupported indirect call to function foo ; CHECK: error: <unknown>:0:0: in function crash_call_constexpr_cast void (): unsupported indirect call to function foo
; Make sure that AMDGPUPromoteAlloca doesn't crash if the called ; Make sure that AMDGPUPromoteAlloca doesn't crash if the called
; function is a constantexpr cast of a function. ; function is a constantexpr cast of a function.
declare void @foo(float*) #0 declare void @foo(float addrspace(5)*) #0
declare void @foo.varargs(...) #0 declare void @foo.varargs(...) #0
; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo ; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo
define amdgpu_kernel void @crash_call_constexpr_cast() #0 { define amdgpu_kernel void @crash_call_constexpr_cast() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
call void bitcast (void (float*)* @foo to void (i32*)*)(i32* %alloca) #0 call void bitcast (void (float addrspace(5)*)* @foo to void (i32 addrspace(5)*)*)(i32 addrspace(5)* %alloca) #0
ret void ret void
} }
; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo.varargs ; XCHECK: in function crash_call_constexpr_cast{{.*}}: unsupported call to function foo.varargs
define amdgpu_kernel void @crash_call_constexpr_cast_varargs() #0 { define amdgpu_kernel void @crash_call_constexpr_cast_varargs() #0 {
%alloca = alloca i32 %alloca = alloca i32, addrspace(5)
call void bitcast (void (...)* @foo.varargs to void (i32*)*)(i32* %alloca) #0 call void bitcast (void (...)* @foo.varargs to void (i32 addrspace(5)*)*)(i32 addrspace(5)* %alloca) #0
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/promote-alloca-calling-conv.ll

; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s ; RUN: opt -data-layout=A5 -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s
; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=ASM %s ; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefix=ASM %s
; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 { ; IR-LABEL: define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
; IR: alloca [5 x i32] ; IR: alloca [5 x i32]
; ASM-LABEL: {{^}}promote_alloca_shaders: ; ASM-LABEL: {{^}}promote_alloca_shaders:
; ASM: ; ScratchSize: 24 ; ASM: ; ScratchSize: 24
define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 { define amdgpu_vs void @promote_alloca_shaders(i32 addrspace(1)* inreg %out, i32 addrspace(1)* inreg %in) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx4 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx4 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx4, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx4, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx5 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx5 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx5 %tmp3 = load i32, i32 addrspace(5)* %arrayidx5
%arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx6 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx6 store i32 %tmp3, i32 addrspace(1)* %arrayidx6
ret void ret void
} }
; OPT-LABEL: @promote_to_vector_call_c( ; OPT-LABEL: @promote_to_vector_call_c(
; OPT-NOT: alloca ; OPT-NOT: alloca
; OPT: extractelement <2 x i32> %{{[0-9]+}}, i32 %in ; OPT: extractelement <2 x i32> %{{[0-9]+}}, i32 %in
; ASM-LABEL: {{^}}promote_to_vector_call_c: ; ASM-LABEL: {{^}}promote_to_vector_call_c:
; ASM-NOT: LDSByteSize ; ASM-NOT: LDSByteSize
; ASM: ; ScratchSize: 0 ; ASM: ; ScratchSize: 0
define void @promote_to_vector_call_c(i32 addrspace(1)* %out, i32 %in) #0 { define void @promote_to_vector_call_c(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%tmp4 = load i32, i32* %tmp3 %tmp4 = load i32, i32 addrspace(5)* %tmp3
%tmp5 = load volatile i32, i32 addrspace(1)* undef %tmp5 = load volatile i32, i32 addrspace(1)* undef
%tmp6 = add i32 %tmp4, %tmp5 %tmp6 = add i32 %tmp4, %tmp5
store i32 %tmp6, i32 addrspace(1)* %out store i32 %tmp6, i32 addrspace(1)* %out
ret void ret void
} }
; OPT-LABEL: @no_promote_to_lds_c( ; OPT-LABEL: @no_promote_to_lds_c(
; OPT: alloca ; OPT: alloca
; ASM-LABEL: {{^}}no_promote_to_lds_c: ; ASM-LABEL: {{^}}no_promote_to_lds_c:
; ASM-NOT: LDSByteSize ; ASM-NOT: LDSByteSize
; ASM: ; ScratchSize: 24 ; ASM: ; ScratchSize: 24
define void @no_promote_to_lds_c(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 { define void @no_promote_to_lds_c(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%0 = load i32, i32 addrspace(1)* %in, align 4 %0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%2 = load i32, i32* %arrayidx10, align 4 %2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %2, i32 addrspace(1)* %out, align 4 store i32 %2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%3 = load i32, i32* %arrayidx12 %3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %3, i32 addrspace(1)* %arrayidx13 store i32 %3, i32 addrspace(1)* %arrayidx13
ret void ret void
} }
declare i32 @foo(i32*) #0 declare i32 @foo(i32 addrspace(5)*) #0
; ASM-LABEL: {{^}}call_private: ; ASM-LABEL: {{^}}call_private:
; ASM: buffer_store_dword ; ASM: buffer_store_dword
; ASM: buffer_store_dword ; ASM: buffer_store_dword
; ASM: s_swappc_b64 ; ASM: s_swappc_b64
; ASM: ScratchSize: 16396 ; ASM: ScratchSize: 16396
define amdgpu_kernel void @call_private(i32 addrspace(1)* %out, i32 %in) #0 { define amdgpu_kernel void @call_private(i32 addrspace(1)* %out, i32 %in) #0 {
entry: entry:
%tmp = alloca [2 x i32] %tmp = alloca [2 x i32], addrspace(5)
%tmp1 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 0 %tmp1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 0
%tmp2 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 1 %tmp2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 1
store i32 0, i32* %tmp1 store i32 0, i32 addrspace(5)* %tmp1
store i32 1, i32* %tmp2 store i32 1, i32 addrspace(5)* %tmp2
%tmp3 = getelementptr [2 x i32], [2 x i32]* %tmp, i32 0, i32 %in %tmp3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %tmp, i32 0, i32 %in
%val = call i32 @foo(i32* %tmp3) %val = call i32 @foo(i32 addrspace(5)* %tmp3)
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" } attributes #0 = { nounwind "amdgpu-max-work-group-size"="64" }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }

test/CodeGen/AMDGPU/promote-alloca-globals.ll

; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s ; RUN: opt -data-layout=A5 -S -mtriple=amdgcn-unknown-unknown -amdgpu-promote-alloca < %s | FileCheck -check-prefix=IR %s
; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s ; RUN: llc -march=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=ASM %s
@global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4 @global_array0 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4
@global_array1 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4 @global_array1 = internal unnamed_addr addrspace(3) global [750 x [10 x i32]] undef, align 4
; IR-LABEL: define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { ; IR-LABEL: define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
; IR: alloca [10 x i32] ; IR: alloca [10 x i32]
; ASM-LABEL: {{^}}promote_alloca_size_256: ; ASM-LABEL: {{^}}promote_alloca_size_256:
; ASM: ; LDSByteSize: 60000 bytes/workgroup (compile time only) ; ASM: ; LDSByteSize: 60000 bytes/workgroup (compile time only)
define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) { define amdgpu_kernel void @promote_alloca_size_256(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) {
entry: entry:
%stack = alloca [10 x i32], align 4 %stack = alloca [10 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [10 x i32], [10 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [10 x i32], [10 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
%v0 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array0, i32 0, i32 0, i32 0 %v0 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array0, i32 0, i32 0, i32 0
store i32 %tmp3, i32 addrspace(3)* %v0 store i32 %tmp3, i32 addrspace(3)* %v0
%v1 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array1, i32 0, i32 0, i32 0 %v1 = getelementptr inbounds [750 x [10 x i32]], [750 x [10 x i32]] addrspace(3)* @global_array1, i32 0, i32 0, i32 0
store i32 %tmp3, i32 addrspace(3)* %v1 store i32 %tmp3, i32 addrspace(3)* %v1
ret void ret void
} }

test/CodeGen/AMDGPU/promote-alloca-no-opts.ll

; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s ; RUN: llc -O0 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=NOOPTS -check-prefix=ALL %s
; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s ; RUN: llc -O1 -march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mcpu=kaveri -mattr=+promote-alloca < %s | FileCheck -check-prefix=OPTS -check-prefix=ALL %s
; ALL-LABEL: {{^}}promote_alloca_i32_array_array: ; ALL-LABEL: {{^}}promote_alloca_i32_array_array:
; NOOPTS: workgroup_group_segment_byte_size = 0{{$}} ; NOOPTS: workgroup_group_segment_byte_size = 0{{$}}
; NOOPTS-NOT ds_write ; NOOPTS-NOT ds_write
; OPTS: ds_write ; OPTS: ds_write
define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 { define amdgpu_kernel void @promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #0 {
entry: entry:
%alloca = alloca [2 x [2 x i32]] %alloca = alloca [2 x [2 x i32]], addrspace(5)
%gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
store i32 0, i32* %gep0 store i32 0, i32 addrspace(5)* %gep0
store i32 1, i32* %gep1 store i32 1, i32 addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
%load = load i32, i32* %gep2 %load = load i32, i32 addrspace(5)* %gep2
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: {{^}}optnone_promote_alloca_i32_array_array: ; ALL-LABEL: {{^}}optnone_promote_alloca_i32_array_array:
; ALL: workgroup_group_segment_byte_size = 0{{$}} ; ALL: workgroup_group_segment_byte_size = 0{{$}}
; ALL-NOT ds_write ; ALL-NOT ds_write
define amdgpu_kernel void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 { define amdgpu_kernel void @optnone_promote_alloca_i32_array_array(i32 addrspace(1)* %out, i32 %index) #1 {
entry: entry:
%alloca = alloca [2 x [2 x i32]] %alloca = alloca [2 x [2 x i32]], addrspace(5)
%gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 0 %gep0 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 0
%gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 1 %gep1 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 1
store i32 0, i32* %gep0 store i32 0, i32 addrspace(5)* %gep0
store i32 1, i32* %gep1 store i32 1, i32 addrspace(5)* %gep1
%gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]]* %alloca, i32 0, i32 0, i32 %index %gep2 = getelementptr inbounds [2 x [2 x i32]], [2 x [2 x i32]] addrspace(5)* %alloca, i32 0, i32 0, i32 %index
%load = load i32, i32* %gep2 %load = load i32, i32 addrspace(5)* %gep2
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" } attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" }
attributes #1 = { nounwind optnone noinline "amdgpu-flat-work-group-size"="64,64" } attributes #1 = { nounwind optnone noinline "amdgpu-flat-work-group-size"="64,64" }

test/CodeGen/AMDGPU/promote-alloca-padding-size-estimate.ll

Show All 26 Lines
@lds2 = internal unnamed_addr addrspace(3) global [32 x i64] undef, align 8 @lds2 = internal unnamed_addr addrspace(3) global [32 x i64] undef, align 8
@lds1 = internal unnamed_addr addrspace(3) global [73 x i32] undef, align 4 @lds1 = internal unnamed_addr addrspace(3) global [73 x i32] undef, align 4
; GCN-LABEL: {{^}}promote_alloca_size_order_0: ; GCN-LABEL: {{^}}promote_alloca_size_order_0:
; GCN: workgroup_group_segment_byte_size = 2340 ; GCN: workgroup_group_segment_byte_size = 2340
define amdgpu_kernel void @promote_alloca_size_order_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { define amdgpu_kernel void @promote_alloca_size_order_0(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
%gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx %gep.lds1 = getelementptr inbounds [73 x i32], [73 x i32] addrspace(3)* @lds1, i32 0, i32 %idx
store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4 store volatile i32 0, i32 addrspace(3)* %gep.lds1, align 4
%gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx %gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx
store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8 store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8
%gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx
store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16 store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16
ret void ret void
} }
; GCN-LABEL: {{^}}promote_alloca_size_order_1: ; GCN-LABEL: {{^}}promote_alloca_size_order_1:
; GCN: workgroup_group_segment_byte_size = 2352 ; GCN: workgroup_group_segment_byte_size = 2352
define amdgpu_kernel void @promote_alloca_size_order_1(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { define amdgpu_kernel void @promote_alloca_size_order_1(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
%gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], [32 x <4 x i32>] addrspace(3)* @lds0, i32 0, i32 %idx
store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16 store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds0, align 16
%gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx %gep.lds2 = getelementptr inbounds [32 x i64], [32 x i64] addrspace(3)* @lds2, i32 0, i32 %idx
store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8 store volatile i64 0, i64 addrspace(3)* %gep.lds2, align 8
Show All 9 Lines
; The guess from the alignment padding pushes this over the determined ; The guess from the alignment padding pushes this over the determined
; size limit, so it isn't promoted ; size limit, so it isn't promoted
; GCN-LABEL: {{^}}promote_alloca_align_pad_guess_over_limit: ; GCN-LABEL: {{^}}promote_alloca_align_pad_guess_over_limit:
; GCN: workgroup_group_segment_byte_size = 1060 ; GCN: workgroup_group_segment_byte_size = 1060
define amdgpu_kernel void @promote_alloca_align_pad_guess_over_limit(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 { define amdgpu_kernel void @promote_alloca_align_pad_guess_over_limit(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in, i32 %idx) #0 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp0 = load i32, i32 addrspace(1)* %in, align 4 %tmp0 = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp0 %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp0
store i32 4, i32* %arrayidx1, align 4 store i32 4, i32 addrspace(5)* %arrayidx1, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %in, i32 1
%tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4 %tmp1 = load i32, i32 addrspace(1)* %arrayidx2, align 4
%arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp1 %arrayidx3 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp1
store i32 5, i32* %arrayidx3, align 4 store i32 5, i32 addrspace(5)* %arrayidx3, align 4
%arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 0 %arrayidx10 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 0
%tmp2 = load i32, i32* %arrayidx10, align 4 %tmp2 = load i32, i32 addrspace(5)* %arrayidx10, align 4
store i32 %tmp2, i32 addrspace(1)* %out, align 4 store i32 %tmp2, i32 addrspace(1)* %out, align 4
%arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 1 %arrayidx12 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 1
%tmp3 = load i32, i32* %arrayidx12 %tmp3 = load i32, i32 addrspace(5)* %arrayidx12
%arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1 %arrayidx13 = getelementptr inbounds i32, i32 addrspace(1)* %out, i32 1
store i32 %tmp3, i32 addrspace(1)* %arrayidx13 store i32 %tmp3, i32 addrspace(1)* %arrayidx13
%gep.lds3 = getelementptr inbounds [13 x i32], [13 x i32] addrspace(3)* @lds3, i32 0, i32 %idx %gep.lds3 = getelementptr inbounds [13 x i32], [13 x i32] addrspace(3)* @lds3, i32 0, i32 %idx
store volatile i32 0, i32 addrspace(3)* %gep.lds3, align 4 store volatile i32 0, i32 addrspace(3)* %gep.lds3, align 4
%gep.lds4 = getelementptr inbounds [63 x <4 x i32>], [63 x <4 x i32>] addrspace(3)* @lds4, i32 0, i32 %idx %gep.lds4 = getelementptr inbounds [63 x <4 x i32>], [63 x <4 x i32>] addrspace(3)* @lds4, i32 0, i32 %idx
store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds4, align 16 store volatile <4 x i32> zeroinitializer, <4 x i32> addrspace(3)* %gep.lds4, align 16
ret void ret void
} }
attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,7" } attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,7" }

test/CodeGen/AMDGPU/promote-alloca-stored-pointer-value.ll

; RUN: llc -march=amdgcn -mattr=+promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mattr=+promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s ; RUN: llc -march=amdgcn -mattr=-promote-alloca,+max-private-element-size-4 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
; Pointer value is stored in a candidate for LDS usage. ; Pointer value is stored in a candidate for LDS usage.
; GCN-LABEL: {{^}}stored_lds_pointer_value: ; GCN-LABEL: {{^}}stored_lds_pointer_value:
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
define amdgpu_kernel void @stored_lds_pointer_value(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_lds_pointer_value(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp = alloca float %tmp = alloca float, addrspace(5)
store float 0.0, float *%tmp store float 0.0, float addrspace(5)*%tmp
store float* %tmp, float* addrspace(1)* %ptr store float addrspace(5)* %tmp, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}stored_lds_pointer_value_offset: ; GCN-LABEL: {{^}}stored_lds_pointer_value_offset:
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
define amdgpu_kernel void @stored_lds_pointer_value_offset(float* addrspace(1)* %ptr) #0 { define amdgpu_kernel void @stored_lds_pointer_value_offset(float addrspace(5)* addrspace(1)* %ptr) #0 {
%tmp0 = alloca float %tmp0 = alloca float, addrspace(5)
%tmp1 = alloca float %tmp1 = alloca float, addrspace(5)
store float 0.0, float *%tmp0 store float 0.0, float addrspace(5)*%tmp0
store float 0.0, float *%tmp1 store float 0.0, float addrspace(5)*%tmp1
store volatile float* %tmp0, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp0, float addrspace(5)* addrspace(1)* %ptr
store volatile float* %tmp1, float* addrspace(1)* %ptr store volatile float addrspace(5)* %tmp1, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}stored_lds_pointer_value_gep: ; GCN-LABEL: {{^}}stored_lds_pointer_value_gep:
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
; GCN: buffer_store_dword v ; GCN: buffer_store_dword v
define amdgpu_kernel void @stored_lds_pointer_value_gep(float* addrspace(1)* %ptr, i32 %idx) #0 { define amdgpu_kernel void @stored_lds_pointer_value_gep(float addrspace(5)* addrspace(1)* %ptr, i32 %idx) #0 {
bb: bb:
%tmp = alloca float, i32 16 %tmp = alloca float, i32 16, addrspace(5)
store float 0.0, float* %tmp store float 0.0, float addrspace(5)* %tmp
%tmp2 = getelementptr inbounds float, float* %tmp, i32 %idx %tmp2 = getelementptr inbounds float, float addrspace(5)* %tmp, i32 %idx
store float* %tmp2, float* addrspace(1)* %ptr store float addrspace(5)* %tmp2, float addrspace(5)* addrspace(1)* %ptr
ret void ret void
} }
; Pointer value is stored in a candidate for vector usage ; Pointer value is stored in a candidate for vector usage
; GCN-LABEL: {{^}}stored_vector_pointer_value: ; GCN-LABEL: {{^}}stored_vector_pointer_value:
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD0
; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1 ; GCN-DAG: s_mov_b32 s{{[0-9]+}}, SCRATCH_RSRC_DWORD1
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: buffer_store_dword ; GCN: buffer_store_dword
; GCN: buffer_store_dword ; GCN: buffer_store_dword
define amdgpu_kernel void @stored_vector_pointer_value(i32* addrspace(1)* %out, i32 %index) { define amdgpu_kernel void @stored_vector_pointer_value(i32 addrspace(5)* addrspace(1)* %out, i32 %index) {
entry: entry:
%tmp0 = alloca [4 x i32] %tmp0 = alloca [4 x i32], addrspace(5)
%x = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 0 %x = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 0
%y = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 1 %y = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 1
%z = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 2 %z = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 2
%w = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 3 %w = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 3
store i32 0, i32* %x store i32 0, i32 addrspace(5)* %x
store i32 1, i32* %y store i32 1, i32 addrspace(5)* %y
store i32 2, i32* %z store i32 2, i32 addrspace(5)* %z
store i32 3, i32* %w store i32 3, i32 addrspace(5)* %w
%tmp1 = getelementptr inbounds [4 x i32], [4 x i32]* %tmp0, i32 0, i32 %index %tmp1 = getelementptr inbounds [4 x i32], [4 x i32] addrspace(5)* %tmp0, i32 0, i32 %index
store i32* %tmp1, i32* addrspace(1)* %out store i32 addrspace(5)* %tmp1, i32 addrspace(5)* addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}stored_fi_to_self: ; GCN-LABEL: {{^}}stored_fi_to_self:
; GCN-NOT: ds_ ; GCN-NOT: ds_
define amdgpu_kernel void @stored_fi_to_self() #0 { define amdgpu_kernel void @stored_fi_to_self() #0 {
%tmp = alloca i32* %tmp = alloca i32 addrspace(5)*, addrspace(5)
store volatile i32* inttoptr (i32 1234 to i32*), i32** %tmp store volatile i32 addrspace(5)* inttoptr (i32 1234 to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %tmp
%bitcast = bitcast i32** %tmp to i32* %bitcast = bitcast i32 addrspace(5)* addrspace(5)* %tmp to i32 addrspace(5)*
store volatile i32* %bitcast, i32** %tmp store volatile i32 addrspace(5)* %bitcast, i32 addrspace(5)* addrspace(5)* %tmp
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/r600.alu-limits.ll

; RUN: opt -loop-unroll -unroll-threshold=2000 -S < %s | llc -march=r600 -mcpu=cypress | FileCheck %s ; RUN: opt -loop-unroll -unroll-threshold=2000 -S < %s | llc -march=r600 -mcpu=cypress | FileCheck %s
; REQUIRES: asserts ; REQUIRES: asserts
; CHECK: {{^}}alu_limits: ; CHECK: {{^}}alu_limits:
; CHECK: CF_END ; CHECK: CF_END
%struct.foo = type {i32, i32, i32} %struct.foo = type {i32, i32, i32}
define amdgpu_kernel void @alu_limits(i32 addrspace(1)* %out, %struct.foo* %in, i32 %offset) { define amdgpu_kernel void @alu_limits(i32 addrspace(1)* %out, %struct.foo addrspace(5)* %in, i32 %offset) {
entry: entry:
%ptr = getelementptr inbounds %struct.foo, %struct.foo* %in, i32 1, i32 2 %ptr = getelementptr inbounds %struct.foo, %struct.foo addrspace(5)* %in, i32 1, i32 2
%x = load i32, i32 *%ptr, align 4 %x = load i32, i32 addrspace(5)*%ptr, align 4
br label %loop br label %loop
loop: loop:
%i = phi i32 [ 100, %entry ], [ %nexti, %loop ] %i = phi i32 [ 100, %entry ], [ %nexti, %loop ]
%val = phi i32 [ 1, %entry ], [ %nextval, %loop ] %val = phi i32 [ 1, %entry ], [ %nextval, %loop ]
%nexti = sub i32 %i, 1 %nexti = sub i32 %i, 1
%y = xor i32 %x, %i %y = xor i32 %x, %i
Show All 9 Lines

test/CodeGen/AMDGPU/r600.private-memory.ll

; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck %s -check-prefix=R600 -check-prefix=FUNC
declare i32 @llvm.r600.read.tidig.x() nounwind readnone declare i32 @llvm.r600.read.tidig.x() nounwind readnone
; Make sure we don't overwrite workitem information with private memory ; Make sure we don't overwrite workitem information with private memory
; FUNC-LABEL: {{^}}work_item_info: ; FUNC-LABEL: {{^}}work_item_info:
; R600-NOT: MOV T0.X ; R600-NOT: MOV T0.X
; Additional check in case the move ends up in the last slot ; Additional check in case the move ends up in the last slot
; R600-NOT: MOV * TO.X ; R600-NOT: MOV * TO.X
define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) { define amdgpu_kernel void @work_item_info(i32 addrspace(1)* %out, i32 %in) {
entry: entry:
%0 = alloca [2 x i32] %0 = alloca [2 x i32], addrspace(5)
%1 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 0 %1 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 0
%2 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 1 %2 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 1
store i32 0, i32* %1 store i32 0, i32 addrspace(5)* %1
store i32 1, i32* %2 store i32 1, i32 addrspace(5)* %2
%3 = getelementptr [2 x i32], [2 x i32]* %0, i32 0, i32 %in %3 = getelementptr [2 x i32], [2 x i32] addrspace(5)* %0, i32 0, i32 %in
%4 = load i32, i32* %3 %4 = load i32, i32 addrspace(5)* %3
%5 = call i32 @llvm.r600.read.tidig.x() %5 = call i32 @llvm.r600.read.tidig.x()
%6 = add i32 %4, %5 %6 = add i32 %4, %5
store i32 %6, i32 addrspace(1)* %out store i32 %6, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/sad.ll

Show First 20 Lines • Show All 53 Lines • ▼ Show 20 Lines
define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b %t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b %icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b %t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1 %ret0 = sub i32 %t0, %t1
store volatile i32 %ret0, i32 *undef store volatile i32 %ret0, i32 addrspace(5)*undef
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_multi_use_add_pat1: ; GCN-LABEL: {{^}}v_sad_u32_multi_use_add_pat1:
; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_add_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b %t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b %icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b %t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1 %ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store volatile i32 %ret, i32 *undef store volatile i32 %ret, i32 addrspace(5)*undef
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_multi_use_max_pat1: ; GCN-LABEL: {{^}}v_sad_u32_multi_use_max_pat1:
; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_max_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b %t0 = select i1 %icmp0, i32 %a, i32 %b
store volatile i32 %t0, i32 *undef store volatile i32 %t0, i32 addrspace(5)*undef
%icmp1 = icmp ule i32 %a, %b %icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b %t1 = select i1 %icmp1, i32 %a, i32 %b
%ret0 = sub i32 %t0, %t1 %ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_multi_use_min_pat1: ; GCN-LABEL: {{^}}v_sad_u32_multi_use_min_pat1:
; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_min_pat1(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%t0 = select i1 %icmp0, i32 %a, i32 %b %t0 = select i1 %icmp0, i32 %a, i32 %b
%icmp1 = icmp ule i32 %a, %b %icmp1 = icmp ule i32 %a, %b
%t1 = select i1 %icmp1, i32 %a, i32 %b %t1 = select i1 %icmp1, i32 %a, i32 %b
store volatile i32 %t1, i32 *undef store volatile i32 %t1, i32 addrspace(5)*undef
%ret0 = sub i32 %t0, %t1 %ret0 = sub i32 %t0, %t1
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat2: ; GCN-LABEL: {{^}}v_sad_u32_multi_use_sub_pat2:
; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} ; GCN: v_sad_u32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_sub_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %b %sub0 = sub i32 %a, %b
store volatile i32 %sub0, i32 *undef store volatile i32 %sub0, i32 addrspace(5)*undef
%sub1 = sub i32 %b, %a %sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2: ; GCN-LABEL: {{^}}v_sad_u32_multi_use_select_pat2:
; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
; GCN-DAG: v_cmp_gt_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}} ; GCN-DAG: v_cmp_gt_u32_e32 vcc, s{{[0-9]+}}, v{{[0-9]+}}
; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}} ; GCN-DAG: s_sub_i32 s{{[0-9]+}}, s{{[0-9]+}}, s{{[0-9]+}}
define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { define amdgpu_kernel void @v_sad_u32_multi_use_select_pat2(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) {
%icmp0 = icmp ugt i32 %a, %b %icmp0 = icmp ugt i32 %a, %b
%sub0 = sub i32 %a, %b %sub0 = sub i32 %a, %b
%sub1 = sub i32 %b, %a %sub1 = sub i32 %b, %a
%ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1 %ret0 = select i1 %icmp0, i32 %sub0, i32 %sub1
store volatile i32 %ret0, i32 *undef store volatile i32 %ret0, i32 addrspace(5)*undef
%ret = add i32 %ret0, %c %ret = add i32 %ret0, %c
store i32 %ret, i32 addrspace(1)* %out store i32 %ret, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}v_sad_u32_vector_pat1: ; GCN-LABEL: {{^}}v_sad_u32_vector_pat1:
▲ Show 20 Lines • Show All 131 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/scratch-buffer.ll

Show All 9 Lines
; GCN-LABEL: {{^}}legal_offset_fi: ; GCN-LABEL: {{^}}legal_offset_fi:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offset:4{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offset:4{{$}}
; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x8004 ; GCN: v_mov_b32_e32 [[OFFSET:v[0-9]+]], 0x8004
; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}}
define amdgpu_kernel void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) { define amdgpu_kernel void @legal_offset_fi(i32 addrspace(1)* %out, i32 %cond, i32 %if_offset, i32 %else_offset) {
entry: entry:
%scratch0 = alloca [8192 x i32] %scratch0 = alloca [8192 x i32], addrspace(5)
%scratch1 = alloca [8192 x i32] %scratch1 = alloca [8192 x i32], addrspace(5)
%scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 0 %scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 0
store i32 1, i32* %scratchptr0 store i32 1, i32 addrspace(5)* %scratchptr0
%scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 0 %scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 0
store i32 2, i32* %scratchptr1 store i32 2, i32 addrspace(5)* %scratchptr1
%cmp = icmp eq i32 %cond, 0 %cmp = icmp eq i32 %cond, 0
br i1 %cmp, label %if, label %else br i1 %cmp, label %if, label %else
if: if:
%if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
%if_value = load i32, i32* %if_ptr %if_value = load i32, i32 addrspace(5)* %if_ptr
br label %done br label %done
else: else:
%else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
%else_value = load i32, i32* %else_ptr %else_value = load i32, i32 addrspace(5)* %else_ptr
br label %done br label %done
done: done:
%value = phi i32 [%if_value, %if], [%else_value, %else] %value = phi i32 [%if_value, %if], [%else_value, %else]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
ret void ret void
} }
; GCN-LABEL: {{^}}legal_offset_fi_offset: ; GCN-LABEL: {{^}}legal_offset_fi_offset:
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} ; GCN-DAG: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}}
; This constant isn't folded, because it has multiple uses. ; This constant isn't folded, because it has multiple uses.
; GCN-DAG: v_mov_b32_e32 [[K8000:v[0-9]+]], 0x8004 ; GCN-DAG: v_mov_b32_e32 [[K8000:v[0-9]+]], 0x8004
; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, [[K8000]] ; GCN-DAG: v_add_{{[iu]}}32_e32 [[OFFSET:v[0-9]+]], vcc, [[K8000]]
; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[OFFSET]], s[{{[0-9]+}}:{{[0-9]+}}], s{{[0-9]+}} offen{{$}}
define amdgpu_kernel void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) { define amdgpu_kernel void @legal_offset_fi_offset(i32 addrspace(1)* %out, i32 %cond, i32 addrspace(1)* %offsets, i32 %if_offset, i32 %else_offset) {
entry: entry:
%scratch0 = alloca [8192 x i32] %scratch0 = alloca [8192 x i32], addrspace(5)
%scratch1 = alloca [8192 x i32] %scratch1 = alloca [8192 x i32], addrspace(5)
%offset0 = load i32, i32 addrspace(1)* %offsets %offset0 = load i32, i32 addrspace(1)* %offsets
%scratchptr0 = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %offset0 %scratchptr0 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %offset0
store i32 %offset0, i32* %scratchptr0 store i32 %offset0, i32 addrspace(5)* %scratchptr0
%offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1 %offsetptr1 = getelementptr i32, i32 addrspace(1)* %offsets, i32 1
%offset1 = load i32, i32 addrspace(1)* %offsetptr1 %offset1 = load i32, i32 addrspace(1)* %offsetptr1
%scratchptr1 = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %offset1 %scratchptr1 = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %offset1
store i32 %offset1, i32* %scratchptr1 store i32 %offset1, i32 addrspace(5)* %scratchptr1
%cmp = icmp eq i32 %cond, 0 %cmp = icmp eq i32 %cond, 0
br i1 %cmp, label %if, label %else br i1 %cmp, label %if, label %else
if: if:
%if_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch0, i32 0, i32 %if_offset %if_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch0, i32 0, i32 %if_offset
%if_value = load i32, i32* %if_ptr %if_value = load i32, i32 addrspace(5)* %if_ptr
br label %done br label %done
else: else:
%else_ptr = getelementptr [8192 x i32], [8192 x i32]* %scratch1, i32 0, i32 %else_offset %else_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %scratch1, i32 0, i32 %else_offset
%else_value = load i32, i32* %else_ptr %else_value = load i32, i32 addrspace(5)* %else_ptr
br label %done br label %done
done: done:
%value = phi i32 [%if_value, %if], [%else_value, %else] %value = phi i32 [%if_value, %if], [%else_value, %else]
store i32 %value, i32 addrspace(1)* %out store i32 %value, i32 addrspace(1)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}neg_vaddr_offset_inbounds: ; GCN-LABEL: {{^}}neg_vaddr_offset_inbounds:
; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}} ; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}}
define amdgpu_kernel void @neg_vaddr_offset_inbounds(i32 %offset) { define amdgpu_kernel void @neg_vaddr_offset_inbounds(i32 %offset) {
entry: entry:
%array = alloca [8192 x i32] %array = alloca [8192 x i32], addrspace(5)
%ptr_offset = add i32 %offset, 4 %ptr_offset = add i32 %offset, 4
%ptr = getelementptr inbounds [8192 x i32], [8192 x i32]* %array, i32 0, i32 %ptr_offset %ptr = getelementptr inbounds [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset
store i32 0, i32* %ptr store i32 0, i32 addrspace(5)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}neg_vaddr_offset: ; GCN-LABEL: {{^}}neg_vaddr_offset:
; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}} ; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 16, v{{[0-9]+}}
; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offen{{$}}
define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) { define amdgpu_kernel void @neg_vaddr_offset(i32 %offset) {
entry: entry:
%array = alloca [8192 x i32] %array = alloca [8192 x i32], addrspace(5)
%ptr_offset = add i32 %offset, 4 %ptr_offset = add i32 %offset, 4
%ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %ptr_offset %ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %ptr_offset
store i32 0, i32* %ptr store i32 0, i32 addrspace(5)* %ptr
ret void ret void
} }
; GCN-LABEL: {{^}}pos_vaddr_offset: ; GCN-LABEL: {{^}}pos_vaddr_offset:
; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:20 ; GCN: buffer_store_dword v{{[0-9]+}}, off, s[{{[0-9]+:[0-9]+}}], s{{[0-9]+}} offset:20
define amdgpu_kernel void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) { define amdgpu_kernel void @pos_vaddr_offset(i32 addrspace(1)* %out, i32 %offset) {
entry: entry:
%array = alloca [8192 x i32] %array = alloca [8192 x i32], addrspace(5)
%ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 4 %ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 4
store i32 0, i32* %ptr store i32 0, i32 addrspace(5)* %ptr
%load_ptr = getelementptr [8192 x i32], [8192 x i32]* %array, i32 0, i32 %offset %load_ptr = getelementptr [8192 x i32], [8192 x i32] addrspace(5)* %array, i32 0, i32 %offset
%val = load i32, i32* %load_ptr %val = load i32, i32 addrspace(5)* %load_ptr
store i32 %val, i32 addrspace(1)* %out store i32 %val, i32 addrspace(1)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/scripts/chaddr.sh

Show First 20 Lines • Show All 72 Lines • ▼ Show 20 Linessed -i \
-e '/^ *;.*: *[A-Z][A-Z][A-Z]/s: addrspace(5)\*:*:g' \ -e '/^ *;.*: *[A-Z][A-Z][A-Z]/s: addrspace(5)\*:*:g' \
$newf $newf
sed -i \ sed -i \
-e 's: addrspace(x) *\*: addrspace(4)*:g' \ -e 's: addrspace(x) *\*: addrspace(4)*:g' \
$newf $newf
## add missing datalayout ## add missing datalayout
if [[ $file == *.ll ]] && { grep alloca $file >/dev/null || grep '; *RUN: *opt ' $file >/dev/null; } && ! grep datalayout $file >/dev/null; then if [[ $file == *.ll ]] && grep '; *RUN: *opt ' $file >/dev/null && ! grep datalayout $file >/dev/null; then
line=$(cat -n $file | grep ';.*RUN'| tail -1 |while read a b; do echo $a; done) sed -i 's:opt:opt -data-layout=A5:' $file
let "line=line+1"
sed -i "${line}i"'target datalayout = "A5"' $newf
fi fi

test/CodeGen/AMDGPU/shl_add_ptr.ll

Show First 20 Lines • Show All 336 Lines • ▼ Show 20 Lines
; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 3, v0 ; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 3, v0
; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], s4 offen offset:32 ; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], s4 offen offset:32
define void @shl_add_ptr_combine_2use_private(i16 zeroext %idx.arg) #0 { define void @shl_add_ptr_combine_2use_private(i16 zeroext %idx.arg) #0 {
%idx = zext i16 %idx.arg to i32 %idx = zext i16 %idx.arg to i32
%idx.add = add nuw i32 %idx, 4 %idx.add = add nuw i32 %idx, 4
%shl0 = shl i32 %idx.add, 2 %shl0 = shl i32 %idx.add, 2
%shl1 = shl i32 %idx.add, 3 %shl1 = shl i32 %idx.add, 3
%ptr0 = inttoptr i32 %shl0 to i32* %ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)*
%ptr1 = inttoptr i32 %shl1 to i32* %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
store volatile i32 9, i32* %ptr0 store volatile i32 9, i32 addrspace(5)* %ptr0
store volatile i32 10, i32* %ptr1 store volatile i32 10, i32 addrspace(5)* %ptr1
ret void ret void
} }
; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_max_private_offset: ; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_max_private_offset:
; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0
; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0 ; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], s4 offen offset:4088 ; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], s4 offen offset:4088
; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x1ff0, [[SCALE1]] ; GCN-DAG: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x1ff0, [[SCALE1]]
; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[0:3], s4 offen{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[ADD]], s[0:3], s4 offen{{$}}
define void @shl_add_ptr_combine_2use_max_private_offset(i16 zeroext %idx.arg) #0 { define void @shl_add_ptr_combine_2use_max_private_offset(i16 zeroext %idx.arg) #0 {
%idx = zext i16 %idx.arg to i32 %idx = zext i16 %idx.arg to i32
%idx.add = add nuw i32 %idx, 511 %idx.add = add nuw i32 %idx, 511
%shl0 = shl i32 %idx.add, 3 %shl0 = shl i32 %idx.add, 3
%shl1 = shl i32 %idx.add, 4 %shl1 = shl i32 %idx.add, 4
%ptr0 = inttoptr i32 %shl0 to i32* %ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)*
%ptr1 = inttoptr i32 %shl1 to i32* %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
store volatile i32 9, i32* %ptr0 store volatile i32 9, i32 addrspace(5)* %ptr0
store volatile i32 10, i32* %ptr1 store volatile i32 10, i32 addrspace(5)* %ptr1
ret void ret void
} }
; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_both_max_private_offset: ; GCN-LABEL: {{^}}shl_add_ptr_combine_2use_both_max_private_offset:
; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x100, v0 ; GCN: v_add_{{[iu]}}32_e32 [[ADD:v[0-9]+]], vcc, 0x100, v0
; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 4, [[ADD]] ; GCN-DAG: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 4, [[ADD]]
; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 5, [[ADD]] ; GCN-DAG: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 5, [[ADD]]
; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], s4 offen{{$}} ; GCN-DAG: buffer_store_dword v{{[0-9]+}}, [[SCALE0]], s[0:3], s4 offen{{$}}
; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], s4 offen{{$}} ; GCN: buffer_store_dword v{{[0-9]+}}, [[SCALE1]], s[0:3], s4 offen{{$}}
define void @shl_add_ptr_combine_2use_both_max_private_offset(i16 zeroext %idx.arg) #0 { define void @shl_add_ptr_combine_2use_both_max_private_offset(i16 zeroext %idx.arg) #0 {
%idx = zext i16 %idx.arg to i32 %idx = zext i16 %idx.arg to i32
%idx.add = add nuw i32 %idx, 256 %idx.add = add nuw i32 %idx, 256
%shl0 = shl i32 %idx.add, 4 %shl0 = shl i32 %idx.add, 4
%shl1 = shl i32 %idx.add, 5 %shl1 = shl i32 %idx.add, 5
%ptr0 = inttoptr i32 %shl0 to i32* %ptr0 = inttoptr i32 %shl0 to i32 addrspace(5)*
%ptr1 = inttoptr i32 %shl1 to i32* %ptr1 = inttoptr i32 %shl1 to i32 addrspace(5)*
store volatile i32 9, i32* %ptr0 store volatile i32 9, i32 addrspace(5)* %ptr0
store volatile i32 10, i32* %ptr1 store volatile i32 10, i32 addrspace(5)* %ptr1
ret void ret void
} }
; GCN-LABEL: {{^}}shl_or_ptr_combine_2use_lds: ; GCN-LABEL: {{^}}shl_or_ptr_combine_2use_lds:
; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0 ; GCN: v_lshlrev_b32_e32 [[SCALE0:v[0-9]+]], 3, v0
; GCN: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:32 ; GCN: ds_write_b32 [[SCALE0]], v{{[0-9]+}} offset:32
; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0 ; GCN: v_lshlrev_b32_e32 [[SCALE1:v[0-9]+]], 4, v0
Show All 31 Lines

test/CodeGen/AMDGPU/spill-empty-live-interval.mir

# RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s # RUN: llc -mtriple=amdgcn-amd-amdhsa-opencl -verify-machineinstrs -stress-regalloc=1 -start-before=simple-register-coalescing -stop-after=greedy -o - %s | FileCheck %s
# https://bugs.llvm.org/show_bug.cgi?id=33620 # https://bugs.llvm.org/show_bug.cgi?id=33620
--- ---
# This would assert due to the empty live interval created for %9 # This would assert due to the empty live interval created for %9
# on the last S_NOP with an undef subreg use. # on the last S_NOP with an undef subreg use.
# CHECK-LABEL: name: expecting_non_empty_interval # CHECK-LABEL: name: expecting_non_empty_interval
# CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit %exec # CHECK: undef %7.sub1:vreg_64 = V_MAC_F32_e32 0, undef %1:vgpr_32, undef %7.sub1, implicit %exec
# CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 8 into %stack.0, align 4) # CHECK-NEXT: SI_SPILL_V64_SAVE %7, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 8 into %stack.0, align 4, addrspace 5)
# CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit %exec # CHECK-NEXT: undef %5.sub1:vreg_64 = V_MOV_B32_e32 1786773504, implicit %exec
# CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit %exec # CHECK-NEXT: dead %2:vgpr_32 = V_MUL_F32_e32 0, %5.sub1, implicit %exec
# CHECK: S_NOP 0, implicit %6.sub1 # CHECK: S_NOP 0, implicit %6.sub1
# CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 8 from %stack.0, align 4) # CHECK-NEXT: %8:vreg_64 = SI_SPILL_V64_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 8 from %stack.0, align 4, addrspace 5)
# CHECK-NEXT: S_NOP 0, implicit %8.sub1 # CHECK-NEXT: S_NOP 0, implicit %8.sub1
# CHECK-NEXT: S_NOP 0, implicit undef %9.sub0 # CHECK-NEXT: S_NOP 0, implicit undef %9.sub0
name: expecting_non_empty_interval name: expecting_non_empty_interval
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vreg_64, preferred-register: '' } - { id: 0, class: vreg_64, preferred-register: '' }
- { id: 1, class: vgpr_32, preferred-register: '' } - { id: 1, class: vgpr_32, preferred-register: '' }
▲ Show 20 Lines • Show All 49 Lines • Show Last 20 Lines

test/CodeGen/AMDGPU/stack-size-overflow.ll

; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck -check-prefix=ERROR %s ; RUN: not llc -march=amdgcn < %s 2>&1 | FileCheck -check-prefix=ERROR %s
; RUN: not llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s ; RUN: not llc -march=amdgcn < %s | FileCheck -check-prefix=GCN %s
declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i1) #1 declare void @llvm.memset.p5i8.i32(i8 addrspace(5)* nocapture, i8, i32, i32, i1) #1
; ERROR: error: stack size limit exceeded (4294967296) in stack_size_limit ; ERROR: error: stack size limit exceeded (4294967296) in stack_size_limit
; GCN: ; ScratchSize: 4294967296 ; GCN: ; ScratchSize: 4294967296
define amdgpu_kernel void @stack_size_limit() #0 { define amdgpu_kernel void @stack_size_limit() #0 {
entry: entry:
%alloca = alloca [1073741823 x i32], align 4 %alloca = alloca [1073741823 x i32], align 4, addrspace(5)
%bc = bitcast [1073741823 x i32]* %alloca to i8* %bc = bitcast [1073741823 x i32] addrspace(5)* %alloca to i8 addrspace(5)*
call void @llvm.memset.p0i8.i32(i8* %bc, i8 9, i32 1073741823, i1 true) call void @llvm.memset.p5i8.i32(i8 addrspace(5)* %bc, i8 9, i32 1073741823, i32 1, i1 true)
ret void ret void
} }

test/CodeGen/AMDGPU/stack-slot-color-sgpr-vgpr-spills.mir

# RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -stress-regalloc=1 -start-before=greedy -stop-after=stack-slot-coloring -o - %s | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs -stress-regalloc=1 -start-before=greedy -stop-after=stack-slot-coloring -o - %s | FileCheck %s
--- ---
# CHECK-LABEL: name: no_merge_sgpr_vgpr_spill_slot{{$}} # CHECK-LABEL: name: no_merge_sgpr_vgpr_spill_slot{{$}}
# CHECK: stack: # CHECK: stack:
# CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, # CHECK: - { id: 0, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# CHECK-NEXT: stack-id: 0, # CHECK-NEXT: stack-id: 0,
# CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4, # CHECK: - { id: 1, name: '', type: spill-slot, offset: 0, size: 4, alignment: 4,
# CHECK-NEXT: stack-id: 1, # CHECK-NEXT: stack-id: 1,
# CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0) # CHECK: SI_SPILL_V32_SAVE killed %vgpr0, %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (store 4 into %stack.0, addrspace 5)
# CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0) # CHECK: %vgpr0 = SI_SPILL_V32_RESTORE %stack.0, %sgpr0_sgpr1_sgpr2_sgpr3, %sgpr5, 0, implicit %exec :: (load 4 from %stack.0, addrspace 5)
# CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1) # CHECK: SI_SPILL_S32_SAVE killed renamable %sgpr6, %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (store 4 into %stack.1, addrspace 5)
# CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1) # CHECK: %sgpr6 = SI_SPILL_S32_RESTORE %stack.1, implicit %exec, implicit %sgpr0_sgpr1_sgpr2_sgpr3, implicit %sgpr5, implicit-def dead %m0 :: (load 4 from %stack.1, addrspace 5)
name: no_merge_sgpr_vgpr_spill_slot name: no_merge_sgpr_vgpr_spill_slot
tracksRegLiveness: true tracksRegLiveness: true
registers: registers:
- { id: 0, class: vgpr_32 } - { id: 0, class: vgpr_32 }
- { id: 1, class: sreg_32_xm0_xexec } - { id: 1, class: sreg_32_xm0_xexec }
- { id: 2, class: vgpr_32 } - { id: 2, class: vgpr_32 }
- { id: 3, class: sreg_32_xm0_xexec } - { id: 3, class: sreg_32_xm0_xexec }
Show All 10 Lines

test/CodeGen/AMDGPU/store-hi16.ll

Show First 20 Lines • Show All 181 Lines • ▼ Show 20 Lines
; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}} ; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: flat_store_short v[0:1], v2 ; VI-NEXT: flat_store_short v[0:1], v2
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16(i16 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16(i16* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
store i16 %hi, i16 addrspace(4)* %out store i16 %hi, i16* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_v2f16: ; GCN-LABEL: {{^}}store_flat_hi_v2f16:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}} ; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: flat_store_short v[0:1], v2 ; VI-NEXT: flat_store_short v[0:1], v2
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2f16(half addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2f16(half* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x half> %value = bitcast i32 %arg to <2 x half>
%hi = extractelement <2 x half> %value, i32 1 %hi = extractelement <2 x half> %value, i32 1
store half %hi, half addrspace(4)* %out store half %hi, half* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_i32_shift: ; GCN-LABEL: {{^}}store_flat_hi_i32_shift:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}} ; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: flat_store_short v[0:1], v2 ; VI-NEXT: flat_store_short v[0:1], v2
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_i32_shift(i16 addrspace(4)* %out, i32 %value) #0 { define void @store_flat_hi_i32_shift(i16* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i16 %hi = trunc i32 %hi32 to i16
store i16 %hi, i16 addrspace(4)* %out store i16 %hi, i16* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8: ; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}} ; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: flat_store_byte v[0:1], v2 ; VI-NEXT: flat_store_byte v[0:1], v2
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8(i8 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_i8(i8* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store i8 %trunc, i8 addrspace(4)* %out store i8 %trunc, i8* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_i8_shift: ; GCN-LABEL: {{^}}store_flat_hi_i8_shift:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}} ; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2 ; VI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
; VI-NEXT: flat_store_byte v[0:1], v2 ; VI-NEXT: flat_store_byte v[0:1], v2
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_i8_shift(i8 addrspace(4)* %out, i32 %value) #0 { define void @store_flat_hi_i8_shift(i8* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i8 %hi = trunc i32 %hi32 to i8
store i8 %hi, i8 addrspace(4)* %out store i8 %hi, i8* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_v2i16_max_offset: ; GCN-LABEL: {{^}}store_flat_hi_v2i16_max_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2 offset:4094{{$}} ; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2 offset:4094{{$}}
; VI-DAG: v_add_u32_e32 ; VI-DAG: v_add_u32_e32
; VI-DAG: v_addc_u32_e32 ; VI-DAG: v_addc_u32_e32
; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2 ; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
; VI: flat_store_short v[0:1], v2{{$}} ; VI: flat_store_short v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_max_offset(i16 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_max_offset(i16* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds i16, i16 addrspace(4)* %out, i64 2047 %gep = getelementptr inbounds i16, i16* %out, i64 2047
store i16 %hi, i16 addrspace(4)* %gep store i16 %hi, i16* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_v2i16_neg_offset: ; GCN-LABEL: {{^}}store_flat_hi_v2i16_neg_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN: v_add{{(_co)?}}_{{i|u}}32_e32 ; GCN: v_add{{(_co)?}}_{{i|u}}32_e32
; VI: v_addc_u32_e32 ; VI: v_addc_u32_e32
; GFX9: v_addc_co_u32_e32 ; GFX9: v_addc_co_u32_e32
; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}} ; GFX9-NEXT: flat_store_short_d16_hi v[0:1], v2{{$}}
; VI: flat_store_short v[0:1], v2{{$}} ; VI: flat_store_short v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_neg_offset(i16 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_neg_offset(i16* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds i16, i16 addrspace(4)* %out, i64 -1023 %gep = getelementptr inbounds i16, i16* %out, i64 -1023
store i16 %hi, i16 addrspace(4)* %gep store i16 %hi, i16* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8_max_offset: ; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8_max_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2 offset:4095{{$}} ; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2 offset:4095{{$}}
; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2 ; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
; VI-DAG: v_add_u32_e32 ; VI-DAG: v_add_u32_e32
; VI-DAG: v_addc_u32_e32 ; VI-DAG: v_addc_u32_e32
; VI: flat_store_byte v[0:1], v2{{$}} ; VI: flat_store_byte v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8_max_offset(i8 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_i8_max_offset(i8* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
%gep = getelementptr inbounds i8, i8 addrspace(4)* %out, i64 4095 %gep = getelementptr inbounds i8, i8* %out, i64 4095
store i8 %trunc, i8 addrspace(4)* %gep store i8 %trunc, i8* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8_neg_offset: ; GCN-LABEL: {{^}}store_flat_hi_v2i16_i8_neg_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GCN-DAG: v_add{{(_co)?}}_{{i|u}}32_e32 ; GCN-DAG: v_add{{(_co)?}}_{{i|u}}32_e32
; VI-DAG: v_addc_u32_e32 ; VI-DAG: v_addc_u32_e32
; GFX9-DAG: v_addc_co_u32_e32 ; GFX9-DAG: v_addc_co_u32_e32
; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}} ; GFX9-NEXT: flat_store_byte_d16_hi v[0:1], v2{{$}}
; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2 ; VI-DAG: v_lshrrev_b32_e32 v2, 16, v2
; VI: flat_store_byte v[0:1], v2{{$}} ; VI: flat_store_byte v[0:1], v2{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_flat_hi_v2i16_i8_neg_offset(i8 addrspace(4)* %out, i32 %arg) #0 { define void @store_flat_hi_v2i16_i8_neg_offset(i8* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
%gep = getelementptr inbounds i8, i8 addrspace(4)* %out, i64 -4095 %gep = getelementptr inbounds i8, i8* %out, i64 -4095
store i8 %trunc, i8 addrspace(4)* %gep store i8 %trunc, i8* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16: ; GCN-LABEL: {{^}}store_private_hi_v2i16:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}} ; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
; VI: v_lshrrev_b32_e32 v1, 16, v1 ; VI: v_lshrrev_b32_e32 v1, 16, v1
; VI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}} ; VI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16(i16* %out, i32 %arg) #0 { define void @store_private_hi_v2i16(i16 addrspace(5)* %out, i32 %arg) #0 {
entry: entry:
; FIXME: ABI for pre-gfx9 ; FIXME: ABI for pre-gfx9
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
store i16 %hi, i16* %out store i16 %hi, i16 addrspace(5)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2f16: ; GCN-LABEL: {{^}}store_private_hi_v2f16:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}} ; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
; VI: v_lshrrev_b32_e32 v1, 16, v1 ; VI: v_lshrrev_b32_e32 v1, 16, v1
; VI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}} ; VI: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2f16(half* %out, i32 %arg) #0 { define void @store_private_hi_v2f16(half addrspace(5)* %out, i32 %arg) #0 {
entry: entry:
; FIXME: ABI for pre-gfx9 ; FIXME: ABI for pre-gfx9
%value = bitcast i32 %arg to <2 x half> %value = bitcast i32 %arg to <2 x half>
%hi = extractelement <2 x half> %value, i32 1 %hi = extractelement <2 x half> %value, i32 1
store half %hi, half* %out store half %hi, half addrspace(5)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_i32_shift: ; GCN-LABEL: {{^}}store_private_hi_i32_shift:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}} ; GFX9-NEXT: buffer_store_short_d16_hi v1, v0, s[0:3], s4 offen{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: buffer_store_short v1, v0, s[0:3], s4 offen{{$}} ; VI-NEXT: buffer_store_short v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_i32_shift(i16* %out, i32 %value) #0 { define void @store_private_hi_i32_shift(i16 addrspace(5)* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i16 %hi = trunc i32 %hi32 to i16
store i16 %hi, i16* %out store i16 %hi, i16 addrspace(5)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_i8: ; GCN-LABEL: {{^}}store_private_hi_v2i16_i8:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}} ; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}} ; VI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16_i8(i8* %out, i32 %arg) #0 { define void @store_private_hi_v2i16_i8(i8 addrspace(5)* %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store i8 %trunc, i8* %out store i8 %trunc, i8 addrspace(5)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_i8_shift: ; GCN-LABEL: {{^}}store_private_hi_i8_shift:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}} ; GFX9-NEXT: buffer_store_byte_d16_hi v1, v0, s[0:3], s4 offen{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1 ; VI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
; VI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}} ; VI-NEXT: buffer_store_byte v1, v0, s[0:3], s4 offen{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_i8_shift(i8* %out, i32 %value) #0 { define void @store_private_hi_i8_shift(i8 addrspace(5)* %out, i32 %value) #0 {
entry: entry:
%hi32 = lshr i32 %value, 16 %hi32 = lshr i32 %value, 16
%hi = trunc i32 %hi32 to i8 %hi = trunc i32 %hi32 to i8
store i8 %hi, i8* %out store i8 %hi, i8 addrspace(5)* %out
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_max_offset: ; GCN-LABEL: {{^}}store_private_hi_v2i16_max_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}} ; GFX9: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094{{$}}
; VI: v_lshrrev_b32_e32 v0, 16, v0 ; VI: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: buffer_store_short v0, off, s[0:3], s5 offset:4094{{$}} ; VI-NEXT: buffer_store_short v0, off, s[0:3], s5 offset:4094{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16_max_offset(i16* byval %out, i32 %arg) #0 { define void @store_private_hi_v2i16_max_offset(i16 addrspace(5)* byval %out, i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds i16, i16* %out, i64 2045 %gep = getelementptr inbounds i16, i16 addrspace(5)* %out, i64 2045
store i16 %hi, i16* %gep store i16 %hi, i16 addrspace(5)* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_nooff: ; GCN-LABEL: {{^}}store_private_hi_v2i16_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s4{{$}} ; GFX9-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s4{{$}}
; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0 ; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; VI-NEXT: buffer_store_short v0, off, s[0:3], s4{{$}} ; VI-NEXT: buffer_store_short v0, off, s[0:3], s4{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16_nooff(i32 %arg) #0 { define void @store_private_hi_v2i16_nooff(i32 %arg) #0 {
entry: entry:
; FIXME: ABI for pre-gfx9 ; FIXME: ABI for pre-gfx9
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
store volatile i16 %hi, i16* null store volatile i16 %hi, i16 addrspace(5)* null
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_nooff: ; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_nooff:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s4{{$}} ; GFX9-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s4{{$}}
; VI: v_lshrrev_b32_e32 v0, 16, v0 ; VI: v_lshrrev_b32_e32 v0, 16, v0
; VI: buffer_store_byte v0, off, s[0:3], s4{{$}} ; VI: buffer_store_byte v0, off, s[0:3], s4{{$}}
; GCN-NEXT: s_waitcnt ; GCN-NEXT: s_waitcnt
; GCN-NEXT: s_setpc_b64 ; GCN-NEXT: s_setpc_b64
define void @store_private_hi_v2i16_i8_nooff(i32 %arg) #0 { define void @store_private_hi_v2i16_i8_nooff(i32 %arg) #0 {
entry: entry:
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store volatile i8 %trunc, i8* null store volatile i8 %trunc, i8 addrspace(5)* null
ret void ret void
} }
; GCN-LABEL: {{^}}store_local_hi_v2i16: ; GCN-LABEL: {{^}}store_local_hi_v2i16:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9-NEXT: ds_write_b16_d16_hi v0, v1{{$}} ; GFX9-NEXT: ds_write_b16_d16_hi v0, v1{{$}}
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} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_to_offset: ; GCN-LABEL: {{^}}store_private_hi_v2i16_to_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094 ; GFX9-NEXT: buffer_store_short_d16_hi v0, off, s[0:3], s5 offset:4094
define void @store_private_hi_v2i16_to_offset(i32 %arg) #0 { define void @store_private_hi_v2i16_to_offset(i32 %arg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i16], align 2 %obj1 = alloca [4096 x i16], align 2, addrspace(5)
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds [4096 x i16], [4096 x i16]* %obj1, i32 0, i32 2025 %gep = getelementptr inbounds [4096 x i16], [4096 x i16] addrspace(5)* %obj1, i32 0, i32 2025
store i16 %hi, i16* %gep store i16 %hi, i16 addrspace(5)* %gep
ret void ret void
} }
; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_to_offset: ; GCN-LABEL: {{^}}store_private_hi_v2i16_i8_to_offset:
; GCN: s_waitcnt ; GCN: s_waitcnt
; GFX9: buffer_store_dword ; GFX9: buffer_store_dword
; GFX9-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s5 offset:4095 ; GFX9-NEXT: buffer_store_byte_d16_hi v0, off, s[0:3], s5 offset:4095
define void @store_private_hi_v2i16_i8_to_offset(i32 %arg) #0 { define void @store_private_hi_v2i16_i8_to_offset(i32 %arg) #0 {
entry: entry:
%obj0 = alloca [10 x i32], align 4 %obj0 = alloca [10 x i32], align 4, addrspace(5)
%obj1 = alloca [4096 x i8], align 2 %obj1 = alloca [4096 x i8], align 2, addrspace(5)
%bc = bitcast [10 x i32]* %obj0 to i32* %bc = bitcast [10 x i32] addrspace(5)* %obj0 to i32 addrspace(5)*
store volatile i32 123, i32* %bc store volatile i32 123, i32 addrspace(5)* %bc
%value = bitcast i32 %arg to <2 x i16> %value = bitcast i32 %arg to <2 x i16>
%hi = extractelement <2 x i16> %value, i32 1 %hi = extractelement <2 x i16> %value, i32 1
%gep = getelementptr inbounds [4096 x i8], [4096 x i8]* %obj1, i32 0, i32 4051 %gep = getelementptr inbounds [4096 x i8], [4096 x i8] addrspace(5)* %obj1, i32 0, i32 4051
%trunc = trunc i16 %hi to i8 %trunc = trunc i16 %hi to i8
store i8 %trunc, i8* %gep store i8 %trunc, i8 addrspace(5)* %gep
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/store-private.ll

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; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_i1(i1 addrspace(0)* %out) { define amdgpu_kernel void @store_i1(i1 addrspace(5)* %out) {
entry: entry:
store i1 true, i1 addrspace(0)* %out store i1 true, i1 addrspace(5)* %out
ret void ret void
} }
; i8 store ; i8 store
; FUNC-LABEL: {{^}}store_i8: ; FUNC-LABEL: {{^}}store_i8:
; EG: LSHR * [[ADDRESS:T[0-9]\.[XYZW]]], KC0[2].Y, literal.x ; EG: LSHR * [[ADDRESS:T[0-9]\.[XYZW]]], KC0[2].Y, literal.x
; EG-NEXT: 2 ; EG-NEXT: 2
; EG: MOVA_INT * AR.x (MASKED) ; EG: MOVA_INT * AR.x (MASKED)
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; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]] ; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]]
; EG: OR_INT * [[RES:T[0-9]\.[XYZW]]] ; EG: OR_INT * [[RES:T[0-9]\.[XYZW]]]
; TODO: Is the reload necessary? ; TODO: Is the reload necessary?
; EG: MOVA_INT * AR.x (MASKED), [[ADDRESS]] ; EG: MOVA_INT * AR.x (MASKED), [[ADDRESS]]
; EG: MOV * T(0 + AR.x).X+, [[RES]] ; EG: MOV * T(0 + AR.x).X+, [[RES]]
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_i8(i8 addrspace(0)* %out, i8 %in) { define amdgpu_kernel void @store_i8(i8 addrspace(5)* %out, i8 %in) {
entry: entry:
store i8 %in, i8 addrspace(0)* %out store i8 %in, i8 addrspace(5)* %out
ret void ret void
} }
; i16 store ; i16 store
; FUNC-LABEL: {{^}}store_i16: ; FUNC-LABEL: {{^}}store_i16:
; EG: LSHR * [[ADDRESS:T[0-9]\.[XYZW]]], KC0[2].Y, literal.x ; EG: LSHR * [[ADDRESS:T[0-9]\.[XYZW]]], KC0[2].Y, literal.x
; EG-NEXT: 2 ; EG-NEXT: 2
; EG: MOVA_INT * AR.x (MASKED) ; EG: MOVA_INT * AR.x (MASKED)
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; EG: NOT_INT ; EG: NOT_INT
; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]] ; EG: AND_INT {{[\* ]*}}[[CLR_CHAN:T[0-9]\.[XYZW]]], {{.*}}[[OLD]]
; EG: OR_INT * [[RES:T[0-9]\.[XYZW]]] ; EG: OR_INT * [[RES:T[0-9]\.[XYZW]]]
; TODO: Is the reload necessary? ; TODO: Is the reload necessary?
; EG: MOVA_INT * AR.x (MASKED), [[ADDRESS]] ; EG: MOVA_INT * AR.x (MASKED), [[ADDRESS]]
; EG: MOV * T(0 + AR.x).X+, [[RES]] ; EG: MOV * T(0 + AR.x).X+, [[RES]]
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_i16(i16 addrspace(0)* %out, i16 %in) { define amdgpu_kernel void @store_i16(i16 addrspace(5)* %out, i16 %in) {
entry: entry:
store i16 %in, i16 addrspace(0)* %out store i16 %in, i16 addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_i24: ; FUNC-LABEL: {{^}}store_i24:
; SI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16 ; SI: s_lshr_b32 s{{[0-9]+}}, s{{[0-9]+}}, 16
; SI-DAG: buffer_store_byte ; SI-DAG: buffer_store_byte
; SI-DAG: buffer_store_short ; SI-DAG: buffer_store_short
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; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; TODO: This load and store can be eliminated ; TODO: This load and store can be eliminated
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
define amdgpu_kernel void @store_i24(i24 addrspace(0)* %out, i24 %in) { define amdgpu_kernel void @store_i24(i24 addrspace(5)* %out, i24 %in) {
entry: entry:
store i24 %in, i24 addrspace(0)* %out store i24 %in, i24 addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_i25: ; FUNC-LABEL: {{^}}store_i25:
; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}} ; SI: s_and_b32 [[AND:s[0-9]+]], s{{[0-9]+}}, 0x1ffffff{{$}}
; SI: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]] ; SI: v_mov_b32_e32 [[VAND:v[0-9]+]], [[AND]]
; SI: buffer_store_dword [[VAND]] ; SI: buffer_store_dword [[VAND]]
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
define amdgpu_kernel void @store_i25(i25 addrspace(0)* %out, i25 %in) { define amdgpu_kernel void @store_i25(i25 addrspace(5)* %out, i25 %in) {
entry: entry:
store i25 %in, i25 addrspace(0)* %out store i25 %in, i25 addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v2i8: ; FUNC-LABEL: {{^}}store_v2i8:
; v2i8 is naturally 2B aligned, treat as i16 ; v2i8 is naturally 2B aligned, treat as i16
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i8(<2 x i8> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i8> %0 = trunc <2 x i32> %in to <2 x i8>
store <2 x i8> %0, <2 x i8> addrspace(0)* %out store <2 x i8> %0, <2 x i8> addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v2i8_unaligned: ; FUNC-LABEL: {{^}}store_v2i8_unaligned:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; TODO: This load and store cannot be eliminated, ; TODO: This load and store cannot be eliminated,
; they might be different locations ; they might be different locations
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_v2i8_unaligned(<2 x i8> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i8_unaligned(<2 x i8> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i8> %0 = trunc <2 x i32> %in to <2 x i8>
store <2 x i8> %0, <2 x i8> addrspace(0)* %out, align 1 store <2 x i8> %0, <2 x i8> addrspace(5)* %out, align 1
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v2i16: ; FUNC-LABEL: {{^}}store_v2i16:
; v2i8 is naturally 2B aligned, treat as i16 ; v2i8 is naturally 2B aligned, treat as i16
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i16(<2 x i16> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i16> %0 = trunc <2 x i32> %in to <2 x i16>
store <2 x i16> %0, <2 x i16> addrspace(0)* %out store <2 x i16> %0, <2 x i16> addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v2i16_unaligned: ; FUNC-LABEL: {{^}}store_v2i16_unaligned:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; they might be different locations ; they might be different locations
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_short ; SI: buffer_store_short
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(0)* %out, <2 x i32> %in) { define amdgpu_kernel void @store_v2i16_unaligned(<2 x i16> addrspace(5)* %out, <2 x i32> %in) {
entry: entry:
%0 = trunc <2 x i32> %in to <2 x i16> %0 = trunc <2 x i32> %in to <2 x i16>
store <2 x i16> %0, <2 x i16> addrspace(0)* %out, align 2 store <2 x i16> %0, <2 x i16> addrspace(5)* %out, align 2
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v4i8: ; FUNC-LABEL: {{^}}store_v4i8:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG-NOT: MOVA_INT ; EG-NOT: MOVA_INT
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM-NOT: MOVA_INT ; CM-NOT: MOVA_INT
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i8(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i8> %0 = trunc <4 x i32> %in to <4 x i8>
store <4 x i8> %0, <4 x i8> addrspace(0)* %out store <4 x i8> %0, <4 x i8> addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v4i8_unaligned: ; FUNC-LABEL: {{^}}store_v4i8_unaligned:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI-NOT: buffer_store_dword ; SI-NOT: buffer_store_dword
define amdgpu_kernel void @store_v4i8_unaligned(<4 x i8> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i8_unaligned(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i8> %0 = trunc <4 x i32> %in to <4 x i8>
store <4 x i8> %0, <4 x i8> addrspace(0)* %out, align 1 store <4 x i8> %0, <4 x i8> addrspace(5)* %out, align 1
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v8i8_unaligned: ; FUNC-LABEL: {{^}}store_v8i8_unaligned:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI: buffer_store_byte ; SI: buffer_store_byte
; SI-NOT: buffer_store_dword ; SI-NOT: buffer_store_dword
define amdgpu_kernel void @store_v8i8_unaligned(<8 x i8> addrspace(0)* %out, <8 x i32> %in) { define amdgpu_kernel void @store_v8i8_unaligned(<8 x i8> addrspace(5)* %out, <8 x i32> %in) {
entry: entry:
%0 = trunc <8 x i32> %in to <8 x i8> %0 = trunc <8 x i32> %in to <8 x i8>
store <8 x i8> %0, <8 x i8> addrspace(0)* %out, align 1 store <8 x i8> %0, <8 x i8> addrspace(5)* %out, align 1
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v4i8_halfaligned: ; FUNC-LABEL: {{^}}store_v4i8_halfaligned:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_short ; SI: buffer_store_short
; SI: buffer_store_short ; SI: buffer_store_short
; SI-NOT: buffer_store_dword ; SI-NOT: buffer_store_dword
define amdgpu_kernel void @store_v4i8_halfaligned(<4 x i8> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i8_halfaligned(<4 x i8> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i8> %0 = trunc <4 x i32> %in to <4 x i8>
store <4 x i8> %0, <4 x i8> addrspace(0)* %out, align 2 store <4 x i8> %0, <4 x i8> addrspace(5)* %out, align 2
ret void ret void
} }
; floating-point store ; floating-point store
; FUNC-LABEL: {{^}}store_f32: ; FUNC-LABEL: {{^}}store_f32:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_f32(float addrspace(0)* %out, float %in) { define amdgpu_kernel void @store_f32(float addrspace(5)* %out, float %in) {
store float %in, float addrspace(0)* %out store float %in, float addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v4i16: ; FUNC-LABEL: {{^}}store_v4i16:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x2? ;TODO: why not x2?
; XSI: buffer_store_dwordx2 ; XSI: buffer_store_dwordx2
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i16(<4 x i16> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
%0 = trunc <4 x i32> %in to <4 x i16> %0 = trunc <4 x i32> %in to <4 x i16>
store <4 x i16> %0, <4 x i16> addrspace(0)* %out store <4 x i16> %0, <4 x i16> addrspace(5)* %out
ret void ret void
} }
; vec2 floating-point stores ; vec2 floating-point stores
; FUNC-LABEL: {{^}}store_v2f32: ; FUNC-LABEL: {{^}}store_v2f32:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x2? ;TODO: why not x2?
; XSI: buffer_store_dwordx2 ; XSI: buffer_store_dwordx2
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(0)* %out, float %a, float %b) { define amdgpu_kernel void @store_v2f32(<2 x float> addrspace(5)* %out, float %a, float %b) {
entry: entry:
%0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0 %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0
%1 = insertelement <2 x float> %0, float %b, i32 1 %1 = insertelement <2 x float> %0, float %b, i32 1
store <2 x float> %1, <2 x float> addrspace(0)* %out store <2 x float> %1, <2 x float> addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v3i32: ; FUNC-LABEL: {{^}}store_v3i32:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x2? ;TODO: why not x2?
; XSI-DAG: buffer_store_dwordx2 ; XSI-DAG: buffer_store_dwordx2
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(0)* %out, <3 x i32> %a) nounwind { define amdgpu_kernel void @store_v3i32(<3 x i32> addrspace(5)* %out, <3 x i32> %a) nounwind {
store <3 x i32> %a, <3 x i32> addrspace(0)* %out, align 16 store <3 x i32> %a, <3 x i32> addrspace(5)* %out, align 16
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v4i32: ; FUNC-LABEL: {{^}}store_v4i32:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x4? ;TODO: why not x4?
; XSI: buffer_store_dwordx4 ; XSI: buffer_store_dwordx4
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i32(<4 x i32> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
store <4 x i32> %in, <4 x i32> addrspace(0)* %out store <4 x i32> %in, <4 x i32> addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_v4i32_unaligned: ; FUNC-LABEL: {{^}}store_v4i32_unaligned:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x4? ;TODO: why not x4?
; XSI: buffer_store_dwordx4 ; XSI: buffer_store_dwordx4
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(0)* %out, <4 x i32> %in) { define amdgpu_kernel void @store_v4i32_unaligned(<4 x i32> addrspace(5)* %out, <4 x i32> %in) {
entry: entry:
store <4 x i32> %in, <4 x i32> addrspace(0)* %out, align 4 store <4 x i32> %in, <4 x i32> addrspace(5)* %out, align 4
ret void ret void
} }
; v4f32 store ; v4f32 store
; FUNC-LABEL: {{^}}store_v4f32: ; FUNC-LABEL: {{^}}store_v4f32:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
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; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x4? ;TODO: why not x4?
; XSI: buffer_store_dwordx4 ; XSI: buffer_store_dwordx4
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(0)* %out, <4 x float> addrspace(0)* %in) { define amdgpu_kernel void @store_v4f32(<4 x float> addrspace(5)* %out, <4 x float> addrspace(5)* %in) {
%1 = load <4 x float>, <4 x float> addrspace(0) * %in %1 = load <4 x float>, <4 x float> addrspace(5)* %in
store <4 x float> %1, <4 x float> addrspace(0)* %out store <4 x float> %1, <4 x float> addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_i64_i8: ; FUNC-LABEL: {{^}}store_i64_i8:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_byte ; SI: buffer_store_byte
define amdgpu_kernel void @store_i64_i8(i8 addrspace(0)* %out, i64 %in) { define amdgpu_kernel void @store_i64_i8(i8 addrspace(5)* %out, i64 %in) {
entry: entry:
%0 = trunc i64 %in to i8 %0 = trunc i64 %in to i8
store i8 %0, i8 addrspace(0)* %out store i8 %0, i8 addrspace(5)* %out
ret void ret void
} }
; FUNC-LABEL: {{^}}store_i64_i16: ; FUNC-LABEL: {{^}}store_i64_i16:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}{{T[0-9]+\.[XYZW]}}, T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; SI: buffer_store_short ; SI: buffer_store_short
define amdgpu_kernel void @store_i64_i16(i16 addrspace(0)* %out, i64 %in) { define amdgpu_kernel void @store_i64_i16(i16 addrspace(5)* %out, i64 %in) {
entry: entry:
%0 = trunc i64 %in to i16 %0 = trunc i64 %in to i16
store i16 %0, i16 addrspace(0)* %out store i16 %0, i16 addrspace(5)* %out
ret void ret void
} }
; The stores in this function are combined by the optimizer to create a ; The stores in this function are combined by the optimizer to create a
; 64-bit store with 32-bit alignment. This is legal and the legalizer ; 64-bit store with 32-bit alignment. This is legal and the legalizer
; should not try to split the 64-bit store back into 2 32-bit stores. ; should not try to split the 64-bit store back into 2 32-bit stores.
; FUNC-LABEL: {{^}}vecload2: ; FUNC-LABEL: {{^}}vecload2:
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
; CM: MOVA_INT ; CM: MOVA_INT
; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x2? ;TODO: why not x2?
; XSI: buffer_store_dwordx2 ; XSI: buffer_store_dwordx2
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @vecload2(i32 addrspace(0)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { define amdgpu_kernel void @vecload2(i32 addrspace(5)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 {
entry: entry:
%0 = load i32, i32 addrspace(2)* %mem, align 4 %0 = load i32, i32 addrspace(2)* %mem, align 4
%arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1 %arrayidx1.i = getelementptr inbounds i32, i32 addrspace(2)* %mem, i64 1
%1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4 %1 = load i32, i32 addrspace(2)* %arrayidx1.i, align 4
store i32 %0, i32 addrspace(0)* %out, align 4 store i32 %0, i32 addrspace(5)* %out, align 4
%arrayidx1 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 1 %arrayidx1 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1
store i32 %1, i32 addrspace(0)* %arrayidx1, align 4 store i32 %1, i32 addrspace(5)* %arrayidx1, align 4
ret void ret void
} }
; When i128 was a legal type this program generated cannot select errors: ; When i128 was a legal type this program generated cannot select errors:
; FUNC-LABEL: {{^}}"i128-const-store": ; FUNC-LABEL: {{^}}"i128-const-store":
; EG: MOVA_INT ; EG: MOVA_INT
; EG: MOV {{[\* ]*}}T(0 + AR.x).X+, ; EG: MOV {{[\* ]*}}T(0 + AR.x).X+,
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; CM: MOV {{[\* ]*}}T(0 + AR.x).X+, ; CM: MOV {{[\* ]*}}T(0 + AR.x).X+,
;TODO: why not x4? ;TODO: why not x4?
; XSI: buffer_store_dwordx4 ; XSI: buffer_store_dwordx4
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
; SI: buffer_store_dword ; SI: buffer_store_dword
define amdgpu_kernel void @i128-const-store(i32 addrspace(0)* %out) { define amdgpu_kernel void @i128-const-store(i32 addrspace(5)* %out) {
entry: entry:
store i32 1, i32 addrspace(0)* %out, align 4 store i32 1, i32 addrspace(5)* %out, align 4
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 1 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 1
store i32 1, i32 addrspace(0)* %arrayidx2, align 4 store i32 1, i32 addrspace(5)* %arrayidx2, align 4
%arrayidx4 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 2 %arrayidx4 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 2
store i32 2, i32 addrspace(0)* %arrayidx4, align 4 store i32 2, i32 addrspace(5)* %arrayidx4, align 4
%arrayidx6 = getelementptr inbounds i32, i32 addrspace(0)* %out, i64 3 %arrayidx6 = getelementptr inbounds i32, i32 addrspace(5)* %out, i64 3
store i32 2, i32 addrspace(0)* %arrayidx6, align 4 store i32 2, i32 addrspace(5)* %arrayidx6, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/CodeGen/AMDGPU/store-vector-ptrs.ll

; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs< %s
; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs< %s
; This tests for a bug that caused a crash in ; This tests for a bug that caused a crash in
; AMDGPUDAGToDAGISel::SelectMUBUFScratch() which is used for selecting ; AMDGPUDAGToDAGISel::SelectMUBUFScratch() which is used for selecting
; scratch loads and stores. ; scratch loads and stores.
; CHECK-LABEL: {{^}}store_vector_ptrs: ; CHECK-LABEL: {{^}}store_vector_ptrs:
define amdgpu_kernel void @store_vector_ptrs(<4 x i32*>* %out, <4 x [1024 x i32]*> %array) nounwind { define amdgpu_kernel void @store_vector_ptrs(<4 x i32 addrspace(5)*> addrspace(5)* %out, <4 x [1024 x i32] addrspace(5)*> %array) nounwind {
%p = getelementptr [1024 x i32], <4 x [1024 x i32]*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16> %p = getelementptr [1024 x i32], <4 x [1024 x i32] addrspace(5)*> %array, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
store <4 x i32*> %p, <4 x i32*>* %out store <4 x i32 addrspace(5)*> %p, <4 x i32 addrspace(5)*> addrspace(5)* %out
ret void ret void
} }

test/CodeGen/AMDGPU/syncscopes.ll

; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -stop-before=si-debugger-insert-nops < %s | FileCheck --check-prefix=GCN %s
; GCN-LABEL: name: syncscopes ; GCN-LABEL: name: syncscopes
; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out, addrspace 4) ; GCN: FLAT_STORE_DWORD killed renamable %vgpr1_vgpr2, killed renamable %vgpr0, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("agent") seq_cst 4 into %ir.agent_out)
; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out, addrspace 4) ; GCN: FLAT_STORE_DWORD killed renamable %vgpr4_vgpr5, killed renamable %vgpr3, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("workgroup") seq_cst 4 into %ir.workgroup_out)
; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out, addrspace 4) ; GCN: FLAT_STORE_DWORD killed renamable %vgpr7_vgpr8, killed renamable %vgpr6, 0, 0, 0, implicit %exec, implicit %flat_scr :: (volatile store syncscope("wavefront") seq_cst 4 into %ir.wavefront_out)
define void @syncscopes( define void @syncscopes(
i32 %agent, i32 %agent,
i32 addrspace(4)* %agent_out, i32* %agent_out,
i32 %workgroup, i32 %workgroup,
i32 addrspace(4)* %workgroup_out, i32* %workgroup_out,
i32 %wavefront, i32 %wavefront,
i32 addrspace(4)* %wavefront_out) { i32* %wavefront_out) {
entry: entry:
store atomic i32 %agent, i32 addrspace(4)* %agent_out syncscope("agent") seq_cst, align 4 store atomic i32 %agent, i32* %agent_out syncscope("agent") seq_cst, align 4
store atomic i32 %workgroup, i32 addrspace(4)* %workgroup_out syncscope("workgroup") seq_cst, align 4 store atomic i32 %workgroup, i32* %workgroup_out syncscope("workgroup") seq_cst, align 4
store atomic i32 %wavefront, i32 addrspace(4)* %wavefront_out syncscope("wavefront") seq_cst, align 4 store atomic i32 %wavefront, i32* %wavefront_out syncscope("wavefront") seq_cst, align 4
ret void ret void
} }

test/CodeGen/AMDGPU/target-cpu.ll

Show First 20 Lines • Show All 75 Lines • ▼ Show 20 Linesdefine amdgpu_kernel void @target_fiji() #4 {
ret void ret void
} }
; CHECK-LABEL: {{^}}promote_alloca_enabled: ; CHECK-LABEL: {{^}}promote_alloca_enabled:
; CHECK: ds_read_b32 ; CHECK: ds_read_b32
; CHECK: ; LDSByteSize: 5120 ; CHECK: ; LDSByteSize: 5120
define amdgpu_kernel void @promote_alloca_enabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #5 { define amdgpu_kernel void @promote_alloca_enabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #5 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
%load = load i32, i32* %arrayidx1 %load = load i32, i32 addrspace(5)* %arrayidx1
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
; CHECK-LABEL: {{^}}promote_alloca_disabled: ; CHECK-LABEL: {{^}}promote_alloca_disabled:
; CHECK: SCRATCH_RSRC_DWORD0 ; CHECK: SCRATCH_RSRC_DWORD0
; CHECK: SCRATCH_RSRC_DWORD1 ; CHECK: SCRATCH_RSRC_DWORD1
; CHECK: ScratchSize: 24 ; CHECK: ScratchSize: 24
define amdgpu_kernel void @promote_alloca_disabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #6 { define amdgpu_kernel void @promote_alloca_disabled(i32 addrspace(1)* nocapture %out, i32 addrspace(1)* nocapture %in) #6 {
entry: entry:
%stack = alloca [5 x i32], align 4 %stack = alloca [5 x i32], align 4, addrspace(5)
%tmp = load i32, i32 addrspace(1)* %in, align 4 %tmp = load i32, i32 addrspace(1)* %in, align 4
%arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32]* %stack, i32 0, i32 %tmp %arrayidx1 = getelementptr inbounds [5 x i32], [5 x i32] addrspace(5)* %stack, i32 0, i32 %tmp
%load = load i32, i32* %arrayidx1 %load = load i32, i32 addrspace(5)* %arrayidx1
store i32 %load, i32 addrspace(1)* %out store i32 %load, i32 addrspace(1)* %out
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind "target-cpu"="tahiti" } attributes #2 = { nounwind "target-cpu"="tahiti" }
attributes #3 = { nounwind "target-cpu"="bonaire" } attributes #3 = { nounwind "target-cpu"="bonaire" }
attributes #4 = { nounwind "target-cpu"="fiji" } attributes #4 = { nounwind "target-cpu"="fiji" }
attributes #5 = { nounwind "target-features"="+promote-alloca" "amdgpu-waves-per-eu"="1,3" } attributes #5 = { nounwind "target-features"="+promote-alloca" "amdgpu-waves-per-eu"="1,3" }
attributes #6 = { nounwind "target-features"="-promote-alloca" "amdgpu-waves-per-eu"="1,3" } attributes #6 = { nounwind "target-features"="-promote-alloca" "amdgpu-waves-per-eu"="1,3" }

test/CodeGen/AMDGPU/undefined-physreg-sgpr-spill.mir

Show First 20 Lines • Show All 76 Lines • ▼ Show 20 Lines
... ...
--- ---
# Move spill to after future save instruction # Move spill to after future save instruction
# CHECK-LABEL: {{^}}name: undefined_physreg_sgpr_spill_reorder # CHECK-LABEL: {{^}}name: undefined_physreg_sgpr_spill_reorder
# CHECK: %sgpr0_sgpr1 = COPY %exec, implicit-def %exec # CHECK: %sgpr0_sgpr1 = COPY %exec, implicit-def %exec
# CHECK: %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def dead %scc # CHECK: %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1, killed %vcc, implicit-def dead %scc
# CHECK: SI_SPILL_S64_SAVE killed %sgpr0_sgpr1, %stack.0, implicit %exec, implicit %sgpr8_sgpr9_sgpr10_sgpr11, implicit %sgpr13, implicit-def dead %m0 :: (store 8 into %stack.0, align 4) # CHECK: SI_SPILL_S64_SAVE killed %sgpr0_sgpr1, %stack.0, implicit %exec, implicit %sgpr8_sgpr9_sgpr10_sgpr11, implicit %sgpr13, implicit-def dead %m0 :: (store 8 into %stack.0, align 4, addrspace 5)
# CHECK: %exec = COPY killed %sgpr2_sgpr3 # CHECK: %exec = COPY killed %sgpr2_sgpr3
name: undefined_physreg_sgpr_spill_reorder name: undefined_physreg_sgpr_spill_reorder
alignment: 0 alignment: 0
exposesReturnsTwice: false exposesReturnsTwice: false
legalized: false legalized: false
regBankSelected: false regBankSelected: false
selected: false selected: false
tracksRegLiveness: true tracksRegLiveness: true
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test/CodeGen/AMDGPU/vop-shrink-frame-index.mir

# RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s # RUN: llc -march=amdgcn -verify-machineinstrs -run-pass si-shrink-instructions -o - %s | FileCheck -check-prefix=GCN %s
--- | --- |
define amdgpu_kernel void @fold_fi_vgpr() { define amdgpu_kernel void @fold_fi_vgpr() {
%alloca = alloca [4 x i32] %alloca = alloca [4 x i32], addrspace(5)
ret void ret void
} }
define amdgpu_kernel void @fold_vgpr_fi() { define amdgpu_kernel void @fold_vgpr_fi() {
%alloca = alloca [4 x i32] %alloca = alloca [4 x i32], addrspace(5)
ret void ret void
} }
define amdgpu_kernel void @fold_sgpr_fi() { define amdgpu_kernel void @fold_sgpr_fi() {
%alloca = alloca [4 x i32] %alloca = alloca [4 x i32], addrspace(5)
ret void ret void
} }
define amdgpu_kernel void @fold_fi_sgpr() { define amdgpu_kernel void @fold_fi_sgpr() {
%alloca = alloca [4 x i32] %alloca = alloca [4 x i32], addrspace(5)
ret void ret void
} }
define amdgpu_kernel void @fold_fi_imm() { define amdgpu_kernel void @fold_fi_imm() {
%alloca = alloca [4 x i32] %alloca = alloca [4 x i32], addrspace(5)
ret void ret void
} }
define amdgpu_kernel void @fold_imm_fi() { define amdgpu_kernel void @fold_imm_fi() {
%alloca = alloca [4 x i32] %alloca = alloca [4 x i32], addrspace(5)
ret void ret void
} }
... ...
# GCN-LABEL: name: fold_fi_vgpr{{$}} # GCN-LABEL: name: fold_fi_vgpr{{$}}
# GCN: %1:vgpr_32 = IMPLICIT_DEF # GCN: %1:vgpr_32 = IMPLICIT_DEF
# GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec # GCN: %2:vgpr_32 = V_ADD_I32_e32 %stack.0.alloca, %1, implicit-def %vcc, implicit %exec
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test/CodeGen/AMDGPU/waitcnt-flat.ll

; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=kaveri < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
; If flat_store_dword and flat_load_dword use different registers for the data ; If flat_store_dword and flat_load_dword use different registers for the data
; operand, this test is not broken. It just means it is no longer testing ; operand, this test is not broken. It just means it is no longer testing
; for the original bug. ; for the original bug.
; GCN: {{^}}test: ; GCN: {{^}}test:
; XGCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]] ; XGCN: flat_store_dword v[{{[0-9]+:[0-9]+}}], [[DATA:v[0-9]+]]
; XGCN: s_waitcnt vmcnt(0) lgkmcnt(0) ; XGCN: s_waitcnt vmcnt(0) lgkmcnt(0)
; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}] ; XGCN: flat_load_dword [[DATA]], v[{{[0-9]+:[0-9]+}}]
define amdgpu_kernel void @test(i32 addrspace(4)* %out, i32 %in) { define amdgpu_kernel void @test(i32* %out, i32 %in) {
store volatile i32 0, i32 addrspace(4)* %out store volatile i32 0, i32* %out
%val = load volatile i32, i32 addrspace(4)* %out %val = load volatile i32, i32* %out
ret void ret void
} }
; Make sure lgkmcnt isn't used for global_* instructions ; Make sure lgkmcnt isn't used for global_ addrspace(5)* instructions
; GCN-LABEL: {{^}}test_waitcnt_type_flat_global: ; GCN-LABEL: {{^}}test_waitcnt_type_flat_global:
; GFX9: global_load_dword [[LD:v[0-9]+]] ; GFX9: global_load_dword [[LD:v[0-9]+]]
; GFX9-NEXT: s_waitcnt vmcnt(0){{$}} ; GFX9-NEXT: s_waitcnt vmcnt(0){{$}}
; GFX9-NEXT: ds_write_b32 [[LD]] ; GFX9-NEXT: ds_write_b32 [[LD]]
define amdgpu_kernel void @test_waitcnt_type_flat_global(i32 addrspace(1)* %in) { define amdgpu_kernel void @test_waitcnt_type_flat_global(i32 addrspace(1)* %in) {
%val = load volatile i32, i32 addrspace(1)* %in %val = load volatile i32, i32 addrspace(1)* %in
store volatile i32 %val, i32 addrspace(3)* undef store volatile i32 %val, i32 addrspace(3)* undef
ret void ret void
} }

test/CodeGen/AMDGPU/waitcnt-looptest.ll

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; GCN: s_waitcnt vmcnt(0) lgkmcnt(0) ; GCN: s_waitcnt vmcnt(0) lgkmcnt(0)
; GCN-NEXT: v_cmp_eq_f32_e32 ; GCN-NEXT: v_cmp_eq_f32_e32
@data_generic = addrspace(1) global [100 x float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340000000, float 0x3FD99999A0000000, float 5.000000e-01, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000, float 0x3FECCCCCC0000000, float 1.000000e+00, float 0x3FF19999A0000000, float 0x3FF3333340000000, float 0x3FF4CCCCC0000000, float 0x3FF6666660000000, float 1.500000e+00, float 0x3FF99999A0000000, float 0x3FFB333340000000, float 0x3FFCCCCCC0000000, float 0x3FFE666660000000, float 2.000000e+00, float 0x4000CCCCC0000000, float 0x40019999A0000000, float 0x4002666660000000, float 0x4003333340000000, float 2.500000e+00, float 0x4004CCCCC0000000, float 0x40059999A0000000, float 0x4006666660000000, float 0x4007333340000000, float 3.000000e+00, float 0x4008CCCCC0000000, float 0x40099999A0000000, float 0x400A666660000000, float 0x400B333340000000, float 3.500000e+00, float 0x400CCCCCC0000000, float 0x400D9999A0000000, float 0x400E666660000000, float 0x400F333340000000, float 4.000000e+00, float 0x4010666660000000, float 0x4010CCCCC0000000, float 0x4011333340000000, float 0x40119999A0000000, float 4.500000e+00, float 0x4012666660000000, float 0x4012CCCCC0000000, float 0x4013333340000000, float 0x40139999A0000000, float 5.000000e+00, float 0x4014666660000000, float 0x4014CCCCC0000000, float 0x4015333340000000, float 0x40159999A0000000, float 5.500000e+00, float 0x4016666660000000, float 0x4016CCCCC0000000, float 0x4017333340000000, float 0x40179999A0000000, float 6.000000e+00, float 0x4018666660000000, float 0x4018CCCCC0000000, float 0x4019333340000000, float 0x40199999A0000000, float 6.500000e+00, float 0x401A666660000000, float 0x401ACCCCC0000000, float 0x401B333340000000, float 0x401B9999A0000000, float 7.000000e+00, float 0x401C666660000000, float 0x401CCCCCC0000000, float 0x401D333340000000, float 0x401D9999A0000000, float 7.500000e+00, float 0x401E666660000000, float 0x401ECCCCC0000000, float 0x401F333340000000, float 0x401F9999A0000000, float 8.000000e+00, float 0x4020333340000000, float 0x4020666660000000, float 0x40209999A0000000, float 0x4020CCCCC0000000, float 8.500000e+00, float 0x4021333340000000, float 0x4021666660000000, float 0x40219999A0000000, float 0x4021CCCCC0000000, float 9.000000e+00, float 0x4022333340000000, float 0x4022666660000000, float 0x40229999A0000000, float 0x4022CCCCC0000000, float 9.500000e+00, float 0x4023333340000000, float 0x4023666660000000, float 0x40239999A0000000, float 0x4023CCCCC0000000], align 4 @data_generic = addrspace(1) global [100 x float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340000000, float 0x3FD99999A0000000, float 5.000000e-01, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000, float 0x3FECCCCCC0000000, float 1.000000e+00, float 0x3FF19999A0000000, float 0x3FF3333340000000, float 0x3FF4CCCCC0000000, float 0x3FF6666660000000, float 1.500000e+00, float 0x3FF99999A0000000, float 0x3FFB333340000000, float 0x3FFCCCCCC0000000, float 0x3FFE666660000000, float 2.000000e+00, float 0x4000CCCCC0000000, float 0x40019999A0000000, float 0x4002666660000000, float 0x4003333340000000, float 2.500000e+00, float 0x4004CCCCC0000000, float 0x40059999A0000000, float 0x4006666660000000, float 0x4007333340000000, float 3.000000e+00, float 0x4008CCCCC0000000, float 0x40099999A0000000, float 0x400A666660000000, float 0x400B333340000000, float 3.500000e+00, float 0x400CCCCCC0000000, float 0x400D9999A0000000, float 0x400E666660000000, float 0x400F333340000000, float 4.000000e+00, float 0x4010666660000000, float 0x4010CCCCC0000000, float 0x4011333340000000, float 0x40119999A0000000, float 4.500000e+00, float 0x4012666660000000, float 0x4012CCCCC0000000, float 0x4013333340000000, float 0x40139999A0000000, float 5.000000e+00, float 0x4014666660000000, float 0x4014CCCCC0000000, float 0x4015333340000000, float 0x40159999A0000000, float 5.500000e+00, float 0x4016666660000000, float 0x4016CCCCC0000000, float 0x4017333340000000, float 0x40179999A0000000, float 6.000000e+00, float 0x4018666660000000, float 0x4018CCCCC0000000, float 0x4019333340000000, float 0x40199999A0000000, float 6.500000e+00, float 0x401A666660000000, float 0x401ACCCCC0000000, float 0x401B333340000000, float 0x401B9999A0000000, float 7.000000e+00, float 0x401C666660000000, float 0x401CCCCCC0000000, float 0x401D333340000000, float 0x401D9999A0000000, float 7.500000e+00, float 0x401E666660000000, float 0x401ECCCCC0000000, float 0x401F333340000000, float 0x401F9999A0000000, float 8.000000e+00, float 0x4020333340000000, float 0x4020666660000000, float 0x40209999A0000000, float 0x4020CCCCC0000000, float 8.500000e+00, float 0x4021333340000000, float 0x4021666660000000, float 0x40219999A0000000, float 0x4021CCCCC0000000, float 9.000000e+00, float 0x4022333340000000, float 0x4022666660000000, float 0x40229999A0000000, float 0x4022CCCCC0000000, float 9.500000e+00, float 0x4023333340000000, float 0x4023666660000000, float 0x40239999A0000000, float 0x4023CCCCC0000000], align 4
@data_reference = addrspace(1) global [100 x float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340000000, float 0x3FD99999A0000000, float 5.000000e-01, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000, float 0x3FECCCCCC0000000, float 1.000000e+00, float 0x3FF19999A0000000, float 0x3FF3333340000000, float 0x3FF4CCCCC0000000, float 0x3FF6666660000000, float 1.500000e+00, float 0x3FF99999A0000000, float 0x3FFB333340000000, float 0x3FFCCCCCC0000000, float 0x3FFE666660000000, float 2.000000e+00, float 0x4000CCCCC0000000, float 0x40019999A0000000, float 0x4002666660000000, float 0x4003333340000000, float 2.500000e+00, float 0x4004CCCCC0000000, float 0x40059999A0000000, float 0x4006666660000000, float 0x4007333340000000, float 3.000000e+00, float 0x4008CCCCC0000000, float 0x40099999A0000000, float 0x400A666660000000, float 0x400B333340000000, float 3.500000e+00, float 0x400CCCCCC0000000, float 0x400D9999A0000000, float 0x400E666660000000, float 0x400F333340000000, float 4.000000e+00, float 0x4010666660000000, float 0x4010CCCCC0000000, float 0x4011333340000000, float 0x40119999A0000000, float 4.500000e+00, float 0x4012666660000000, float 0x4012CCCCC0000000, float 0x4013333340000000, float 0x40139999A0000000, float 5.000000e+00, float 0x4014666660000000, float 0x4014CCCCC0000000, float 0x4015333340000000, float 0x40159999A0000000, float 5.500000e+00, float 0x4016666660000000, float 0x4016CCCCC0000000, float 0x4017333340000000, float 0x40179999A0000000, float 6.000000e+00, float 0x4018666660000000, float 0x4018CCCCC0000000, float 0x4019333340000000, float 0x40199999A0000000, float 6.500000e+00, float 0x401A666660000000, float 0x401ACCCCC0000000, float 0x401B333340000000, float 0x401B9999A0000000, float 7.000000e+00, float 0x401C666660000000, float 0x401CCCCCC0000000, float 0x401D333340000000, float 0x401D9999A0000000, float 7.500000e+00, float 0x401E666660000000, float 0x401ECCCCC0000000, float 0x401F333340000000, float 0x401F9999A0000000, float 8.000000e+00, float 0x4020333340000000, float 0x4020666660000000, float 0x40209999A0000000, float 0x4020CCCCC0000000, float 8.500000e+00, float 0x4021333340000000, float 0x4021666660000000, float 0x40219999A0000000, float 0x4021CCCCC0000000, float 9.000000e+00, float 0x4022333340000000, float 0x4022666660000000, float 0x40229999A0000000, float 0x4022CCCCC0000000, float 9.500000e+00, float 0x4023333340000000, float 0x4023666660000000, float 0x40239999A0000000, float 0x4023CCCCC0000000], align 4 @data_reference = addrspace(1) global [100 x float] [float 0.000000e+00, float 0x3FB99999A0000000, float 0x3FC99999A0000000, float 0x3FD3333340000000, float 0x3FD99999A0000000, float 5.000000e-01, float 0x3FE3333340000000, float 0x3FE6666660000000, float 0x3FE99999A0000000, float 0x3FECCCCCC0000000, float 1.000000e+00, float 0x3FF19999A0000000, float 0x3FF3333340000000, float 0x3FF4CCCCC0000000, float 0x3FF6666660000000, float 1.500000e+00, float 0x3FF99999A0000000, float 0x3FFB333340000000, float 0x3FFCCCCCC0000000, float 0x3FFE666660000000, float 2.000000e+00, float 0x4000CCCCC0000000, float 0x40019999A0000000, float 0x4002666660000000, float 0x4003333340000000, float 2.500000e+00, float 0x4004CCCCC0000000, float 0x40059999A0000000, float 0x4006666660000000, float 0x4007333340000000, float 3.000000e+00, float 0x4008CCCCC0000000, float 0x40099999A0000000, float 0x400A666660000000, float 0x400B333340000000, float 3.500000e+00, float 0x400CCCCCC0000000, float 0x400D9999A0000000, float 0x400E666660000000, float 0x400F333340000000, float 4.000000e+00, float 0x4010666660000000, float 0x4010CCCCC0000000, float 0x4011333340000000, float 0x40119999A0000000, float 4.500000e+00, float 0x4012666660000000, float 0x4012CCCCC0000000, float 0x4013333340000000, float 0x40139999A0000000, float 5.000000e+00, float 0x4014666660000000, float 0x4014CCCCC0000000, float 0x4015333340000000, float 0x40159999A0000000, float 5.500000e+00, float 0x4016666660000000, float 0x4016CCCCC0000000, float 0x4017333340000000, float 0x40179999A0000000, float 6.000000e+00, float 0x4018666660000000, float 0x4018CCCCC0000000, float 0x4019333340000000, float 0x40199999A0000000, float 6.500000e+00, float 0x401A666660000000, float 0x401ACCCCC0000000, float 0x401B333340000000, float 0x401B9999A0000000, float 7.000000e+00, float 0x401C666660000000, float 0x401CCCCCC0000000, float 0x401D333340000000, float 0x401D9999A0000000, float 7.500000e+00, float 0x401E666660000000, float 0x401ECCCCC0000000, float 0x401F333340000000, float 0x401F9999A0000000, float 8.000000e+00, float 0x4020333340000000, float 0x4020666660000000, float 0x40209999A0000000, float 0x4020CCCCC0000000, float 8.500000e+00, float 0x4021333340000000, float 0x4021666660000000, float 0x40219999A0000000, float 0x4021CCCCC0000000, float 9.000000e+00, float 0x4022333340000000, float 0x4022666660000000, float 0x40229999A0000000, float 0x4022CCCCC0000000, float 9.500000e+00, float 0x4023333340000000, float 0x4023666660000000, float 0x40239999A0000000, float 0x4023CCCCC0000000], align 4
define amdgpu_kernel void @testKernel(i32 addrspace(1)* nocapture %arg) local_unnamed_addr #0 { define amdgpu_kernel void @testKernel(i32 addrspace(1)* nocapture %arg) local_unnamed_addr #0 {
bb: bb:
store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> addrspace(4)* bitcast (float addrspace(4)* getelementptr ([100 x float], [100 x float] addrspace(4)* addrspacecast ([100 x float] addrspace(1)* @data_generic to [100 x float] addrspace(4)*), i64 0, i64 4) to <2 x float> addrspace(4)*), align 4 store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_generic to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4
store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float> addrspace(4)* bitcast (float addrspace(4)* getelementptr ([100 x float], [100 x float] addrspace(4)* addrspacecast ([100 x float] addrspace(1)* @data_reference to [100 x float] addrspace(4)*), i64 0, i64 4) to <2 x float> addrspace(4)*), align 4 store <2 x float> <float 1.000000e+00, float 1.000000e+00>, <2 x float>* bitcast (float* getelementptr ([100 x float], [100 x float]* addrspacecast ([100 x float] addrspace(1)* @data_reference to [100 x float]*), i64 0, i64 4) to <2 x float>*), align 4
br label %bb18 br label %bb18
bb1: ; preds = %bb18 bb1: ; preds = %bb18
%tmp = tail call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() %tmp = tail call i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr()
%tmp2 = tail call i32 @llvm.amdgcn.workitem.id.x() %tmp2 = tail call i32 @llvm.amdgcn.workitem.id.x()
%tmp3 = tail call i32 @llvm.amdgcn.workgroup.id.x() %tmp3 = tail call i32 @llvm.amdgcn.workgroup.id.x()
%tmp4 = getelementptr inbounds i8, i8 addrspace(2)* %tmp, i64 4 %tmp4 = getelementptr inbounds i8, i8 addrspace(2)* %tmp, i64 4
%tmp5 = bitcast i8 addrspace(2)* %tmp4 to i16 addrspace(2)* %tmp5 = bitcast i8 addrspace(2)* %tmp4 to i16 addrspace(2)*
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test/CodeGen/AMDGPU/waitcnt.mir

# RUN: llc -march=amdgcn -mcpu=fiji -run-pass si-insert-waits %s -o - | FileCheck %s # RUN: llc -march=amdgcn -mcpu=fiji -run-pass si-insert-waits %s -o - | FileCheck %s
--- | --- |
define amdgpu_kernel void @flat_zero_waitcnt(i32 addrspace(1)* %global4, define amdgpu_kernel void @flat_zero_waitcnt(i32 addrspace(1)* %global4,
<4 x i32> addrspace(1)* %global16, <4 x i32> addrspace(1)* %global16,
i32 addrspace(4)* %flat4, i32* %flat4,
<4 x i32> addrspace(4)* %flat16) { <4 x i32>* %flat16) {
ret void ret void
} }
define amdgpu_kernel void @single_fallthrough_successor_no_end_block_wait() { define amdgpu_kernel void @single_fallthrough_successor_no_end_block_wait() {
ret void ret void
} }
define amdgpu_kernel void @single_branch_successor_not_next_block() { define amdgpu_kernel void @single_branch_successor_not_next_block() {
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test/CodeGen/AMDGPU/wqm.ll

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; CHECK: s_wqm_b64 exec, exec ; CHECK: s_wqm_b64 exec, exec
; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen ; CHECK: buffer_load_dword {{v[0-9]+}}, {{v[0-9]+}}, {{s\[[0-9]+:[0-9]+\]}}, {{s[0-9]+}} offen
; CHECK: s_and_b64 exec, exec, [[LIVE]] ; CHECK: s_and_b64 exec, exec, [[LIVE]]
; CHECK: image_sample ; CHECK: image_sample
; CHECK: buffer_store_dwordx4 ; CHECK: buffer_store_dwordx4
define amdgpu_ps void @test_alloca(float %data, i32 %a, i32 %idx) nounwind { define amdgpu_ps void @test_alloca(float %data, i32 %a, i32 %idx) nounwind {
entry: entry:
%array = alloca [32 x i32], align 4 %array = alloca [32 x i32], align 4, addrspace(5)
call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
%s.gep = getelementptr [32 x i32], [32 x i32]* %array, i32 0, i32 0 %s.gep = getelementptr [32 x i32], [32 x i32] addrspace(5)* %array, i32 0, i32 0
store volatile i32 %a, i32* %s.gep, align 4 store volatile i32 %a, i32 addrspace(5)* %s.gep, align 4
call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 1, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.f32(float %data, <4 x i32> undef, i32 1, i32 0, i1 0, i1 0)
%c.gep = getelementptr [32 x i32], [32 x i32]* %array, i32 0, i32 %idx %c.gep = getelementptr [32 x i32], [32 x i32] addrspace(5)* %array, i32 0, i32 %idx
%c = load i32, i32* %c.gep, align 4 %c = load i32, i32 addrspace(5)* %c.gep, align 4
%c.bc = bitcast i32 %c to float %c.bc = bitcast i32 %c to float
%t = call <4 x float> @llvm.amdgcn.image.sample.v4f32.f32.v8i32(float %c.bc, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #0 %t = call <4 x float> @llvm.amdgcn.image.sample.v4f32.f32.v8i32(float %c.bc, <8 x i32> undef, <4 x i32> undef, i32 15, i1 false, i1 false, i1 false, i1 false, i1 false) #0
call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %t, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0) call void @llvm.amdgcn.buffer.store.v4f32(<4 x float> %t, <4 x i32> undef, i32 0, i32 0, i1 0, i1 0)
ret void ret void
} }
; Must return to exact at the end of a non-void returning shader, ; Must return to exact at the end of a non-void returning shader,
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test/DebugInfo/AMDGPU/code-pointer-size.ll

; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s ; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -filetype=obj < %s | llvm-dwarfdump -debug-info - | FileCheck %s
; LLVM IR generated with the following command and OpenCL source: ; LLVM IR generated with the following command and OpenCL source:
; ;
; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> ; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file>
; ;
; kernel void kernel1(global int *A) { ; kernel void kernel1(global int addrspace(5)*A) {
; *A = 11; ; *A = 11;
; } ; }
; ;
; kernel void kernel2(global int *B) { ; kernel void kernel2(global int addrspace(5)*B) {
; *B = 12; ; *B = 12;
; } ; }
; Make sure that code pointer size is 8 bytes: ; Make sure that code pointer size is 8 bytes:
; CHECK: .debug_info contents: ; CHECK: .debug_info contents:
; CHECK: addr_size = 0x08 ; CHECK: addr_size = 0x08
declare void @llvm.dbg.declare(metadata, metadata, metadata) declare void @llvm.dbg.declare(metadata, metadata, metadata)
define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 { define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 {
entry: entry:
%A.addr = alloca i32 addrspace(1)*, align 4 %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !16, metadata !17), !dbg !18 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18
%0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !19 %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19
store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20 store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20
ret void, !dbg !21 ret void, !dbg !21
} }
define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 { define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 {
entry: entry:
%B.addr = alloca i32 addrspace(1)*, align 4 %B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %B, i32 addrspace(1)** %B.addr, align 4 store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %B.addr, metadata !23, metadata !17), !dbg !24 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24
%0 = load i32 addrspace(1)*, i32 addrspace(1)** %B.addr, align 4, !dbg !25 %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25
store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26 store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26
ret void, !dbg !27 ret void, !dbg !27
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!opencl.ocl.version = !{!3, !3} !opencl.ocl.version = !{!3, !3}
!llvm.module.flags = !{!4, !5} !llvm.module.flags = !{!4, !5}
!llvm.ident = !{!6} !llvm.ident = !{!6}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
!1 = !DIFile(filename: "dwarfdump-relocs.cl", directory: "/some/random/directory") !1 = !DIFile(filename: "dwarfdump-relocs.cl", directory: "/some/random/directory")
!2 = !{} !2 = !{}
!3 = !{i32 2, i32 0} !3 = !{i32 2, i32 0}
!4 = !{i32 2, !"Dwarf Version", i32 2} !4 = !{i32 2, !"Dwarf Version", i32 2}
!5 = !{i32 2, !"Debug Info Version", i32 3} !5 = !{i32 2, !"Debug Info Version", i32 3}
!6 = !{!""} !6 = !{!""}
!7 = distinct !DISubprogram(name: "kernel1", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !7 = distinct !DISubprogram(name: "kernel1", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
!8 = !DISubroutineType(types: !9) !8 = !DISubroutineType(types: !9)
!9 = !{null, !10} !9 = !{null, !10}
!10 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !11, size: 64) !10 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !11, size: 64)
!11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!12 = !{i32 1} !12 = !{i32 1}
!13 = !{!"none"} !13 = !{!"none"}
!14 = !{!"int*"} !14 = !{!"int addrspace(5)*"}
!15 = !{!""} !15 = !{!""}
!16 = !DILocalVariable(name: "A", arg: 1, scope: !7, file: !1, line: 1, type: !10) !16 = !DILocalVariable(name: "A", arg: 1, scope: !7, file: !1, line: 1, type: !10)
!17 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef) !17 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)
!18 = !DILocation(line: 1, column: 33, scope: !7) !18 = !DILocation(line: 1, column: 33, scope: !7)
!19 = !DILocation(line: 2, column: 4, scope: !7) !19 = !DILocation(line: 2, column: 4, scope: !7)
!20 = !DILocation(line: 2, column: 6, scope: !7) !20 = !DILocation(line: 2, column: 6, scope: !7)
!21 = !DILocation(line: 3, column: 1, scope: !7) !21 = !DILocation(line: 3, column: 1, scope: !7)
!22 = distinct !DISubprogram(name: "kernel2", scope: !1, file: !1, line: 5, type: !8, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !22 = distinct !DISubprogram(name: "kernel2", scope: !1, file: !1, line: 5, type: !8, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
!23 = !DILocalVariable(name: "B", arg: 1, scope: !22, file: !1, line: 5, type: !10) !23 = !DILocalVariable(name: "B", arg: 1, scope: !22, file: !1, line: 5, type: !10)
!24 = !DILocation(line: 5, column: 33, scope: !22) !24 = !DILocation(line: 5, column: 33, scope: !22)
!25 = !DILocation(line: 6, column: 4, scope: !22) !25 = !DILocation(line: 6, column: 4, scope: !22)
!26 = !DILocation(line: 6, column: 6, scope: !22) !26 = !DILocation(line: 6, column: 6, scope: !22)
!27 = !DILocation(line: 7, column: 1, scope: !22) !27 = !DILocation(line: 7, column: 1, scope: !22)

test/DebugInfo/AMDGPU/dwarfdump-relocs.ll

; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v - 2>&1 | FileCheck %s ; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v - 2>&1 | FileCheck %s
; LLVM IR generated with the following command and OpenCL source: ; LLVM IR generated with the following command and OpenCL source:
; ;
; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> ; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file>
; ;
; kernel void kernel1(global int *A) { ; kernel void kernel1(global int addrspace(5)*A) {
; *A = 11; ; *A = 11;
; } ; }
; ;
; kernel void kernel2(global int *B) { ; kernel void kernel2(global int addrspace(5)*B) {
; *B = 12; ; *B = 12;
; } ; }
; CHECK-NOT: failed to compute relocation ; CHECK-NOT: failed to compute relocation
; CHECK: file_names[ 1] 0 0x00000000 0x00000000 dwarfdump-relocs.cl ; CHECK: file_names[ 1] 0 0x00000000 0x00000000 dwarfdump-relocs.cl
declare void @llvm.dbg.declare(metadata, metadata, metadata) declare void @llvm.dbg.declare(metadata, metadata, metadata)
define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 { define amdgpu_kernel void @kernel1(i32 addrspace(1)* %A) !dbg !7 {
entry: entry:
%A.addr = alloca i32 addrspace(1)*, align 4 %A.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %A, i32 addrspace(1)** %A.addr, align 4 store i32 addrspace(1)* %A, i32 addrspace(1)* addrspace(5)* %A.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %A.addr, metadata !16, metadata !17), !dbg !18 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %A.addr, metadata !16, metadata !17), !dbg !18
%0 = load i32 addrspace(1)*, i32 addrspace(1)** %A.addr, align 4, !dbg !19 %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %A.addr, align 4, !dbg !19
store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20 store i32 11, i32 addrspace(1)* %0, align 4, !dbg !20
ret void, !dbg !21 ret void, !dbg !21
} }
define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 { define amdgpu_kernel void @kernel2(i32 addrspace(1)* %B) !dbg !22 {
entry: entry:
%B.addr = alloca i32 addrspace(1)*, align 4 %B.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 addrspace(1)* %B, i32 addrspace(1)** %B.addr, align 4 store i32 addrspace(1)* %B, i32 addrspace(1)* addrspace(5)* %B.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %B.addr, metadata !23, metadata !17), !dbg !24 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %B.addr, metadata !23, metadata !17), !dbg !24
%0 = load i32 addrspace(1)*, i32 addrspace(1)** %B.addr, align 4, !dbg !25 %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %B.addr, align 4, !dbg !25
store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26 store i32 12, i32 addrspace(1)* %0, align 4, !dbg !26
ret void, !dbg !27 ret void, !dbg !27
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!opencl.ocl.version = !{!3, !3} !opencl.ocl.version = !{!3, !3}
!llvm.module.flags = !{!4, !5} !llvm.module.flags = !{!4, !5}
!llvm.ident = !{!6} !llvm.ident = !{!6}
!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2) !0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, producer: "", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2)
!1 = !DIFile(filename: "dwarfdump-relocs.cl", directory: "/some/random/directory") !1 = !DIFile(filename: "dwarfdump-relocs.cl", directory: "/some/random/directory")
!2 = !{} !2 = !{}
!3 = !{i32 2, i32 0} !3 = !{i32 2, i32 0}
!4 = !{i32 2, !"Dwarf Version", i32 2} !4 = !{i32 2, !"Dwarf Version", i32 2}
!5 = !{i32 2, !"Debug Info Version", i32 3} !5 = !{i32 2, !"Debug Info Version", i32 3}
!6 = !{!""} !6 = !{!""}
!7 = distinct !DISubprogram(name: "kernel1", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !7 = distinct !DISubprogram(name: "kernel1", scope: !1, file: !1, line: 1, type: !8, isLocal: false, isDefinition: true, scopeLine: 1, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
!8 = !DISubroutineType(types: !9) !8 = !DISubroutineType(types: !9)
!9 = !{null, !10} !9 = !{null, !10}
!10 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !11, size: 64) !10 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !11, size: 64)
!11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed) !11 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
!12 = !{i32 1} !12 = !{i32 1}
!13 = !{!"none"} !13 = !{!"none"}
!14 = !{!"int*"} !14 = !{!"int addrspace(5)*"}
!15 = !{!""} !15 = !{!""}
!16 = !DILocalVariable(name: "A", arg: 1, scope: !7, file: !1, line: 1, type: !10) !16 = !DILocalVariable(name: "A", arg: 1, scope: !7, file: !1, line: 1, type: !10)
!17 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef) !17 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)
!18 = !DILocation(line: 1, column: 33, scope: !7) !18 = !DILocation(line: 1, column: 33, scope: !7)
!19 = !DILocation(line: 2, column: 4, scope: !7) !19 = !DILocation(line: 2, column: 4, scope: !7)
!20 = !DILocation(line: 2, column: 6, scope: !7) !20 = !DILocation(line: 2, column: 6, scope: !7)
!21 = !DILocation(line: 3, column: 1, scope: !7) !21 = !DILocation(line: 3, column: 1, scope: !7)
!22 = distinct !DISubprogram(name: "kernel2", scope: !1, file: !1, line: 5, type: !8, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2) !22 = distinct !DISubprogram(name: "kernel2", scope: !1, file: !1, line: 5, type: !8, isLocal: false, isDefinition: true, scopeLine: 5, flags: DIFlagPrototyped, isOptimized: false, unit: !0, variables: !2)
!23 = !DILocalVariable(name: "B", arg: 1, scope: !22, file: !1, line: 5, type: !10) !23 = !DILocalVariable(name: "B", arg: 1, scope: !22, file: !1, line: 5, type: !10)
!24 = !DILocation(line: 5, column: 33, scope: !22) !24 = !DILocation(line: 5, column: 33, scope: !22)
!25 = !DILocation(line: 6, column: 4, scope: !22) !25 = !DILocation(line: 6, column: 4, scope: !22)
!26 = !DILocation(line: 6, column: 6, scope: !22) !26 = !DILocation(line: 6, column: 6, scope: !22)
!27 = !DILocation(line: 7, column: 1, scope: !22) !27 = !DILocation(line: 7, column: 1, scope: !22)

test/DebugInfo/AMDGPU/pointer-address-space.ll

; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s ; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s
; LLVM IR generated with the following command and OpenCL source: ; LLVM IR generated with the following command and OpenCL source:
; ;
; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> ; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file>
; ;
; kernel void kernel1() { ; kernel void kernel1() {
; global int *FuncVar0 = 0; ; global int addrspace(5)*FuncVar0 = 0;
; constant int *FuncVar1 = 0; ; constant int addrspace(5)*FuncVar1 = 0;
; local int *FuncVar2 = 0; ; local int addrspace(5)*FuncVar2 = 0;
; private int *FuncVar3 = 0; ; private int addrspace(5)*FuncVar3 = 0;
; int *FuncVar4 = 0; ; int addrspace(5)*FuncVar4 = 0;
; } ; }
; CHECK: DW_AT_name {{.*}}"FuncVar0" ; CHECK: DW_AT_name {{.*}}"FuncVar0"
; CHECK-NEXT: DW_AT_decl_file ; CHECK-NEXT: DW_AT_decl_file
; CHECK-NEXT: DW_AT_decl_line ; CHECK-NEXT: DW_AT_decl_line
; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[NONE:[a-f0-9]+]]} ; CHECK-NEXT: DW_AT_type [DW_FORM_ref4] (cu + 0x{{[a-f0-9]+}} => {0x[[NONE:[a-f0-9]+]]}
; CHECK: DW_AT_name {{.*}}"FuncVar1" ; CHECK: DW_AT_name {{.*}}"FuncVar1"
Show All 27 Lines
; CHECK: 0x[[PRIVATE]]: DW_TAG_pointer_type ; CHECK: 0x[[PRIVATE]]: DW_TAG_pointer_type
; CHECK-NEXT: DW_AT_type ; CHECK-NEXT: DW_AT_type
; CHECK-NEXT: DW_AT_address_class [DW_FORM_data4] (0x00000001) ; CHECK-NEXT: DW_AT_address_class [DW_FORM_data4] (0x00000001)
declare void @llvm.dbg.declare(metadata, metadata, metadata) declare void @llvm.dbg.declare(metadata, metadata, metadata)
define amdgpu_kernel void @kernel1() !dbg !7 { define amdgpu_kernel void @kernel1() !dbg !7 {
entry: entry:
%FuncVar0 = alloca i32 addrspace(1)*, align 4 %FuncVar0 = alloca i32 addrspace(1)*, align 4, addrspace(5)
%FuncVar1 = alloca i32 addrspace(2)*, align 4 %FuncVar1 = alloca i32 addrspace(2)*, align 4, addrspace(5)
%FuncVar2 = alloca i32 addrspace(3)*, align 4 %FuncVar2 = alloca i32 addrspace(3)*, align 4, addrspace(5)
%FuncVar3 = alloca i32*, align 4 %FuncVar3 = alloca i32 addrspace(5)*, align 4, addrspace(5)
%FuncVar4 = alloca i32 addrspace(4)*, align 4 %FuncVar4 = alloca i32*, align 4, addrspace(5)
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %FuncVar0, metadata !10, metadata !13), !dbg !14 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %FuncVar0, metadata !10, metadata !13), !dbg !14
store i32 addrspace(1)* null, i32 addrspace(1)** %FuncVar0, align 4, !dbg !14 store i32 addrspace(1)* null, i32 addrspace(1)* addrspace(5)* %FuncVar0, align 4, !dbg !14
call void @llvm.dbg.declare(metadata i32 addrspace(2)** %FuncVar1, metadata !15, metadata !13), !dbg !16 call void @llvm.dbg.declare(metadata i32 addrspace(2)* addrspace(5)* %FuncVar1, metadata !15, metadata !13), !dbg !16
store i32 addrspace(2)* null, i32 addrspace(2)** %FuncVar1, align 4, !dbg !16 store i32 addrspace(2)* null, i32 addrspace(2)* addrspace(5)* %FuncVar1, align 4, !dbg !16
call void @llvm.dbg.declare(metadata i32 addrspace(3)** %FuncVar2, metadata !17, metadata !13), !dbg !19 call void @llvm.dbg.declare(metadata i32 addrspace(3)* addrspace(5)* %FuncVar2, metadata !17, metadata !13), !dbg !19
store i32 addrspace(3)* addrspacecast (i32 addrspace(4)* null to i32 addrspace(3)*), i32 addrspace(3)** %FuncVar2, align 4, !dbg !19 store i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*), i32 addrspace(3)* addrspace(5)* %FuncVar2, align 4, !dbg !19
call void @llvm.dbg.declare(metadata i32** %FuncVar3, metadata !20, metadata !13), !dbg !22 call void @llvm.dbg.declare(metadata i32 addrspace(5)* addrspace(5)* %FuncVar3, metadata !20, metadata !13), !dbg !22
store i32* addrspacecast (i32 addrspace(4)* null to i32*), i32** %FuncVar3, align 4, !dbg !22 store i32 addrspace(5)* addrspacecast (i32* null to i32 addrspace(5)*), i32 addrspace(5)* addrspace(5)* %FuncVar3, align 4, !dbg !22
call void @llvm.dbg.declare(metadata i32 addrspace(4)** %FuncVar4, metadata !23, metadata !13), !dbg !24 call void @llvm.dbg.declare(metadata i32* addrspace(5)* %FuncVar4, metadata !23, metadata !13), !dbg !24
store i32 addrspace(4)* null, i32 addrspace(4)** %FuncVar4, align 4, !dbg !24 store i32* null, i32* addrspace(5)* %FuncVar4, align 4, !dbg !24
ret void, !dbg !25 ret void, !dbg !25
} }
!llvm.dbg.cu = !{!0} !llvm.dbg.cu = !{!0}
!opencl.ocl.version = !{!3} !opencl.ocl.version = !{!3}
!llvm.module.flags = !{!4, !5} !llvm.module.flags = !{!4, !5}
!llvm.ident = !{!6} !llvm.ident = !{!6}
Show All 26 Lines

test/DebugInfo/AMDGPU/variable-locations.ll

; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s ; RUN: llc -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs -filetype=obj < %s | llvm-dwarfdump -v -debug-info - | FileCheck %s
; LLVM IR generated with the following command and OpenCL source: ; LLVM IR generated with the following command and OpenCL source:
; ;
; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file> ; $clang -cl-std=CL2.0 -g -O0 -target amdgcn-amd-amdhsa -S -emit-llvm <path-to-file>
; ;
; global int GlobA; ; global int GlobA;
; global int GlobB; ; global int GlobB;
; ;
; kernel void kernel1(unsigned int ArgN, global int *ArgA, global int *ArgB) { ; kernel void kernel1(unsigned int ArgN, global int addrspace(5)*ArgA, global int addrspace(5)*ArgB) {
; ArgA[ArgN] += ArgB[ArgN]; ; ArgA[ArgN] += ArgB[ArgN];
; } ; }
declare void @llvm.dbg.declare(metadata, metadata, metadata) declare void @llvm.dbg.declare(metadata, metadata, metadata)
; CHECK: {{.*}}DW_TAG_variable ; CHECK: {{.*}}DW_TAG_variable
; CHECK-NEXT: DW_AT_name {{.*}}"GlobA" ; CHECK-NEXT: DW_AT_name {{.*}}"GlobA"
; CHECK-NEXT: DW_AT_type ; CHECK-NEXT: DW_AT_type
Show All 21 Lines
; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +8, DW_OP_constu 0x1, DW_OP_swap, DW_OP_xderef) ; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +8, DW_OP_constu 0x1, DW_OP_swap, DW_OP_xderef)
; CHECK-NEXT: DW_AT_name {{.*}}"ArgA" ; CHECK-NEXT: DW_AT_name {{.*}}"ArgA"
i32 addrspace(1)* %ArgA, i32 addrspace(1)* %ArgA,
; CHECK: {{.*}}DW_TAG_formal_parameter ; CHECK: {{.*}}DW_TAG_formal_parameter
; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +16, DW_OP_constu 0x1, DW_OP_swap, DW_OP_xderef) ; CHECK-NEXT: DW_AT_location [DW_FORM_block1] (DW_OP_fbreg +16, DW_OP_constu 0x1, DW_OP_swap, DW_OP_xderef)
; CHECK-NEXT: DW_AT_name {{.*}}"ArgB" ; CHECK-NEXT: DW_AT_name {{.*}}"ArgB"
i32 addrspace(1)* %ArgB) !dbg !13 { i32 addrspace(1)* %ArgB) !dbg !13 {
entry: entry:
%ArgN.addr = alloca i32, align 4 %ArgN.addr = alloca i32, align 4, addrspace(5)
%ArgA.addr = alloca i32 addrspace(1)*, align 4 %ArgA.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
%ArgB.addr = alloca i32 addrspace(1)*, align 4 %ArgB.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
store i32 %ArgN, i32* %ArgN.addr, align 4 store i32 %ArgN, i32 addrspace(5)* %ArgN.addr, align 4
call void @llvm.dbg.declare(metadata i32* %ArgN.addr, metadata !22, metadata !23), !dbg !24 call void @llvm.dbg.declare(metadata i32 addrspace(5)* %ArgN.addr, metadata !22, metadata !23), !dbg !24
store i32 addrspace(1)* %ArgA, i32 addrspace(1)** %ArgA.addr, align 4 store i32 addrspace(1)* %ArgA, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %ArgA.addr, metadata !25, metadata !23), !dbg !26 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgA.addr, metadata !25, metadata !23), !dbg !26
store i32 addrspace(1)* %ArgB, i32 addrspace(1)** %ArgB.addr, align 4 store i32 addrspace(1)* %ArgB, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4
call void @llvm.dbg.declare(metadata i32 addrspace(1)** %ArgB.addr, metadata !27, metadata !23), !dbg !28 call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %ArgB.addr, metadata !27, metadata !23), !dbg !28
%0 = load i32 addrspace(1)*, i32 addrspace(1)** %ArgB.addr, align 4, !dbg !29 %0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgB.addr, align 4, !dbg !29
%1 = load i32, i32* %ArgN.addr, align 4, !dbg !30 %1 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !30
%idxprom = zext i32 %1 to i64, !dbg !29 %idxprom = zext i32 %1 to i64, !dbg !29
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 %idxprom, !dbg !29 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %0, i64 %idxprom, !dbg !29
%2 = load i32, i32 addrspace(1)* %arrayidx, align 4, !dbg !29 %2 = load i32, i32 addrspace(1)* %arrayidx, align 4, !dbg !29
%3 = load i32 addrspace(1)*, i32 addrspace(1)** %ArgA.addr, align 4, !dbg !31 %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %ArgA.addr, align 4, !dbg !31
%4 = load i32, i32* %ArgN.addr, align 4, !dbg !32 %4 = load i32, i32 addrspace(5)* %ArgN.addr, align 4, !dbg !32
%idxprom1 = zext i32 %4 to i64, !dbg !31 %idxprom1 = zext i32 %4 to i64, !dbg !31
%arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %idxprom1, !dbg !31 %arrayidx2 = getelementptr inbounds i32, i32 addrspace(1)* %3, i64 %idxprom1, !dbg !31
%5 = load i32, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33 %5 = load i32, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33
%add = add nsw i32 %5, %2, !dbg !33 %add = add nsw i32 %5, %2, !dbg !33
store i32 %add, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33 store i32 %add, i32 addrspace(1)* %arrayidx2, align 4, !dbg !33
ret void, !dbg !34 ret void, !dbg !34
} }
Show All 17 Lines
!12 = !{!"clang version 5.0.0"} !12 = !{!"clang version 5.0.0"}
!13 = distinct !DISubprogram(name: "kernel1", scope: !3, file: !3, line: 4, type: !14, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !2, variables: !4) !13 = distinct !DISubprogram(name: "kernel1", scope: !3, file: !3, line: 4, type: !14, isLocal: false, isDefinition: true, scopeLine: 4, flags: DIFlagPrototyped, isOptimized: false, unit: !2, variables: !4)
!14 = !DISubroutineType(types: !15) !14 = !DISubroutineType(types: !15)
!15 = !{null, !16, !17, !17} !15 = !{null, !16, !17, !17}
!16 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) !16 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned)
!17 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64) !17 = !DIDerivedType(tag: DW_TAG_pointer_type, baseType: !8, size: 64)
!18 = !{i32 0, i32 1, i32 1} !18 = !{i32 0, i32 1, i32 1}
!19 = !{!"none", !"none", !"none"} !19 = !{!"none", !"none", !"none"}
!20 = !{!"uint", !"int*", !"int*"} !20 = !{!"uint", !"int addrspace(5)*", !"int addrspace(5)*"}
!21 = !{!"", !"", !""} !21 = !{!"", !"", !""}
!22 = !DILocalVariable(name: "ArgN", arg: 1, scope: !13, file: !3, line: 4, type: !16) !22 = !DILocalVariable(name: "ArgN", arg: 1, scope: !13, file: !3, line: 4, type: !16)
!23 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef) !23 = !DIExpression(DW_OP_constu, 1, DW_OP_swap, DW_OP_xderef)
!24 = !DILocation(line: 4, column: 34, scope: !13) !24 = !DILocation(line: 4, column: 34, scope: !13)
!25 = !DILocalVariable(name: "ArgA", arg: 2, scope: !13, file: !3, line: 4, type: !17) !25 = !DILocalVariable(name: "ArgA", arg: 2, scope: !13, file: !3, line: 4, type: !17)
!26 = !DILocation(line: 4, column: 52, scope: !13) !26 = !DILocation(line: 4, column: 52, scope: !13)
!27 = !DILocalVariable(name: "ArgB", arg: 3, scope: !13, file: !3, line: 4, type: !17) !27 = !DILocalVariable(name: "ArgB", arg: 3, scope: !13, file: !3, line: 4, type: !17)
!28 = !DILocation(line: 4, column: 70, scope: !13) !28 = !DILocation(line: 4, column: 70, scope: !13)
!29 = !DILocation(line: 5, column: 17, scope: !13) !29 = !DILocation(line: 5, column: 17, scope: !13)
!30 = !DILocation(line: 5, column: 22, scope: !13) !30 = !DILocation(line: 5, column: 22, scope: !13)
!31 = !DILocation(line: 5, column: 3, scope: !13) !31 = !DILocation(line: 5, column: 3, scope: !13)
!32 = !DILocation(line: 5, column: 8, scope: !13) !32 = !DILocation(line: 5, column: 8, scope: !13)
!33 = !DILocation(line: 5, column: 14, scope: !13) !33 = !DILocation(line: 5, column: 14, scope: !13)
!34 = !DILocation(line: 6, column: 1, scope: !13) !34 = !DILocation(line: 6, column: 1, scope: !13)

test/Transforms/CodeGenPrepare/AMDGPU/sink-addrspacecast.ll

; RUN: opt -S -codegenprepare -mtriple=amdgcn--amdhsa < %s | FileCheck %s ; RUN: opt -S -codegenprepare -mtriple=amdgcn--amdhsa < %s | FileCheck %s
; CHECK-LABEL: @no_sink_local_to_flat( ; CHECK-LABEL: @no_sink_local_to_flat(
; CHECK: addrspacecast ; CHECK: addrspacecast
; CHECK: br ; CHECK: br
; CHECK-NOT: addrspacecast ; CHECK-NOT: addrspacecast
define i64 @no_sink_local_to_flat(i1 %pred, i64 addrspace(3)* %ptr) { define i64 @no_sink_local_to_flat(i1 %pred, i64 addrspace(3)* %ptr) {
%ptr_cast = addrspacecast i64 addrspace(3)* %ptr to i64 addrspace(4)* %ptr_cast = addrspacecast i64 addrspace(3)* %ptr to i64*
br i1 %pred, label %l1, label %l2 br i1 %pred, label %l1, label %l2
l1: l1:
%v1 = load i64, i64 addrspace(3)* %ptr %v1 = load i64, i64 addrspace(3)* %ptr
ret i64 %v1 ret i64 %v1
l2: l2:
%v2 = load i64, i64 addrspace(4)* %ptr_cast %v2 = load i64, i64* %ptr_cast
ret i64 %v2 ret i64 %v2
} }
; CHECK-LABEL: @no_sink_private_to_flat( ; CHECK-LABEL: @no_sink_private_to_flat(
; CHECK: addrspacecast ; CHECK: addrspacecast
; CHECK: br ; CHECK: br
; CHECK-NOT: addrspacecast ; CHECK-NOT: addrspacecast
define i64 @no_sink_private_to_flat(i1 %pred, i64* %ptr) { define i64 @no_sink_private_to_flat(i1 %pred, i64 addrspace(5)* %ptr) {
%ptr_cast = addrspacecast i64* %ptr to i64 addrspace(4)* %ptr_cast = addrspacecast i64 addrspace(5)* %ptr to i64*
br i1 %pred, label %l1, label %l2 br i1 %pred, label %l1, label %l2
l1: l1:
%v1 = load i64, i64* %ptr %v1 = load i64, i64 addrspace(5)* %ptr
ret i64 %v1 ret i64 %v1
l2: l2:
%v2 = load i64, i64 addrspace(4)* %ptr_cast %v2 = load i64, i64* %ptr_cast
ret i64 %v2 ret i64 %v2
} }
; CHECK-LABEL: @sink_global_to_flat( ; CHECK-LABEL: @sink_global_to_flat(
; CHECK-NOT: addrspacecast ; CHECK-NOT: addrspacecast
; CHECK: br ; CHECK: br
; CHECK: addrspacecast ; CHECK: addrspacecast
define i64 @sink_global_to_flat(i1 %pred, i64 addrspace(1)* %ptr) { define i64 @sink_global_to_flat(i1 %pred, i64 addrspace(1)* %ptr) {
%ptr_cast = addrspacecast i64 addrspace(1)* %ptr to i64 addrspace(4)* %ptr_cast = addrspacecast i64 addrspace(1)* %ptr to i64*
br i1 %pred, label %l1, label %l2 br i1 %pred, label %l1, label %l2
l1: l1:
%v1 = load i64, i64 addrspace(1)* %ptr %v1 = load i64, i64 addrspace(1)* %ptr
ret i64 %v1 ret i64 %v1
l2: l2:
%v2 = load i64, i64 addrspace(4)* %ptr_cast %v2 = load i64, i64* %ptr_cast
ret i64 %v2 ret i64 %v2
} }
; CHECK-LABEL: @sink_flat_to_global( ; CHECK-LABEL: @sink_flat_to_global(
; CHECK-NOT: addrspacecast ; CHECK-NOT: addrspacecast
; CHECK: br ; CHECK: br
; CHECK: addrspacecast ; CHECK: addrspacecast
define i64 @sink_flat_to_global(i1 %pred, i64 addrspace(4)* %ptr) { define i64 @sink_flat_to_global(i1 %pred, i64* %ptr) {
%ptr_cast = addrspacecast i64 addrspace(4)* %ptr to i64 addrspace(1)* %ptr_cast = addrspacecast i64* %ptr to i64 addrspace(1)*
br i1 %pred, label %l1, label %l2 br i1 %pred, label %l1, label %l2
l1: l1:
%v1 = load i64, i64 addrspace(4)* %ptr %v1 = load i64, i64* %ptr
ret i64 %v1 ret i64 %v1
l2: l2:
%v2 = load i64, i64 addrspace(1)* %ptr_cast %v2 = load i64, i64 addrspace(1)* %ptr_cast
ret i64 %v2 ret i64 %v2
} }
; CHECK-LABEL: @sink_flat_to_constant( ; CHECK-LABEL: @sink_flat_to_constant(
; CHECK-NOT: addrspacecast ; CHECK-NOT: addrspacecast
; CHECK: br ; CHECK: br
; CHECK: addrspacecast ; CHECK: addrspacecast
define i64 @sink_flat_to_constant(i1 %pred, i64 addrspace(4)* %ptr) { define i64 @sink_flat_to_constant(i1 %pred, i64* %ptr) {
%ptr_cast = addrspacecast i64 addrspace(4)* %ptr to i64 addrspace(2)* %ptr_cast = addrspacecast i64* %ptr to i64 addrspace(2)*
br i1 %pred, label %l1, label %l2 br i1 %pred, label %l1, label %l2
l1: l1:
%v1 = load i64, i64 addrspace(4)* %ptr %v1 = load i64, i64* %ptr
ret i64 %v1 ret i64 %v1
l2: l2:
%v2 = load i64, i64 addrspace(2)* %ptr_cast %v2 = load i64, i64 addrspace(2)* %ptr_cast
ret i64 %v2 ret i64 %v2
} }
; CHECK-LABEL: @sink_flat_to_local( ; CHECK-LABEL: @sink_flat_to_local(
; CHECK-NOT: addrspacecast ; CHECK-NOT: addrspacecast
; CHECK: br ; CHECK: br
; CHECK: addrspacecast ; CHECK: addrspacecast
define i64 @sink_flat_to_local(i1 %pred, i64 addrspace(4)* %ptr) { define i64 @sink_flat_to_local(i1 %pred, i64* %ptr) {
%ptr_cast = addrspacecast i64 addrspace(4)* %ptr to i64 addrspace(3)* %ptr_cast = addrspacecast i64* %ptr to i64 addrspace(3)*
br i1 %pred, label %l1, label %l2 br i1 %pred, label %l1, label %l2
l1: l1:
%v1 = load i64, i64 addrspace(4)* %ptr %v1 = load i64, i64* %ptr
ret i64 %v1 ret i64 %v1
l2: l2:
%v2 = load i64, i64 addrspace(3)* %ptr_cast %v2 = load i64, i64 addrspace(3)* %ptr_cast
ret i64 %v2 ret i64 %v2
} }
; CHECK-LABEL: @sink_flat_to_private( ; CHECK-LABEL: @sink_flat_to_private(
; CHECK-NOT: addrspacecast ; CHECK-NOT: addrspacecast
; CHECK: br ; CHECK: br
; CHECK: addrspacecast ; CHECK: addrspacecast
define i64 @sink_flat_to_private(i1 %pred, i64 addrspace(4)* %ptr) { define i64 @sink_flat_to_private(i1 %pred, i64* %ptr) {
%ptr_cast = addrspacecast i64 addrspace(4)* %ptr to i64* %ptr_cast = addrspacecast i64* %ptr to i64 addrspace(5)*
br i1 %pred, label %l1, label %l2 br i1 %pred, label %l1, label %l2
l1: l1:
%v1 = load i64, i64 addrspace(4)* %ptr %v1 = load i64, i64* %ptr
ret i64 %v1 ret i64 %v1
l2: l2:
%v2 = load i64, i64* %ptr_cast %v2 = load i64, i64 addrspace(5)* %ptr_cast
ret i64 %v2 ret i64 %v2
} }

test/Transforms/InferAddressSpaces/AMDGPU/basic.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; Trivial optimization of generic addressing ; Trivial optimization of generic addressing
; CHECK-LABEL: @load_global_from_flat( ; CHECK-LABEL: @load_global_from_flat(
; CHECK-NEXT: %tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(1)* ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(1)*
; CHECK-NEXT: %tmp1 = load float, float addrspace(1)* %tmp0 ; CHECK-NEXT: %tmp1 = load float, float addrspace(1)* %tmp0
; CHECK-NEXT: ret float %tmp1 ; CHECK-NEXT: ret float %tmp1
define float @load_global_from_flat(float addrspace(4)* %generic_scalar) #0 { define float @load_global_from_flat(float* %generic_scalar) #0 {
%tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(1)* %tmp0 = addrspacecast float* %generic_scalar to float addrspace(1)*
%tmp1 = load float, float addrspace(1)* %tmp0 %tmp1 = load float, float addrspace(1)* %tmp0
ret float %tmp1 ret float %tmp1
} }
; CHECK-LABEL: @load_constant_from_flat( ; CHECK-LABEL: @load_constant_from_flat(
; CHECK-NEXT: %tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(2)* ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(2)*
; CHECK-NEXT: %tmp1 = load float, float addrspace(2)* %tmp0 ; CHECK-NEXT: %tmp1 = load float, float addrspace(2)* %tmp0
; CHECK-NEXT: ret float %tmp1 ; CHECK-NEXT: ret float %tmp1
define float @load_constant_from_flat(float addrspace(4)* %generic_scalar) #0 { define float @load_constant_from_flat(float* %generic_scalar) #0 {
%tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(2)* %tmp0 = addrspacecast float* %generic_scalar to float addrspace(2)*
%tmp1 = load float, float addrspace(2)* %tmp0 %tmp1 = load float, float addrspace(2)* %tmp0
ret float %tmp1 ret float %tmp1
} }
; CHECK-LABEL: @load_group_from_flat( ; CHECK-LABEL: @load_group_from_flat(
; CHECK-NEXT: %tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(3)* ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(3)*
; CHECK-NEXT: %tmp1 = load float, float addrspace(3)* %tmp0 ; CHECK-NEXT: %tmp1 = load float, float addrspace(3)* %tmp0
; CHECK-NEXT: ret float %tmp1 ; CHECK-NEXT: ret float %tmp1
define float @load_group_from_flat(float addrspace(4)* %generic_scalar) #0 { define float @load_group_from_flat(float* %generic_scalar) #0 {
%tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(3)* %tmp0 = addrspacecast float* %generic_scalar to float addrspace(3)*
%tmp1 = load float, float addrspace(3)* %tmp0 %tmp1 = load float, float addrspace(3)* %tmp0
ret float %tmp1 ret float %tmp1
} }
; CHECK-LABEL: @load_private_from_flat( ; CHECK-LABEL: @load_private_from_flat(
; CHECK-NEXT: %tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float* ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(5)*
; CHECK-NEXT: %tmp1 = load float, float* %tmp0 ; CHECK-NEXT: %tmp1 = load float, float addrspace(5)* %tmp0
; CHECK-NEXT: ret float %tmp1 ; CHECK-NEXT: ret float %tmp1
define float @load_private_from_flat(float addrspace(4)* %generic_scalar) #0 { define float @load_private_from_flat(float* %generic_scalar) #0 {
%tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float* %tmp0 = addrspacecast float* %generic_scalar to float addrspace(5)*
%tmp1 = load float, float* %tmp0 %tmp1 = load float, float addrspace(5)* %tmp0
ret float %tmp1 ret float %tmp1
} }
; CHECK-LABEL: @store_global_from_flat( ; CHECK-LABEL: @store_global_from_flat(
; CHECK-NEXT: %tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(1)* ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(1)*
; CHECK-NEXT: store float 0.000000e+00, float addrspace(1)* %tmp0 ; CHECK-NEXT: store float 0.000000e+00, float addrspace(1)* %tmp0
define amdgpu_kernel void @store_global_from_flat(float addrspace(4)* %generic_scalar) #0 { define amdgpu_kernel void @store_global_from_flat(float* %generic_scalar) #0 {
%tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(1)* %tmp0 = addrspacecast float* %generic_scalar to float addrspace(1)*
store float 0.0, float addrspace(1)* %tmp0 store float 0.0, float addrspace(1)* %tmp0
ret void ret void
} }
; CHECK-LABEL: @store_group_from_flat( ; CHECK-LABEL: @store_group_from_flat(
; CHECK-NEXT: %tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(3)* ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(3)*
; CHECK-NEXT: store float 0.000000e+00, float addrspace(3)* %tmp0 ; CHECK-NEXT: store float 0.000000e+00, float addrspace(3)* %tmp0
define amdgpu_kernel void @store_group_from_flat(float addrspace(4)* %generic_scalar) #0 { define amdgpu_kernel void @store_group_from_flat(float* %generic_scalar) #0 {
%tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float addrspace(3)* %tmp0 = addrspacecast float* %generic_scalar to float addrspace(3)*
store float 0.0, float addrspace(3)* %tmp0 store float 0.0, float addrspace(3)* %tmp0
ret void ret void
} }
; CHECK-LABEL: @store_private_from_flat( ; CHECK-LABEL: @store_private_from_flat(
; CHECK-NEXT: %tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float* ; CHECK-NEXT: %tmp0 = addrspacecast float* %generic_scalar to float addrspace(5)*
; CHECK-NEXT: store float 0.000000e+00, float* %tmp0 ; CHECK-NEXT: store float 0.000000e+00, float addrspace(5)* %tmp0
define amdgpu_kernel void @store_private_from_flat(float addrspace(4)* %generic_scalar) #0 { define amdgpu_kernel void @store_private_from_flat(float* %generic_scalar) #0 {
%tmp0 = addrspacecast float addrspace(4)* %generic_scalar to float* %tmp0 = addrspacecast float* %generic_scalar to float addrspace(5)*
store float 0.0, float* %tmp0 store float 0.0, float addrspace(5)* %tmp0
ret void ret void
} }
; optimized to global load/store. ; optimized to global load/store.
; CHECK-LABEL: @load_store_global( ; CHECK-LABEL: @load_store_global(
; CHECK-NEXT: %val = load i32, i32 addrspace(1)* %input, align 4 ; CHECK-NEXT: %val = load i32, i32 addrspace(1)* %input, align 4
; CHECK-NEXT: store i32 %val, i32 addrspace(1)* %output, align 4 ; CHECK-NEXT: store i32 %val, i32 addrspace(1)* %output, align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define amdgpu_kernel void @load_store_global(i32 addrspace(1)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 { define amdgpu_kernel void @load_store_global(i32 addrspace(1)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 {
%tmp0 = addrspacecast i32 addrspace(1)* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(1)* %input to i32*
%tmp1 = addrspacecast i32 addrspace(1)* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(1)* %output to i32*
%val = load i32, i32 addrspace(4)* %tmp0, align 4 %val = load i32, i32* %tmp0, align 4
store i32 %val, i32 addrspace(4)* %tmp1, align 4 store i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; Optimized to group load/store. ; Optimized to group load/store.
; CHECK-LABEL: @load_store_group( ; CHECK-LABEL: @load_store_group(
; CHECK-NEXT: %val = load i32, i32 addrspace(3)* %input, align 4 ; CHECK-NEXT: %val = load i32, i32 addrspace(3)* %input, align 4
; CHECK-NEXT: store i32 %val, i32 addrspace(3)* %output, align 4 ; CHECK-NEXT: store i32 %val, i32 addrspace(3)* %output, align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define amdgpu_kernel void @load_store_group(i32 addrspace(3)* nocapture %input, i32 addrspace(3)* nocapture %output) #0 { define amdgpu_kernel void @load_store_group(i32 addrspace(3)* nocapture %input, i32 addrspace(3)* nocapture %output) #0 {
%tmp0 = addrspacecast i32 addrspace(3)* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(3)* %input to i32*
%tmp1 = addrspacecast i32 addrspace(3)* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(3)* %output to i32*
%val = load i32, i32 addrspace(4)* %tmp0, align 4 %val = load i32, i32* %tmp0, align 4
store i32 %val, i32 addrspace(4)* %tmp1, align 4 store i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; Optimized to private load/store. ; Optimized to private load/store.
; CHECK-LABEL: @load_store_private( ; CHECK-LABEL: @load_store_private(
; CHECK-NEXT: %val = load i32, i32* %input, align 4 ; CHECK-NEXT: %val = load i32, i32 addrspace(5)* %input, align 4
; CHECK-NEXT: store i32 %val, i32* %output, align 4 ; CHECK-NEXT: store i32 %val, i32 addrspace(5)* %output, align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define amdgpu_kernel void @load_store_private(i32* nocapture %input, i32* nocapture %output) #0 { define amdgpu_kernel void @load_store_private(i32 addrspace(5)* nocapture %input, i32 addrspace(5)* nocapture %output) #0 {
%tmp0 = addrspacecast i32* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(5)* %input to i32*
%tmp1 = addrspacecast i32* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(5)* %output to i32*
%val = load i32, i32 addrspace(4)* %tmp0, align 4 %val = load i32, i32* %tmp0, align 4
store i32 %val, i32 addrspace(4)* %tmp1, align 4 store i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; No optimization. flat load/store. ; No optimization. flat load/store.
; CHECK-LABEL: @load_store_flat( ; CHECK-LABEL: @load_store_flat(
; CHECK-NEXT: %val = load i32, i32 addrspace(4)* %input, align 4 ; CHECK-NEXT: %val = load i32, i32* %input, align 4
; CHECK-NEXT: store i32 %val, i32 addrspace(4)* %output, align 4 ; CHECK-NEXT: store i32 %val, i32* %output, align 4
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define amdgpu_kernel void @load_store_flat(i32 addrspace(4)* nocapture %input, i32 addrspace(4)* nocapture %output) #0 { define amdgpu_kernel void @load_store_flat(i32* nocapture %input, i32* nocapture %output) #0 {
%val = load i32, i32 addrspace(4)* %input, align 4 %val = load i32, i32* %input, align 4
store i32 %val, i32 addrspace(4)* %output, align 4 store i32 %val, i32* %output, align 4
ret void ret void
} }
; CHECK-LABEL: @store_addrspacecast_ptr_value( ; CHECK-LABEL: @store_addrspacecast_ptr_value(
; CHECK: %cast = addrspacecast i32 addrspace(1)* %input to i32 addrspace(4)* ; CHECK: %cast = addrspacecast i32 addrspace(1)* %input to i32*
; CHECK-NEXT: store i32 addrspace(4)* %cast, i32 addrspace(4)* addrspace(1)* %output, align 4 ; CHECK-NEXT: store i32* %cast, i32* addrspace(1)* %output, align 4
define amdgpu_kernel void @store_addrspacecast_ptr_value(i32 addrspace(1)* nocapture %input, i32 addrspace(4)* addrspace(1)* nocapture %output) #0 { define amdgpu_kernel void @store_addrspacecast_ptr_value(i32 addrspace(1)* nocapture %input, i32* addrspace(1)* nocapture %output) #0 {
%cast = addrspacecast i32 addrspace(1)* %input to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %input to i32*
store i32 addrspace(4)* %cast, i32 addrspace(4)* addrspace(1)* %output, align 4 store i32* %cast, i32* addrspace(1)* %output, align 4
ret void ret void
} }
; CHECK-LABEL: @atomicrmw_add_global_to_flat( ; CHECK-LABEL: @atomicrmw_add_global_to_flat(
; CHECK-NEXT: %ret = atomicrmw add i32 addrspace(1)* %global.ptr, i32 %y seq_cst ; CHECK-NEXT: %ret = atomicrmw add i32 addrspace(1)* %global.ptr, i32 %y seq_cst
define i32 @atomicrmw_add_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %y) #0 { define i32 @atomicrmw_add_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %y) #0 {
%cast = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %global.ptr to i32*
%ret = atomicrmw add i32 addrspace(4)* %cast, i32 %y seq_cst %ret = atomicrmw add i32* %cast, i32 %y seq_cst
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @atomicrmw_add_group_to_flat( ; CHECK-LABEL: @atomicrmw_add_group_to_flat(
; CHECK-NEXT: %ret = atomicrmw add i32 addrspace(3)* %group.ptr, i32 %y seq_cst ; CHECK-NEXT: %ret = atomicrmw add i32 addrspace(3)* %group.ptr, i32 %y seq_cst
define i32 @atomicrmw_add_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %y) #0 { define i32 @atomicrmw_add_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %y) #0 {
%cast = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* %group.ptr to i32*
%ret = atomicrmw add i32 addrspace(4)* %cast, i32 %y seq_cst %ret = atomicrmw add i32* %cast, i32 %y seq_cst
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @cmpxchg_global_to_flat( ; CHECK-LABEL: @cmpxchg_global_to_flat(
; CHECK: %ret = cmpxchg i32 addrspace(1)* %global.ptr, i32 %cmp, i32 %val seq_cst monotonic ; CHECK: %ret = cmpxchg i32 addrspace(1)* %global.ptr, i32 %cmp, i32 %val seq_cst monotonic
define { i32, i1 } @cmpxchg_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %cmp, i32 %val) #0 { define { i32, i1 } @cmpxchg_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %cmp, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %global.ptr to i32*
%ret = cmpxchg i32 addrspace(4)* %cast, i32 %cmp, i32 %val seq_cst monotonic %ret = cmpxchg i32* %cast, i32 %cmp, i32 %val seq_cst monotonic
ret { i32, i1 } %ret ret { i32, i1 } %ret
} }
; CHECK-LABEL: @cmpxchg_group_to_flat( ; CHECK-LABEL: @cmpxchg_group_to_flat(
; CHECK: %ret = cmpxchg i32 addrspace(3)* %group.ptr, i32 %cmp, i32 %val seq_cst monotonic ; CHECK: %ret = cmpxchg i32 addrspace(3)* %group.ptr, i32 %cmp, i32 %val seq_cst monotonic
define { i32, i1 } @cmpxchg_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %cmp, i32 %val) #0 { define { i32, i1 } @cmpxchg_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %cmp, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* %group.ptr to i32*
%ret = cmpxchg i32 addrspace(4)* %cast, i32 %cmp, i32 %val seq_cst monotonic %ret = cmpxchg i32* %cast, i32 %cmp, i32 %val seq_cst monotonic
ret { i32, i1 } %ret ret { i32, i1 } %ret
} }
; Not pointer operand ; Not pointer operand
; CHECK-LABEL: @cmpxchg_group_to_flat_wrong_operand( ; CHECK-LABEL: @cmpxchg_group_to_flat_wrong_operand(
; CHECK: %cast.cmp = addrspacecast i32 addrspace(3)* %cmp.ptr to i32 addrspace(4)* ; CHECK: %cast.cmp = addrspacecast i32 addrspace(3)* %cmp.ptr to i32*
; CHECK: %ret = cmpxchg i32 addrspace(4)* addrspace(3)* %cas.ptr, i32 addrspace(4)* %cast.cmp, i32 addrspace(4)* %val seq_cst monotonic ; CHECK: %ret = cmpxchg i32* addrspace(3)* %cas.ptr, i32* %cast.cmp, i32* %val seq_cst monotonic
define { i32 addrspace(4)*, i1 } @cmpxchg_group_to_flat_wrong_operand(i32 addrspace(4)* addrspace(3)* %cas.ptr, i32 addrspace(3)* %cmp.ptr, i32 addrspace(4)* %val) #0 { define { i32*, i1 } @cmpxchg_group_to_flat_wrong_operand(i32* addrspace(3)* %cas.ptr, i32 addrspace(3)* %cmp.ptr, i32* %val) #0 {
%cast.cmp = addrspacecast i32 addrspace(3)* %cmp.ptr to i32 addrspace(4)* %cast.cmp = addrspacecast i32 addrspace(3)* %cmp.ptr to i32*
%ret = cmpxchg i32 addrspace(4)* addrspace(3)* %cas.ptr, i32 addrspace(4)* %cast.cmp, i32 addrspace(4)* %val seq_cst monotonic %ret = cmpxchg i32* addrspace(3)* %cas.ptr, i32* %cast.cmp, i32* %val seq_cst monotonic
ret { i32 addrspace(4)*, i1 } %ret ret { i32*, i1 } %ret
} }
; Null pointer in local addr space ; Null pointer in local addr space
; CHECK-LABEL: @local_nullptr ; CHECK-LABEL: @local_nullptr
; CHECK: icmp ne i8 addrspace(3)* %a, addrspacecast (i8* null to i8 addrspace(3)*) ; CHECK: icmp ne i8 addrspace(3)* %a, addrspacecast (i8 addrspace(5)* null to i8 addrspace(3)*)
; CHECK-NOT: i8 addrspace(3)* null ; CHECK-NOT: i8 addrspace(3)* null
define void @local_nullptr(i32 addrspace(1)* nocapture %results, i8 addrspace(3)* %a) { define void @local_nullptr(i32 addrspace(1)* nocapture %results, i8 addrspace(3)* %a) {
entry: entry:
%tobool = icmp ne i8 addrspace(3)* %a, addrspacecast (i8* null to i8 addrspace(3)*) %tobool = icmp ne i8 addrspace(3)* %a, addrspacecast (i8 addrspace(5)* null to i8 addrspace(3)*)
%conv = zext i1 %tobool to i32 %conv = zext i1 %tobool to i32
store i32 %conv, i32 addrspace(1)* %results, align 4 store i32 %conv, i32 addrspace(1)* %results, align 4
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/Transforms/InferAddressSpaces/AMDGPU/icmp.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; CHECK-LABEL: @icmp_flat_cmp_self( ; CHECK-LABEL: @icmp_flat_cmp_self(
; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, %group.ptr.0 ; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, %group.ptr.0
define i1 @icmp_flat_cmp_self(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_flat_cmp_self(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, %cast0 %cmp = icmp eq i32* %cast0, %cast0
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_flat_flat_from_group( ; CHECK-LABEL: @icmp_flat_flat_from_group(
; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, %group.ptr.1 ; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, %group.ptr.1
define i1 @icmp_flat_flat_from_group(i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 { define i1 @icmp_flat_flat_from_group(i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, %cast1 %cmp = icmp eq i32* %cast0, %cast1
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_mismatch_flat_from_group_private( ; CHECK-LABEL: @icmp_mismatch_flat_from_group_private(
; CHECK: %1 = addrspacecast i32* %private.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(5)* %private.ptr.0 to i32*
; CHECK: %2 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* ; CHECK: %2 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
; CHECK: %cmp = icmp eq i32 addrspace(4)* %1, %2 ; CHECK: %cmp = icmp eq i32* %1, %2
define i1 @icmp_mismatch_flat_from_group_private(i32* %private.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 { define i1 @icmp_mismatch_flat_from_group_private(i32 addrspace(5)* %private.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 {
%cast0 = addrspacecast i32* %private.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(5)* %private.ptr.0 to i32*
%cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, %cast1 %cmp = icmp eq i32* %cast0, %cast1
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_flat_group_flat( ; CHECK-LABEL: @icmp_flat_group_flat(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %cmp = icmp eq i32 addrspace(4)* %1, %flat.ptr.1 ; CHECK: %cmp = icmp eq i32* %1, %flat.ptr.1
define i1 @icmp_flat_group_flat(i32 addrspace(3)* %group.ptr.0, i32 addrspace(4)* %flat.ptr.1) #0 { define i1 @icmp_flat_group_flat(i32 addrspace(3)* %group.ptr.0, i32* %flat.ptr.1) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, %flat.ptr.1 %cmp = icmp eq i32* %cast0, %flat.ptr.1
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_flat_flat_group( ; CHECK-LABEL: @icmp_flat_flat_group(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
; CHECK: %cmp = icmp eq i32 addrspace(4)* %flat.ptr.0, %1 ; CHECK: %cmp = icmp eq i32* %flat.ptr.0, %1
define i1 @icmp_flat_flat_group(i32 addrspace(4)* %flat.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 { define i1 @icmp_flat_flat_group(i32* %flat.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 {
%cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
%cmp = icmp eq i32 addrspace(4)* %flat.ptr.0, %cast1 %cmp = icmp eq i32* %flat.ptr.0, %cast1
ret i1 %cmp ret i1 %cmp
} }
; Keeping as cmp addrspace(3)* is better ; Keeping as cmp addrspace(3)* is better
; CHECK-LABEL: @icmp_flat_to_group_cmp( ; CHECK-LABEL: @icmp_flat_to_group_cmp(
; CHECK: %cast0 = addrspacecast i32 addrspace(4)* %flat.ptr.0 to i32 addrspace(3)* ; CHECK: %cast0 = addrspacecast i32* %flat.ptr.0 to i32 addrspace(3)*
; CHECK: %cast1 = addrspacecast i32 addrspace(4)* %flat.ptr.1 to i32 addrspace(3)* ; CHECK: %cast1 = addrspacecast i32* %flat.ptr.1 to i32 addrspace(3)*
; CHECK: %cmp = icmp eq i32 addrspace(3)* %cast0, %cast1 ; CHECK: %cmp = icmp eq i32 addrspace(3)* %cast0, %cast1
define i1 @icmp_flat_to_group_cmp(i32 addrspace(4)* %flat.ptr.0, i32 addrspace(4)* %flat.ptr.1) #0 { define i1 @icmp_flat_to_group_cmp(i32* %flat.ptr.0, i32* %flat.ptr.1) #0 {
%cast0 = addrspacecast i32 addrspace(4)* %flat.ptr.0 to i32 addrspace(3)* %cast0 = addrspacecast i32* %flat.ptr.0 to i32 addrspace(3)*
%cast1 = addrspacecast i32 addrspace(4)* %flat.ptr.1 to i32 addrspace(3)* %cast1 = addrspacecast i32* %flat.ptr.1 to i32 addrspace(3)*
%cmp = icmp eq i32 addrspace(3)* %cast0, %cast1 %cmp = icmp eq i32 addrspace(3)* %cast0, %cast1
ret i1 %cmp ret i1 %cmp
} }
; FIXME: Should be able to ask target about how to constant fold the ; FIXME: Should be able to ask target about how to constant fold the
; constant cast if this is OK to change if 0 is a valid pointer. ; constant cast if this is OK to change if 0 is a valid pointer.
; CHECK-LABEL: @icmp_group_flat_cmp_null( ; CHECK-LABEL: @icmp_group_flat_cmp_null(
; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, addrspacecast (i32 addrspace(4)* null to i32 addrspace(3)*) ; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, addrspacecast (i32* null to i32 addrspace(3)*)
define i1 @icmp_group_flat_cmp_null(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_group_flat_cmp_null(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, null %cmp = icmp eq i32* %cast0, null
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_group_flat_cmp_constant_inttoptr( ; CHECK-LABEL: @icmp_group_flat_cmp_constant_inttoptr(
; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, addrspacecast (i32 addrspace(4)* inttoptr (i64 400 to i32 addrspace(4)*) to i32 addrspace(3)*) ; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, addrspacecast (i32* inttoptr (i64 400 to i32*) to i32 addrspace(3)*)
define i1 @icmp_group_flat_cmp_constant_inttoptr(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_group_flat_cmp_constant_inttoptr(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, inttoptr (i64 400 to i32 addrspace(4)*) %cmp = icmp eq i32* %cast0, inttoptr (i64 400 to i32*)
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_null( ; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_null(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %cmp = icmp eq i32 addrspace(4)* %1, addrspacecast (i32* null to i32 addrspace(4)*) ; CHECK: %cmp = icmp eq i32* %1, addrspacecast (i32 addrspace(5)* null to i32*)
define i1 @icmp_mismatch_flat_group_private_cmp_null(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_mismatch_flat_group_private_cmp_null(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, addrspacecast (i32* null to i32 addrspace(4)*) %cmp = icmp eq i32* %cast0, addrspacecast (i32 addrspace(5)* null to i32*)
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_undef( ; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_undef(
; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, undef ; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, undef
define i1 @icmp_mismatch_flat_group_private_cmp_undef(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_mismatch_flat_group_private_cmp_undef(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, addrspacecast (i32* undef to i32 addrspace(4)*) %cmp = icmp eq i32* %cast0, addrspacecast (i32 addrspace(5)* undef to i32*)
ret i1 %cmp ret i1 %cmp
} }
@lds0 = internal addrspace(3) global i32 0, align 4 @lds0 = internal addrspace(3) global i32 0, align 4
@global0 = internal addrspace(1) global i32 0, align 4 @global0 = internal addrspace(1) global i32 0, align 4
; CHECK-LABEL: @icmp_mismatch_flat_group_global_cmp_gv( ; CHECK-LABEL: @icmp_mismatch_flat_group_global_cmp_gv(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %cmp = icmp eq i32 addrspace(4)* %1, addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*) ; CHECK: %cmp = icmp eq i32* %1, addrspacecast (i32 addrspace(1)* @global0 to i32*)
define i1 @icmp_mismatch_flat_group_global_cmp_gv(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_mismatch_flat_group_global_cmp_gv(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*) %cmp = icmp eq i32* %cast0, addrspacecast (i32 addrspace(1)* @global0 to i32*)
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_mismatch_group_global_cmp_gv_gv( ; CHECK-LABEL: @icmp_mismatch_group_global_cmp_gv_gv(
; CHECK: %cmp = icmp eq i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds0 to i32 addrspace(4)*), addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*) ; CHECK: %cmp = icmp eq i32* addrspacecast (i32 addrspace(3)* @lds0 to i32*), addrspacecast (i32 addrspace(1)* @global0 to i32*)
define i1 @icmp_mismatch_group_global_cmp_gv_gv(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_mismatch_group_global_cmp_gv_gv(i32 addrspace(3)* %group.ptr.0) #0 {
%cmp = icmp eq i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds0 to i32 addrspace(4)*), addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*) %cmp = icmp eq i32* addrspacecast (i32 addrspace(3)* @lds0 to i32*), addrspacecast (i32 addrspace(1)* @global0 to i32*)
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_group_flat_cmp_undef( ; CHECK-LABEL: @icmp_group_flat_cmp_undef(
; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, undef ; CHECK: %cmp = icmp eq i32 addrspace(3)* %group.ptr.0, undef
define i1 @icmp_group_flat_cmp_undef(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_group_flat_cmp_undef(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* %cast0, undef %cmp = icmp eq i32* %cast0, undef
ret i1 %cmp ret i1 %cmp
} }
; Test non-canonical orders ; Test non-canonical orders
; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_null_swap( ; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_null_swap(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %cmp = icmp eq i32 addrspace(4)* addrspacecast (i32* null to i32 addrspace(4)*), %1 ; CHECK: %cmp = icmp eq i32* addrspacecast (i32 addrspace(5)* null to i32*), %1
define i1 @icmp_mismatch_flat_group_private_cmp_null_swap(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_mismatch_flat_group_private_cmp_null_swap(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* addrspacecast (i32* null to i32 addrspace(4)*), %cast0 %cmp = icmp eq i32* addrspacecast (i32 addrspace(5)* null to i32*), %cast0
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_group_flat_cmp_undef_swap( ; CHECK-LABEL: @icmp_group_flat_cmp_undef_swap(
; CHECK: %cmp = icmp eq i32 addrspace(3)* undef, %group.ptr.0 ; CHECK: %cmp = icmp eq i32 addrspace(3)* undef, %group.ptr.0
define i1 @icmp_group_flat_cmp_undef_swap(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_group_flat_cmp_undef_swap(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* undef, %cast0 %cmp = icmp eq i32* undef, %cast0
ret i1 %cmp ret i1 %cmp
} }
; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_undef_swap( ; CHECK-LABEL: @icmp_mismatch_flat_group_private_cmp_undef_swap(
; CHECK: %cmp = icmp eq i32 addrspace(3)* undef, %group.ptr.0 ; CHECK: %cmp = icmp eq i32 addrspace(3)* undef, %group.ptr.0
define i1 @icmp_mismatch_flat_group_private_cmp_undef_swap(i32 addrspace(3)* %group.ptr.0) #0 { define i1 @icmp_mismatch_flat_group_private_cmp_undef_swap(i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cmp = icmp eq i32 addrspace(4)* addrspacecast (i32* undef to i32 addrspace(4)*), %cast0 %cmp = icmp eq i32* addrspacecast (i32 addrspace(5)* undef to i32*), %cast0
ret i1 %cmp ret i1 %cmp
} }
; TODO: Should be handled ; TODO: Should be handled
; CHECK-LABEL: @icmp_flat_flat_from_group_vector( ; CHECK-LABEL: @icmp_flat_flat_from_group_vector(
; CHECK: %cmp = icmp eq <2 x i32 addrspace(4)*> %cast0, %cast1 ; CHECK: %cmp = icmp eq <2 x i32*> %cast0, %cast1
define <2 x i1> @icmp_flat_flat_from_group_vector(<2 x i32 addrspace(3)*> %group.ptr.0, <2 x i32 addrspace(3)*> %group.ptr.1) #0 { define <2 x i1> @icmp_flat_flat_from_group_vector(<2 x i32 addrspace(3)*> %group.ptr.0, <2 x i32 addrspace(3)*> %group.ptr.1) #0 {
%cast0 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.0 to <2 x i32 addrspace(4)*> %cast0 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.0 to <2 x i32*>
%cast1 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.1 to <2 x i32 addrspace(4)*> %cast1 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.1 to <2 x i32*>
%cmp = icmp eq <2 x i32 addrspace(4)*> %cast0, %cast1 %cmp = icmp eq <2 x i32*> %cast0, %cast1
ret <2 x i1> %cmp ret <2 x i1> %cmp
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/Transforms/InferAddressSpaces/AMDGPU/infer-address-space.ll

Show All 24 Lines
; CHECK: %tmp7 = getelementptr inbounds [10 x float], [10 x float] addrspace(3)* @array, i32 0, i32 %i ; CHECK: %tmp7 = getelementptr inbounds [10 x float], [10 x float] addrspace(3)* @array, i32 0, i32 %i
; CHECK: %tmp8 = load float, float addrspace(3)* %tmp7, align 4 ; CHECK: %tmp8 = load float, float addrspace(3)* %tmp7, align 4
; CHECK: call void @use(float %tmp8) ; CHECK: call void @use(float %tmp8)
; CHECK: store float %v, float addrspace(3)* %tmp7, align 4 ; CHECK: store float %v, float addrspace(3)* %tmp7, align 4
; CHECK: call void @llvm.amdgcn.s.barrier() ; CHECK: call void @llvm.amdgcn.s.barrier()
; CHECK: ret void ; CHECK: ret void
define amdgpu_kernel void @load_store_lds_f32(i32 %i, float %v) #0 { define amdgpu_kernel void @load_store_lds_f32(i32 %i, float %v) #0 {
bb: bb:
%tmp = load float, float addrspace(4)* addrspacecast (float addrspace(3)* @scalar to float addrspace(4)*), align 4 %tmp = load float, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4
call void @use(float %tmp) call void @use(float %tmp)
store float %v, float addrspace(4)* addrspacecast (float addrspace(3)* @scalar to float addrspace(4)*), align 4 store float %v, float* addrspacecast (float addrspace(3)* @scalar to float*), align 4
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%tmp1 = addrspacecast float addrspace(3)* @scalar to float addrspace(4)* %tmp1 = addrspacecast float addrspace(3)* @scalar to float*
%tmp2 = load float, float addrspace(4)* %tmp1, align 4 %tmp2 = load float, float* %tmp1, align 4
call void @use(float %tmp2) call void @use(float %tmp2)
store float %v, float addrspace(4)* %tmp1, align 4 store float %v, float* %tmp1, align 4
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%tmp3 = load float, float addrspace(4)* getelementptr inbounds ([10 x float], [10 x float] addrspace(4)* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float] addrspace(4)*), i32 0, i32 5), align 4 %tmp3 = load float, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
call void @use(float %tmp3) call void @use(float %tmp3)
store float %v, float addrspace(4)* getelementptr inbounds ([10 x float], [10 x float] addrspace(4)* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float] addrspace(4)*), i32 0, i32 5), align 4 store float %v, float* getelementptr inbounds ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5), align 4
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%tmp4 = getelementptr inbounds [10 x float], [10 x float] addrspace(4)* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float] addrspace(4)*), i32 0, i32 5 %tmp4 = getelementptr inbounds [10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i32 0, i32 5
%tmp5 = load float, float addrspace(4)* %tmp4, align 4 %tmp5 = load float, float* %tmp4, align 4
call void @use(float %tmp5) call void @use(float %tmp5)
store float %v, float addrspace(4)* %tmp4, align 4 store float %v, float* %tmp4, align 4
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
%tmp6 = addrspacecast [10 x float] addrspace(3)* @array to [10 x float] addrspace(4)* %tmp6 = addrspacecast [10 x float] addrspace(3)* @array to [10 x float]*
%tmp7 = getelementptr inbounds [10 x float], [10 x float] addrspace(4)* %tmp6, i32 0, i32 %i %tmp7 = getelementptr inbounds [10 x float], [10 x float]* %tmp6, i32 0, i32 %i
%tmp8 = load float, float addrspace(4)* %tmp7, align 4 %tmp8 = load float, float* %tmp7, align 4
call void @use(float %tmp8) call void @use(float %tmp8)
store float %v, float addrspace(4)* %tmp7, align 4 store float %v, float* %tmp7, align 4
call void @llvm.amdgcn.s.barrier() call void @llvm.amdgcn.s.barrier()
ret void ret void
} }
; CHECK-LABEL: @constexpr_load_int_from_float_lds( ; CHECK-LABEL: @constexpr_load_int_from_float_lds(
; CHECK: %tmp = load i32, i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*), align 4 ; CHECK: %tmp = load i32, i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*), align 4
define i32 @constexpr_load_int_from_float_lds() #0 { define i32 @constexpr_load_int_from_float_lds() #0 {
bb: bb:
%tmp = load i32, i32 addrspace(4)* addrspacecast (i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*) to i32 addrspace(4)*), align 4 %tmp = load i32, i32* addrspacecast (i32 addrspace(3)* bitcast (float addrspace(3)* @scalar to i32 addrspace(3)*) to i32*), align 4
ret i32 %tmp ret i32 %tmp
} }
; CHECK-LABEL: @load_int_from_global_float( ; CHECK-LABEL: @load_int_from_global_float(
; CHECK: %tmp1 = getelementptr float, float addrspace(1)* %input, i32 %i ; CHECK: %tmp1 = getelementptr float, float addrspace(1)* %input, i32 %i
; CHECK: %tmp2 = getelementptr float, float addrspace(1)* %tmp1, i32 %j ; CHECK: %tmp2 = getelementptr float, float addrspace(1)* %tmp1, i32 %j
; CHECK: %tmp3 = bitcast float addrspace(1)* %tmp2 to i32 addrspace(1)* ; CHECK: %tmp3 = bitcast float addrspace(1)* %tmp2 to i32 addrspace(1)*
; CHECK: %tmp4 = load i32, i32 addrspace(1)* %tmp3 ; CHECK: %tmp4 = load i32, i32 addrspace(1)* %tmp3
; CHECK: ret i32 %tmp4 ; CHECK: ret i32 %tmp4
define i32 @load_int_from_global_float(float addrspace(1)* %input, i32 %i, i32 %j) #0 { define i32 @load_int_from_global_float(float addrspace(1)* %input, i32 %i, i32 %j) #0 {
bb: bb:
%tmp = addrspacecast float addrspace(1)* %input to float addrspace(4)* %tmp = addrspacecast float addrspace(1)* %input to float*
%tmp1 = getelementptr float, float addrspace(4)* %tmp, i32 %i %tmp1 = getelementptr float, float* %tmp, i32 %i
%tmp2 = getelementptr float, float addrspace(4)* %tmp1, i32 %j %tmp2 = getelementptr float, float* %tmp1, i32 %j
%tmp3 = bitcast float addrspace(4)* %tmp2 to i32 addrspace(4)* %tmp3 = bitcast float* %tmp2 to i32*
%tmp4 = load i32, i32 addrspace(4)* %tmp3 %tmp4 = load i32, i32* %tmp3
ret i32 %tmp4 ret i32 %tmp4
} }
; CHECK-LABEL: @nested_const_expr( ; CHECK-LABEL: @nested_const_expr(
; CHECK: store i32 1, i32 addrspace(3)* bitcast (float addrspace(3)* getelementptr inbounds ([10 x float], [10 x float] addrspace(3)* @array, i64 0, i64 1) to i32 addrspace(3)*), align 4 ; CHECK: store i32 1, i32 addrspace(3)* bitcast (float addrspace(3)* getelementptr inbounds ([10 x float], [10 x float] addrspace(3)* @array, i64 0, i64 1) to i32 addrspace(3)*), align 4
define amdgpu_kernel void @nested_const_expr() #0 { define amdgpu_kernel void @nested_const_expr() #0 {
store i32 1, i32 addrspace(4)* bitcast (float addrspace(4)* getelementptr ([10 x float], [10 x float] addrspace(4)* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float] addrspace(4)*), i64 0, i64 1) to i32 addrspace(4)*), align 4 store i32 1, i32* bitcast (float* getelementptr ([10 x float], [10 x float]* addrspacecast ([10 x float] addrspace(3)* @array to [10 x float]*), i64 0, i64 1) to i32*), align 4
ret void ret void
} }
; CHECK-LABEL: @rauw( ; CHECK-LABEL: @rauw(
; CHECK: %addr = getelementptr float, float addrspace(1)* %input, i64 10 ; CHECK: %addr = getelementptr float, float addrspace(1)* %input, i64 10
; CHECK-NEXT: %v = load float, float addrspace(1)* %addr ; CHECK-NEXT: %v = load float, float addrspace(1)* %addr
; CHECK-NEXT: store float %v, float addrspace(1)* %addr ; CHECK-NEXT: store float %v, float addrspace(1)* %addr
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define amdgpu_kernel void @rauw(float addrspace(1)* %input) #0 { define amdgpu_kernel void @rauw(float addrspace(1)* %input) #0 {
bb: bb:
%generic_input = addrspacecast float addrspace(1)* %input to float addrspace(4)* %generic_input = addrspacecast float addrspace(1)* %input to float*
%addr = getelementptr float, float addrspace(4)* %generic_input, i64 10 %addr = getelementptr float, float* %generic_input, i64 10
%v = load float, float addrspace(4)* %addr %v = load float, float* %addr
store float %v, float addrspace(4)* %addr store float %v, float* %addr
ret void ret void
} }
; FIXME: Should be able to eliminate the cast inside the loop ; FIXME: Should be able to eliminate the cast inside the loop
; CHECK-LABEL: @loop( ; CHECK-LABEL: @loop(
; CHECK: %p = bitcast [10 x float] addrspace(3)* @array to float addrspace(3)* ; CHECK: %p = bitcast [10 x float] addrspace(3)* @array to float addrspace(3)*
; CHECK: %end = getelementptr float, float addrspace(3)* %p, i64 10 ; CHECK: %end = getelementptr float, float addrspace(3)* %p, i64 10
; CHECK: br label %loop ; CHECK: br label %loop
; CHECK: loop: ; preds = %loop, %entry ; CHECK: loop: ; preds = %loop, %entry
; CHECK: %i = phi float addrspace(3)* [ %p, %entry ], [ %i2, %loop ] ; CHECK: %i = phi float addrspace(3)* [ %p, %entry ], [ %i2, %loop ]
; CHECK: %v = load float, float addrspace(3)* %i ; CHECK: %v = load float, float addrspace(3)* %i
; CHECK: call void @use(float %v) ; CHECK: call void @use(float %v)
; CHECK: %i2 = getelementptr float, float addrspace(3)* %i, i64 1 ; CHECK: %i2 = getelementptr float, float addrspace(3)* %i, i64 1
; CHECK: %exit_cond = icmp eq float addrspace(3)* %i2, %end ; CHECK: %exit_cond = icmp eq float addrspace(3)* %i2, %end
; CHECK: br i1 %exit_cond, label %exit, label %loop ; CHECK: br i1 %exit_cond, label %exit, label %loop
define amdgpu_kernel void @loop() #0 { define amdgpu_kernel void @loop() #0 {
entry: entry:
%p = addrspacecast [10 x float] addrspace(3)* @array to float addrspace(4)* %p = addrspacecast [10 x float] addrspace(3)* @array to float*
%end = getelementptr float, float addrspace(4)* %p, i64 10 %end = getelementptr float, float* %p, i64 10
br label %loop br label %loop
loop: ; preds = %loop, %entry loop: ; preds = %loop, %entry
%i = phi float addrspace(4)* [ %p, %entry ], [ %i2, %loop ] %i = phi float* [ %p, %entry ], [ %i2, %loop ]
%v = load float, float addrspace(4)* %i %v = load float, float* %i
call void @use(float %v) call void @use(float %v)
%i2 = getelementptr float, float addrspace(4)* %i, i64 1 %i2 = getelementptr float, float* %i, i64 1
%exit_cond = icmp eq float addrspace(4)* %i2, %end %exit_cond = icmp eq float* %i2, %end
br i1 %exit_cond, label %exit, label %loop br i1 %exit_cond, label %exit, label %loop
exit: ; preds = %loop exit: ; preds = %loop
ret void ret void
} }
@generic_end = external addrspace(1) global float addrspace(4)* @generic_end = external addrspace(1) global float*
; CHECK-LABEL: @loop_with_generic_bound( ; CHECK-LABEL: @loop_with_generic_bound(
; CHECK: %p = bitcast [10 x float] addrspace(3)* @array to float addrspace(3)* ; CHECK: %p = bitcast [10 x float] addrspace(3)* @array to float addrspace(3)*
; CHECK: %end = load float addrspace(4)*, float addrspace(4)* addrspace(1)* @generic_end ; CHECK: %end = load float*, float* addrspace(1)* @generic_end
; CHECK: br label %loop ; CHECK: br label %loop
; CHECK: loop: ; CHECK: loop:
; CHECK: %i = phi float addrspace(3)* [ %p, %entry ], [ %i2, %loop ] ; CHECK: %i = phi float addrspace(3)* [ %p, %entry ], [ %i2, %loop ]
; CHECK: %v = load float, float addrspace(3)* %i ; CHECK: %v = load float, float addrspace(3)* %i
; CHECK: call void @use(float %v) ; CHECK: call void @use(float %v)
; CHECK: %i2 = getelementptr float, float addrspace(3)* %i, i64 1 ; CHECK: %i2 = getelementptr float, float addrspace(3)* %i, i64 1
; CHECK: %0 = addrspacecast float addrspace(3)* %i2 to float addrspace(4)* ; CHECK: %0 = addrspacecast float addrspace(3)* %i2 to float*
; CHECK: %exit_cond = icmp eq float addrspace(4)* %0, %end ; CHECK: %exit_cond = icmp eq float* %0, %end
; CHECK: br i1 %exit_cond, label %exit, label %loop ; CHECK: br i1 %exit_cond, label %exit, label %loop
define amdgpu_kernel void @loop_with_generic_bound() #0 { define amdgpu_kernel void @loop_with_generic_bound() #0 {
entry: entry:
%p = addrspacecast [10 x float] addrspace(3)* @array to float addrspace(4)* %p = addrspacecast [10 x float] addrspace(3)* @array to float*
%end = load float addrspace(4)*, float addrspace(4)* addrspace(1)* @generic_end %end = load float*, float* addrspace(1)* @generic_end
br label %loop br label %loop
loop: ; preds = %loop, %entry loop: ; preds = %loop, %entry
%i = phi float addrspace(4)* [ %p, %entry ], [ %i2, %loop ] %i = phi float* [ %p, %entry ], [ %i2, %loop ]
%v = load float, float addrspace(4)* %i %v = load float, float* %i
call void @use(float %v) call void @use(float %v)
%i2 = getelementptr float, float addrspace(4)* %i, i64 1 %i2 = getelementptr float, float* %i, i64 1
%exit_cond = icmp eq float addrspace(4)* %i2, %end %exit_cond = icmp eq float* %i2, %end
br i1 %exit_cond, label %exit, label %loop br i1 %exit_cond, label %exit, label %loop
exit: ; preds = %loop exit: ; preds = %loop
ret void ret void
} }
declare void @llvm.amdgcn.s.barrier() #1 declare void @llvm.amdgcn.s.barrier() #1
declare void @use(float) #0 declare void @use(float) #0
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { convergent nounwind } attributes #1 = { convergent nounwind }

test/Transforms/InferAddressSpaces/AMDGPU/infer-addrspacecast.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; Test that pure addrspacecast instructions not directly connected to ; Test that pure addrspacecast instructions not directly connected to
; a memory operation are inferred. ; a memory operation are inferred.
; CHECK-LABEL: @addrspacecast_gep_addrspacecast( ; CHECK-LABEL: @addrspacecast_gep_addrspacecast(
; CHECK: %gep0 = getelementptr i32, i32 addrspace(3)* %ptr, i64 9 ; CHECK: %gep0 = getelementptr i32, i32 addrspace(3)* %ptr, i64 9
; CHECK-NEXT: store i32 8, i32 addrspace(3)* %gep0, align 8 ; CHECK-NEXT: store i32 8, i32 addrspace(3)* %gep0, align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define void @addrspacecast_gep_addrspacecast(i32 addrspace(3)* %ptr) { define void @addrspacecast_gep_addrspacecast(i32 addrspace(3)* %ptr) {
%asc0 = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %asc0 = addrspacecast i32 addrspace(3)* %ptr to i32*
%gep0 = getelementptr i32, i32 addrspace(4)* %asc0, i64 9 %gep0 = getelementptr i32, i32* %asc0, i64 9
%asc1 = addrspacecast i32 addrspace(4)* %gep0 to i32 addrspace(3)* %asc1 = addrspacecast i32* %gep0 to i32 addrspace(3)*
store i32 8, i32 addrspace(3)* %asc1, align 8 store i32 8, i32 addrspace(3)* %asc1, align 8
ret void ret void
} }
; CHECK-LABEL: @addrspacecast_different_pointee_type( ; CHECK-LABEL: @addrspacecast_different_pointee_type(
; CHECK: [[GEP:%.*]] = getelementptr i32, i32 addrspace(3)* %ptr, i64 9 ; CHECK: [[GEP:%.*]] = getelementptr i32, i32 addrspace(3)* %ptr, i64 9
; CHECK: [[CAST:%.*]] = bitcast i32 addrspace(3)* [[GEP]] to i8 addrspace(3)* ; CHECK: [[CAST:%.*]] = bitcast i32 addrspace(3)* [[GEP]] to i8 addrspace(3)*
; CHECK-NEXT: store i8 8, i8 addrspace(3)* [[CAST]], align 8 ; CHECK-NEXT: store i8 8, i8 addrspace(3)* [[CAST]], align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define void @addrspacecast_different_pointee_type(i32 addrspace(3)* %ptr) { define void @addrspacecast_different_pointee_type(i32 addrspace(3)* %ptr) {
%asc0 = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %asc0 = addrspacecast i32 addrspace(3)* %ptr to i32*
%gep0 = getelementptr i32, i32 addrspace(4)* %asc0, i64 9 %gep0 = getelementptr i32, i32* %asc0, i64 9
%asc1 = addrspacecast i32 addrspace(4)* %gep0 to i8 addrspace(3)* %asc1 = addrspacecast i32* %gep0 to i8 addrspace(3)*
store i8 8, i8 addrspace(3)* %asc1, align 8 store i8 8, i8 addrspace(3)* %asc1, align 8
ret void ret void
} }
; CHECK-LABEL: @addrspacecast_to_memory( ; CHECK-LABEL: @addrspacecast_to_memory(
; CHECK: %gep0 = getelementptr i32, i32 addrspace(3)* %ptr, i64 9 ; CHECK: %gep0 = getelementptr i32, i32 addrspace(3)* %ptr, i64 9
; CHECK-NEXT: store volatile i32 addrspace(3)* %gep0, i32 addrspace(3)* addrspace(1)* undef ; CHECK-NEXT: store volatile i32 addrspace(3)* %gep0, i32 addrspace(3)* addrspace(1)* undef
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define void @addrspacecast_to_memory(i32 addrspace(3)* %ptr) { define void @addrspacecast_to_memory(i32 addrspace(3)* %ptr) {
%asc0 = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %asc0 = addrspacecast i32 addrspace(3)* %ptr to i32*
%gep0 = getelementptr i32, i32 addrspace(4)* %asc0, i64 9 %gep0 = getelementptr i32, i32* %asc0, i64 9
%asc1 = addrspacecast i32 addrspace(4)* %gep0 to i32 addrspace(3)* %asc1 = addrspacecast i32* %gep0 to i32 addrspace(3)*
store volatile i32 addrspace(3)* %asc1, i32 addrspace(3)* addrspace(1)* undef store volatile i32 addrspace(3)* %asc1, i32 addrspace(3)* addrspace(1)* undef
ret void ret void
} }
; CHECK-LABEL: @multiuse_addrspacecast_gep_addrspacecast( ; CHECK-LABEL: @multiuse_addrspacecast_gep_addrspacecast(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %ptr to i32*
; CHECK-NEXT: store volatile i32 addrspace(4)* %1, i32 addrspace(4)* addrspace(1)* undef ; CHECK-NEXT: store volatile i32* %1, i32* addrspace(1)* undef
; CHECK-NEXT: %gep0 = getelementptr i32, i32 addrspace(3)* %ptr, i64 9 ; CHECK-NEXT: %gep0 = getelementptr i32, i32 addrspace(3)* %ptr, i64 9
; CHECK-NEXT: store i32 8, i32 addrspace(3)* %gep0, align 8 ; CHECK-NEXT: store i32 8, i32 addrspace(3)* %gep0, align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define void @multiuse_addrspacecast_gep_addrspacecast(i32 addrspace(3)* %ptr) { define void @multiuse_addrspacecast_gep_addrspacecast(i32 addrspace(3)* %ptr) {
%asc0 = addrspacecast i32 addrspace(3)* %ptr to i32 addrspace(4)* %asc0 = addrspacecast i32 addrspace(3)* %ptr to i32*
store volatile i32 addrspace(4)* %asc0, i32 addrspace(4)* addrspace(1)* undef store volatile i32* %asc0, i32* addrspace(1)* undef
%gep0 = getelementptr i32, i32 addrspace(4)* %asc0, i64 9 %gep0 = getelementptr i32, i32* %asc0, i64 9
%asc1 = addrspacecast i32 addrspace(4)* %gep0 to i32 addrspace(3)* %asc1 = addrspacecast i32* %gep0 to i32 addrspace(3)*
store i32 8, i32 addrspace(3)* %asc1, align 8 store i32 8, i32 addrspace(3)* %asc1, align 8
ret void ret void
} }

test/Transforms/InferAddressSpaces/AMDGPU/infer-getelementptr.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; Test that pure GetElementPtr instructions not directly connected to ; Test that pure GetElementPtr instructions not directly connected to
; a memory operation are inferred. ; a memory operation are inferred.
@lds = internal unnamed_addr addrspace(3) global [648 x double] undef, align 8 @lds = internal unnamed_addr addrspace(3) global [648 x double] undef, align 8
; CHECK-LABEL: @simplified_constexpr_gep_addrspacecast( ; CHECK-LABEL: @simplified_constexpr_gep_addrspacecast(
; CHECK: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0 ; CHECK: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0
; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep0, align 8 ; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep0, align 8
define void @simplified_constexpr_gep_addrspacecast(i64 %idx0, i64 %idx1) { define void @simplified_constexpr_gep_addrspacecast(i64 %idx0, i64 %idx1) {
%gep0 = getelementptr inbounds double, double addrspace(4)* addrspacecast (double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384) to double addrspace(4)*), i64 %idx0 %gep0 = getelementptr inbounds double, double* addrspacecast (double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384) to double*), i64 %idx0
%asc = addrspacecast double addrspace(4)* %gep0 to double addrspace(3)* %asc = addrspacecast double* %gep0 to double addrspace(3)*
store double 1.000000e+00, double addrspace(3)* %asc, align 8 store double 1.000000e+00, double addrspace(3)* %asc, align 8
ret void ret void
} }
; CHECK-LABEL: @constexpr_gep_addrspacecast( ; CHECK-LABEL: @constexpr_gep_addrspacecast(
; CHECK-NEXT: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0 ; CHECK-NEXT: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0
; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep0, align 8 ; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep0, align 8
define void @constexpr_gep_addrspacecast(i64 %idx0, i64 %idx1) { define void @constexpr_gep_addrspacecast(i64 %idx0, i64 %idx1) {
%gep0 = getelementptr inbounds double, double addrspace(4)* getelementptr ([648 x double], [648 x double] addrspace(4)* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double] addrspace(4)*), i64 0, i64 384), i64 %idx0 %gep0 = getelementptr inbounds double, double* getelementptr ([648 x double], [648 x double]* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double]*), i64 0, i64 384), i64 %idx0
%asc = addrspacecast double addrspace(4)* %gep0 to double addrspace(3)* %asc = addrspacecast double* %gep0 to double addrspace(3)*
store double 1.0, double addrspace(3)* %asc, align 8 store double 1.0, double addrspace(3)* %asc, align 8
ret void ret void
} }
; CHECK-LABEL: @constexpr_gep_gep_addrspacecast( ; CHECK-LABEL: @constexpr_gep_gep_addrspacecast(
; CHECK: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0 ; CHECK: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0
; CHECK-NEXT: %gep1 = getelementptr inbounds double, double addrspace(3)* %gep0, i64 %idx1 ; CHECK-NEXT: %gep1 = getelementptr inbounds double, double addrspace(3)* %gep0, i64 %idx1
; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep1, align 8 ; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep1, align 8
define void @constexpr_gep_gep_addrspacecast(i64 %idx0, i64 %idx1) { define void @constexpr_gep_gep_addrspacecast(i64 %idx0, i64 %idx1) {
%gep0 = getelementptr inbounds double, double addrspace(4)* getelementptr ([648 x double], [648 x double] addrspace(4)* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double] addrspace(4)*), i64 0, i64 384), i64 %idx0 %gep0 = getelementptr inbounds double, double* getelementptr ([648 x double], [648 x double]* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double]*), i64 0, i64 384), i64 %idx0
%gep1 = getelementptr inbounds double, double addrspace(4)* %gep0, i64 %idx1 %gep1 = getelementptr inbounds double, double* %gep0, i64 %idx1
%asc = addrspacecast double addrspace(4)* %gep1 to double addrspace(3)* %asc = addrspacecast double* %gep1 to double addrspace(3)*
store double 1.0, double addrspace(3)* %asc, align 8 store double 1.0, double addrspace(3)* %asc, align 8
ret void ret void
} }
; Don't crash ; Don't crash
; CHECK-LABEL: @vector_gep( ; CHECK-LABEL: @vector_gep(
; CHECK: %cast = addrspacecast <4 x [1024 x i32] addrspace(3)*> %array to <4 x [1024 x i32] addrspace(4)*> ; CHECK: %cast = addrspacecast <4 x [1024 x i32] addrspace(3)*> %array to <4 x [1024 x i32]*>
define amdgpu_kernel void @vector_gep(<4 x [1024 x i32] addrspace(3)*> %array) nounwind { define amdgpu_kernel void @vector_gep(<4 x [1024 x i32] addrspace(3)*> %array) nounwind {
%cast = addrspacecast <4 x [1024 x i32] addrspace(3)*> %array to <4 x [1024 x i32] addrspace(4)*> %cast = addrspacecast <4 x [1024 x i32] addrspace(3)*> %array to <4 x [1024 x i32]*>
%p = getelementptr [1024 x i32], <4 x [1024 x i32] addrspace(4)*> %cast, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16> %p = getelementptr [1024 x i32], <4 x [1024 x i32]*> %cast, <4 x i16> zeroinitializer, <4 x i16> <i16 16, i16 16, i16 16, i16 16>
%p0 = extractelement <4 x i32 addrspace(4)*> %p, i32 0 %p0 = extractelement <4 x i32*> %p, i32 0
%p1 = extractelement <4 x i32 addrspace(4)*> %p, i32 1 %p1 = extractelement <4 x i32*> %p, i32 1
%p2 = extractelement <4 x i32 addrspace(4)*> %p, i32 2 %p2 = extractelement <4 x i32*> %p, i32 2
%p3 = extractelement <4 x i32 addrspace(4)*> %p, i32 3 %p3 = extractelement <4 x i32*> %p, i32 3
store i32 99, i32 addrspace(4)* %p0 store i32 99, i32* %p0
store i32 99, i32 addrspace(4)* %p1 store i32 99, i32* %p1
store i32 99, i32 addrspace(4)* %p2 store i32 99, i32* %p2
store i32 99, i32 addrspace(4)* %p3 store i32 99, i32* %p3
ret void ret void
} }
; CHECK-LABEL: @repeated_constexpr_gep_addrspacecast( ; CHECK-LABEL: @repeated_constexpr_gep_addrspacecast(
; CHECK-NEXT: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0 ; CHECK-NEXT: %gep0 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx0
; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep0, align 8 ; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep0, align 8
; CHECK-NEXT: %gep1 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx1 ; CHECK-NEXT: %gep1 = getelementptr inbounds double, double addrspace(3)* getelementptr inbounds ([648 x double], [648 x double] addrspace(3)* @lds, i64 0, i64 384), i64 %idx1
; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep1, align 8 ; CHECK-NEXT: store double 1.000000e+00, double addrspace(3)* %gep1, align 8
; CHECK-NEXT: ret void ; CHECK-NEXT: ret void
define void @repeated_constexpr_gep_addrspacecast(i64 %idx0, i64 %idx1) { define void @repeated_constexpr_gep_addrspacecast(i64 %idx0, i64 %idx1) {
%gep0 = getelementptr inbounds double, double addrspace(4)* getelementptr ([648 x double], [648 x double] addrspace(4)* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double] addrspace(4)*), i64 0, i64 384), i64 %idx0 %gep0 = getelementptr inbounds double, double* getelementptr ([648 x double], [648 x double]* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double]*), i64 0, i64 384), i64 %idx0
%asc0 = addrspacecast double addrspace(4)* %gep0 to double addrspace(3)* %asc0 = addrspacecast double* %gep0 to double addrspace(3)*
store double 1.0, double addrspace(3)* %asc0, align 8 store double 1.0, double addrspace(3)* %asc0, align 8
%gep1 = getelementptr inbounds double, double addrspace(4)* getelementptr ([648 x double], [648 x double] addrspace(4)* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double] addrspace(4)*), i64 0, i64 384), i64 %idx1 %gep1 = getelementptr inbounds double, double* getelementptr ([648 x double], [648 x double]* addrspacecast ([648 x double] addrspace(3)* @lds to [648 x double]*), i64 0, i64 384), i64 %idx1
%asc1 = addrspacecast double addrspace(4)* %gep1 to double addrspace(3)* %asc1 = addrspacecast double* %gep1 to double addrspace(3)*
store double 1.0, double addrspace(3)* %asc1, align 8 store double 1.0, double addrspace(3)* %asc1, align 8
ret void ret void
} }

test/Transforms/InferAddressSpaces/AMDGPU/intrinsics.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; CHECK-LABEL: @objectsize_group_to_flat_i32( ; CHECK-LABEL: @objectsize_group_to_flat_i32(
; CHECK: %val = call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* %group.ptr, i1 true, i1 false) ; CHECK: %val = call i32 @llvm.objectsize.i32.p3i8(i8 addrspace(3)* %group.ptr, i1 true, i1 false)
define i32 @objectsize_group_to_flat_i32(i8 addrspace(3)* %group.ptr) #0 { define i32 @objectsize_group_to_flat_i32(i8 addrspace(3)* %group.ptr) #0 {
%cast = addrspacecast i8 addrspace(3)* %group.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
%val = call i32 @llvm.objectsize.i32.p4i8(i8 addrspace(4)* %cast, i1 true, i1 false) %val = call i32 @llvm.objectsize.i32.p0i8(i8* %cast, i1 true, i1 false)
ret i32 %val ret i32 %val
} }
; CHECK-LABEL: @objectsize_global_to_flat_i64( ; CHECK-LABEL: @objectsize_global_to_flat_i64(
; CHECK: %val = call i64 @llvm.objectsize.i64.p3i8(i8 addrspace(3)* %global.ptr, i1 true, i1 false) ; CHECK: %val = call i64 @llvm.objectsize.i64.p3i8(i8 addrspace(3)* %global.ptr, i1 true, i1 false)
define i64 @objectsize_global_to_flat_i64(i8 addrspace(3)* %global.ptr) #0 { define i64 @objectsize_global_to_flat_i64(i8 addrspace(3)* %global.ptr) #0 {
%cast = addrspacecast i8 addrspace(3)* %global.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(3)* %global.ptr to i8*
%val = call i64 @llvm.objectsize.i64.p4i8(i8 addrspace(4)* %cast, i1 true, i1 false) %val = call i64 @llvm.objectsize.i64.p0i8(i8* %cast, i1 true, i1 false)
ret i64 %val ret i64 %val
} }
; CHECK-LABEL: @atomicinc_global_to_flat_i32( ; CHECK-LABEL: @atomicinc_global_to_flat_i32(
; CHECK: call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %global.ptr, i32 %y, i32 0, i32 0, i1 false) ; CHECK: call i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* %global.ptr, i32 %y, i32 0, i32 0, i1 false)
define i32 @atomicinc_global_to_flat_i32(i32 addrspace(1)* %global.ptr, i32 %y) #0 { define i32 @atomicinc_global_to_flat_i32(i32 addrspace(1)* %global.ptr, i32 %y) #0 {
%cast = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %global.ptr to i32*
%ret = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %cast, i32 %y, i32 0, i32 0, i1 false) %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %cast, i32 %y, i32 0, i32 0, i1 false)
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @atomicinc_group_to_flat_i32( ; CHECK-LABEL: @atomicinc_group_to_flat_i32(
; CHECK: %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %group.ptr, i32 %y, i32 0, i32 0, i1 false) ; CHECK: %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %group.ptr, i32 %y, i32 0, i32 0, i1 false)
define i32 @atomicinc_group_to_flat_i32(i32 addrspace(3)* %group.ptr, i32 %y) #0 { define i32 @atomicinc_group_to_flat_i32(i32 addrspace(3)* %group.ptr, i32 %y) #0 {
%cast = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* %group.ptr to i32*
%ret = call i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* %cast, i32 %y, i32 0, i32 0, i1 false) %ret = call i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* %cast, i32 %y, i32 0, i32 0, i1 false)
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @atomicinc_global_to_flat_i64( ; CHECK-LABEL: @atomicinc_global_to_flat_i64(
; CHECK: call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %global.ptr, i64 %y, i32 0, i32 0, i1 false) ; CHECK: call i64 @llvm.amdgcn.atomic.inc.i64.p1i64(i64 addrspace(1)* %global.ptr, i64 %y, i32 0, i32 0, i1 false)
define i64 @atomicinc_global_to_flat_i64(i64 addrspace(1)* %global.ptr, i64 %y) #0 { define i64 @atomicinc_global_to_flat_i64(i64 addrspace(1)* %global.ptr, i64 %y) #0 {
%cast = addrspacecast i64 addrspace(1)* %global.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(1)* %global.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 false) %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 false)
ret i64 %ret ret i64 %ret
} }
; CHECK-LABEL: @atomicinc_group_to_flat_i64( ; CHECK-LABEL: @atomicinc_group_to_flat_i64(
; CHECK: call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %group.ptr, i64 %y, i32 0, i32 0, i1 false) ; CHECK: call i64 @llvm.amdgcn.atomic.inc.i64.p3i64(i64 addrspace(3)* %group.ptr, i64 %y, i32 0, i32 0, i1 false)
define i64 @atomicinc_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 { define i64 @atomicinc_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 {
%cast = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(3)* %group.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 false) %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 false)
ret i64 %ret ret i64 %ret
} }
; CHECK-LABEL: @atomicdec_global_to_flat_i32( ; CHECK-LABEL: @atomicdec_global_to_flat_i32(
; CHECK: call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %global.ptr, i32 %val, i32 0, i32 0, i1 false) ; CHECK: call i32 @llvm.amdgcn.atomic.dec.i32.p1i32(i32 addrspace(1)* %global.ptr, i32 %val, i32 0, i32 0, i1 false)
define i32 @atomicdec_global_to_flat_i32(i32 addrspace(1)* %global.ptr, i32 %val) #0 { define i32 @atomicdec_global_to_flat_i32(i32 addrspace(1)* %global.ptr, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %global.ptr to i32*
%ret = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %cast, i32 %val, i32 0, i32 0, i1 false) %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 false)
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @atomicdec_group_to_flat_i32( ; CHECK-LABEL: @atomicdec_group_to_flat_i32(
; CHECK: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %group.ptr, i32 %val, i32 0, i32 0, i1 false) ; CHECK: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p3i32(i32 addrspace(3)* %group.ptr, i32 %val, i32 0, i32 0, i1 false)
define i32 @atomicdec_group_to_flat_i32(i32 addrspace(3)* %group.ptr, i32 %val) #0 { define i32 @atomicdec_group_to_flat_i32(i32 addrspace(3)* %group.ptr, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* %group.ptr to i32*
%ret = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %cast, i32 %val, i32 0, i32 0, i1 false) %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 false)
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @atomicdec_global_to_flat_i64( ; CHECK-LABEL: @atomicdec_global_to_flat_i64(
; CHECK: call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %global.ptr, i64 %y, i32 0, i32 0, i1 false) ; CHECK: call i64 @llvm.amdgcn.atomic.dec.i64.p1i64(i64 addrspace(1)* %global.ptr, i64 %y, i32 0, i32 0, i1 false)
define i64 @atomicdec_global_to_flat_i64(i64 addrspace(1)* %global.ptr, i64 %y) #0 { define i64 @atomicdec_global_to_flat_i64(i64 addrspace(1)* %global.ptr, i64 %y) #0 {
%cast = addrspacecast i64 addrspace(1)* %global.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(1)* %global.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 false) %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 false)
ret i64 %ret ret i64 %ret
} }
; CHECK-LABEL: @atomicdec_group_to_flat_i64( ; CHECK-LABEL: @atomicdec_group_to_flat_i64(
; CHECK: call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %group.ptr, i64 %y, i32 0, i32 0, i1 false ; CHECK: call i64 @llvm.amdgcn.atomic.dec.i64.p3i64(i64 addrspace(3)* %group.ptr, i64 %y, i32 0, i32 0, i1 false
define i64 @atomicdec_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 { define i64 @atomicdec_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 {
%cast = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(3)* %group.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 false) %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 false)
ret i64 %ret ret i64 %ret
} }
; CHECK-LABEL: @volatile_atomicinc_group_to_flat_i64( ; CHECK-LABEL: @volatile_atomicinc_group_to_flat_i64(
; CHECK-NEXT: %1 = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* ; CHECK-NEXT: %1 = addrspacecast i64 addrspace(3)* %group.ptr to i64*
; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %1, i64 %y, i32 0, i32 0, i1 true) ; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %1, i64 %y, i32 0, i32 0, i1 true)
define i64 @volatile_atomicinc_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 { define i64 @volatile_atomicinc_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 {
%cast = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(3)* %group.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 true) %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 true)
ret i64 %ret ret i64 %ret
} }
; CHECK-LABEL: @volatile_atomicdec_global_to_flat_i32( ; CHECK-LABEL: @volatile_atomicdec_global_to_flat_i32(
; CHECK-NEXT: %1 = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* ; CHECK-NEXT: %1 = addrspacecast i32 addrspace(1)* %global.ptr to i32*
; CHECK-NEXT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %1, i32 %val, i32 0, i32 0, i1 true) ; CHECK-NEXT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %1, i32 %val, i32 0, i32 0, i1 true)
define i32 @volatile_atomicdec_global_to_flat_i32(i32 addrspace(1)* %global.ptr, i32 %val) #0 { define i32 @volatile_atomicdec_global_to_flat_i32(i32 addrspace(1)* %global.ptr, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %global.ptr to i32*
%ret = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %cast, i32 %val, i32 0, i32 0, i1 true) %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 true)
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @volatile_atomicdec_group_to_flat_i32( ; CHECK-LABEL: @volatile_atomicdec_group_to_flat_i32(
; CHECK-NEXT: %1 = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* ; CHECK-NEXT: %1 = addrspacecast i32 addrspace(3)* %group.ptr to i32*
; CHECK-NEXT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %1, i32 %val, i32 0, i32 0, i1 true) ; CHECK-NEXT: %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %1, i32 %val, i32 0, i32 0, i1 true)
define i32 @volatile_atomicdec_group_to_flat_i32(i32 addrspace(3)* %group.ptr, i32 %val) #0 { define i32 @volatile_atomicdec_group_to_flat_i32(i32 addrspace(3)* %group.ptr, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* %group.ptr to i32*
%ret = call i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* %cast, i32 %val, i32 0, i32 0, i1 true) %ret = call i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* %cast, i32 %val, i32 0, i32 0, i1 true)
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @volatile_atomicdec_global_to_flat_i64( ; CHECK-LABEL: @volatile_atomicdec_global_to_flat_i64(
; CHECK-NEXT: %1 = addrspacecast i64 addrspace(1)* %global.ptr to i64 addrspace(4)* ; CHECK-NEXT: %1 = addrspacecast i64 addrspace(1)* %global.ptr to i64*
; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %1, i64 %y, i32 0, i32 0, i1 true) ; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %1, i64 %y, i32 0, i32 0, i1 true)
define i64 @volatile_atomicdec_global_to_flat_i64(i64 addrspace(1)* %global.ptr, i64 %y) #0 { define i64 @volatile_atomicdec_global_to_flat_i64(i64 addrspace(1)* %global.ptr, i64 %y) #0 {
%cast = addrspacecast i64 addrspace(1)* %global.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(1)* %global.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 true) %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 true)
ret i64 %ret ret i64 %ret
} }
; CHECK-LABEL: @volatile_atomicdec_group_to_flat_i64( ; CHECK-LABEL: @volatile_atomicdec_group_to_flat_i64(
; CHECK-NEXT: %1 = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* ; CHECK-NEXT: %1 = addrspacecast i64 addrspace(3)* %group.ptr to i64*
; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %1, i64 %y, i32 0, i32 0, i1 true) ; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %1, i64 %y, i32 0, i32 0, i1 true)
define i64 @volatile_atomicdec_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 { define i64 @volatile_atomicdec_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y) #0 {
%cast = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(3)* %group.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 true) %ret = call i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 true)
ret i64 %ret ret i64 %ret
} }
; CHECK-LABEL: @invalid_variable_volatile_atomicinc_group_to_flat_i64( ; CHECK-LABEL: @invalid_variable_volatile_atomicinc_group_to_flat_i64(
; CHECK-NEXT: %1 = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* ; CHECK-NEXT: %1 = addrspacecast i64 addrspace(3)* %group.ptr to i64*
; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %1, i64 %y, i32 0, i32 0, i1 %volatile.var) ; CHECK-NEXT: %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %1, i64 %y, i32 0, i32 0, i1 %volatile.var)
define i64 @invalid_variable_volatile_atomicinc_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y, i1 %volatile.var) #0 { define i64 @invalid_variable_volatile_atomicinc_group_to_flat_i64(i64 addrspace(3)* %group.ptr, i64 %y, i1 %volatile.var) #0 {
%cast = addrspacecast i64 addrspace(3)* %group.ptr to i64 addrspace(4)* %cast = addrspacecast i64 addrspace(3)* %group.ptr to i64*
%ret = call i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* %cast, i64 %y, i32 0, i32 0, i1 %volatile.var) %ret = call i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* %cast, i64 %y, i32 0, i32 0, i1 %volatile.var)
ret i64 %ret ret i64 %ret
} }
declare i32 @llvm.objectsize.i32.p4i8(i8 addrspace(4)*, i1, i1) #1 declare i32 @llvm.objectsize.i32.p0i8(i8*, i1, i1) #1
declare i64 @llvm.objectsize.i64.p4i8(i8 addrspace(4)*, i1, i1) #1 declare i64 @llvm.objectsize.i64.p0i8(i8*, i1, i1) #1
declare i32 @llvm.amdgcn.atomic.inc.i32.p4i32(i32 addrspace(4)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.inc.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.inc.i64.p4i64(i64 addrspace(4)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.inc.i64.p0i64(i64* nocapture, i64, i32, i32, i1) #2
declare i32 @llvm.amdgcn.atomic.dec.i32.p4i32(i32 addrspace(4)* nocapture, i32, i32, i32, i1) #2 declare i32 @llvm.amdgcn.atomic.dec.i32.p0i32(i32* nocapture, i32, i32, i32, i1) #2
declare i64 @llvm.amdgcn.atomic.dec.i64.p4i64(i64 addrspace(4)* nocapture, i64, i32, i32, i1) #2 declare i64 @llvm.amdgcn.atomic.dec.i64.p0i64(i64* nocapture, i64, i32, i32, i1) #2
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }
attributes #2 = { nounwind argmemonly } attributes #2 = { nounwind argmemonly }

test/Transforms/InferAddressSpaces/AMDGPU/mem-intrinsics.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; CHECK-LABEL: @memset_group_to_flat( ; CHECK-LABEL: @memset_group_to_flat(
; CHECK: call void @llvm.memset.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memset.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memset_group_to_flat(i8 addrspace(3)* %group.ptr, i32 %y) #0 { define amdgpu_kernel void @memset_group_to_flat(i8 addrspace(3)* %group.ptr, i32 %y) #0 {
%cast = addrspacecast i8 addrspace(3)* %group.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memset_global_to_flat( ; CHECK-LABEL: @memset_global_to_flat(
; CHECK: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* align 4 %global.ptr, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* align 4 %global.ptr, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memset_global_to_flat(i8 addrspace(1)* %global.ptr, i32 %y) #0 { define amdgpu_kernel void @memset_global_to_flat(i8 addrspace(1)* %global.ptr, i32 %y) #0 {
%cast = addrspacecast i8 addrspace(1)* %global.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(1)* %global.ptr to i8*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memset_group_to_flat_no_md( ; CHECK-LABEL: @memset_group_to_flat_no_md(
; CHECK: call void @llvm.memset.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 4, i64 %size, i1 false){{$}} ; CHECK: call void @llvm.memset.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 4, i64 %size, i1 false){{$}}
define amdgpu_kernel void @memset_group_to_flat_no_md(i8 addrspace(3)* %group.ptr, i64 %size) #0 { define amdgpu_kernel void @memset_group_to_flat_no_md(i8 addrspace(3)* %group.ptr, i64 %size) #0 {
%cast = addrspacecast i8 addrspace(3)* %group.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %cast, i8 4, i64 %size, i1 false) call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 %size, i1 false)
ret void ret void
} }
; CHECK-LABEL: @memset_global_to_flat_no_md( ; CHECK-LABEL: @memset_global_to_flat_no_md(
; CHECK: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* align 4 %global.ptr, i8 4, i64 %size, i1 false){{$}} ; CHECK: call void @llvm.memset.p1i8.i64(i8 addrspace(1)* align 4 %global.ptr, i8 4, i64 %size, i1 false){{$}}
define amdgpu_kernel void @memset_global_to_flat_no_md(i8 addrspace(1)* %global.ptr, i64 %size) #0 { define amdgpu_kernel void @memset_global_to_flat_no_md(i8 addrspace(1)* %global.ptr, i64 %size) #0 {
%cast = addrspacecast i8 addrspace(1)* %global.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(1)* %global.ptr to i8*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %cast, i8 4, i64 %size, i1 false) call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 %size, i1 false)
ret void ret void
} }
; CHECK-LABEL: @memcpy_flat_to_flat_replace_src_with_group( ; CHECK-LABEL: @memcpy_flat_to_flat_replace_src_with_group(
; CHCK: call void @llvm.memcpy.p4i8.p3i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHCK: call void @llvm.memcpy.p0i8.p3i8.i64(i8* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memcpy_flat_to_flat_replace_src_with_group(i8 addrspace(4)* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 { define amdgpu_kernel void @memcpy_flat_to_flat_replace_src_with_group(i8* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 {
%cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8 addrspace(4)* %cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %dest, i8* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memcpy_flat_to_flat_replace_dest_with_group( ; CHECK-LABEL: @memcpy_flat_to_flat_replace_dest_with_group(
; CHECK: call void @llvm.memcpy.p3i8.p4i8.i64(i8 addrspace(3)* align 4 %dest.group.ptr, i8 addrspace(4)* align 4 %src.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memcpy.p3i8.p0i8.i64(i8 addrspace(3)* align 4 %dest.group.ptr, i8* align 4 %src.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memcpy_flat_to_flat_replace_dest_with_group(i8 addrspace(3)* %dest.group.ptr, i8 addrspace(4)* %src.ptr, i64 %size) #0 { define amdgpu_kernel void @memcpy_flat_to_flat_replace_dest_with_group(i8 addrspace(3)* %dest.group.ptr, i8* %src.ptr, i64 %size) #0 {
%cast.dest = addrspacecast i8 addrspace(3)* %dest.group.ptr to i8 addrspace(4)* %cast.dest = addrspacecast i8 addrspace(3)* %dest.group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %cast.dest, i8 addrspace(4)* align 4 %src.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %cast.dest, i8* align 4 %src.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memcpy_flat_to_flat_replace_dest_src_with_group( ; CHECK-LABEL: @memcpy_flat_to_flat_replace_dest_src_with_group(
; CHECK: call void @llvm.memcpy.p3i8.p3i8.i64(i8 addrspace(3)* align 4 %src.group.ptr, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memcpy.p3i8.p3i8.i64(i8 addrspace(3)* align 4 %src.group.ptr, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memcpy_flat_to_flat_replace_dest_src_with_group(i8 addrspace(3)* %dest.group.ptr, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 { define amdgpu_kernel void @memcpy_flat_to_flat_replace_dest_src_with_group(i8 addrspace(3)* %dest.group.ptr, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 {
%cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8 addrspace(4)* %cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8*
%cast.dest = addrspacecast i8 addrspace(3)* %src.group.ptr to i8 addrspace(4)* %cast.dest = addrspacecast i8 addrspace(3)* %src.group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %cast.dest, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %cast.dest, i8* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memcpy_flat_to_flat_replace_dest_group_src_global( ; CHECK-LABEL: @memcpy_flat_to_flat_replace_dest_group_src_global(
; CHECK: call void @llvm.memcpy.p3i8.p1i8.i64(i8 addrspace(3)* align 4 %dest.group.ptr, i8 addrspace(1)* align 4 %src.global.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memcpy.p3i8.p1i8.i64(i8 addrspace(3)* align 4 %dest.group.ptr, i8 addrspace(1)* align 4 %src.global.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memcpy_flat_to_flat_replace_dest_group_src_global(i8 addrspace(3)* %dest.group.ptr, i8 addrspace(1)* %src.global.ptr, i64 %size) #0 { define amdgpu_kernel void @memcpy_flat_to_flat_replace_dest_group_src_global(i8 addrspace(3)* %dest.group.ptr, i8 addrspace(1)* %src.global.ptr, i64 %size) #0 {
%cast.src = addrspacecast i8 addrspace(1)* %src.global.ptr to i8 addrspace(4)* %cast.src = addrspacecast i8 addrspace(1)* %src.global.ptr to i8*
%cast.dest = addrspacecast i8 addrspace(3)* %dest.group.ptr to i8 addrspace(4)* %cast.dest = addrspacecast i8 addrspace(3)* %dest.group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %cast.dest, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %cast.dest, i8* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memcpy_group_to_flat_replace_dest_global( ; CHECK-LABEL: @memcpy_group_to_flat_replace_dest_global(
; CHECK: call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* align 4 %dest.global.ptr, i8 addrspace(3)* align 4 %src.group.ptr, i32 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memcpy.p1i8.p3i8.i32(i8 addrspace(1)* align 4 %dest.global.ptr, i8 addrspace(3)* align 4 %src.group.ptr, i32 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memcpy_group_to_flat_replace_dest_global(i8 addrspace(1)* %dest.global.ptr, i8 addrspace(3)* %src.group.ptr, i32 %size) #0 { define amdgpu_kernel void @memcpy_group_to_flat_replace_dest_global(i8 addrspace(1)* %dest.global.ptr, i8 addrspace(3)* %src.group.ptr, i32 %size) #0 {
%cast.dest = addrspacecast i8 addrspace(1)* %dest.global.ptr to i8 addrspace(4)* %cast.dest = addrspacecast i8 addrspace(1)* %dest.global.ptr to i8*
call void @llvm.memcpy.p4i8.p3i8.i32(i8 addrspace(4)* align 4 %cast.dest, i8 addrspace(3)* align 4 %src.group.ptr, i32 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memcpy.p0i8.p3i8.i32(i8* align 4 %cast.dest, i8 addrspace(3)* align 4 %src.group.ptr, i32 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memcpy_flat_to_flat_replace_src_with_group_tbaa_struct( ; CHECK-LABEL: @memcpy_flat_to_flat_replace_src_with_group_tbaa_struct(
; CHECK: call void @llvm.memcpy.p4i8.p3i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa.struct !7 ; CHECK: call void @llvm.memcpy.p0i8.p3i8.i64(i8* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa.struct !7
define amdgpu_kernel void @memcpy_flat_to_flat_replace_src_with_group_tbaa_struct(i8 addrspace(4)* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 { define amdgpu_kernel void @memcpy_flat_to_flat_replace_src_with_group_tbaa_struct(i8* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 {
%cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8 addrspace(4)* %cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false), !tbaa.struct !7 call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %dest, i8* align 4 %cast.src, i64 %size, i1 false), !tbaa.struct !7
ret void ret void
} }
; CHECK-LABEL: @memcpy_flat_to_flat_replace_src_with_group_no_md( ; CHECK-LABEL: @memcpy_flat_to_flat_replace_src_with_group_no_md(
; CHECK: call void @llvm.memcpy.p4i8.p3i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false){{$}} ; CHECK: call void @llvm.memcpy.p0i8.p3i8.i64(i8* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false){{$}}
define amdgpu_kernel void @memcpy_flat_to_flat_replace_src_with_group_no_md(i8 addrspace(4)* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 { define amdgpu_kernel void @memcpy_flat_to_flat_replace_src_with_group_no_md(i8* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 {
%cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8 addrspace(4)* %cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false) call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %dest, i8* align 4 %cast.src, i64 %size, i1 false)
ret void ret void
} }
; CHECK-LABEL: @multiple_memcpy_flat_to_flat_replace_src_with_group_no_md( ; CHECK-LABEL: @multiple_memcpy_flat_to_flat_replace_src_with_group_no_md(
; CHECK: call void @llvm.memcpy.p4i8.p3i8.i64(i8 addrspace(4)* align 4 %dest0, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false){{$}} ; CHECK: call void @llvm.memcpy.p0i8.p3i8.i64(i8* align 4 %dest0, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false){{$}}
; CHECK: call void @llvm.memcpy.p4i8.p3i8.i64(i8 addrspace(4)* align 4 %dest1, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false){{$}} ; CHECK: call void @llvm.memcpy.p0i8.p3i8.i64(i8* align 4 %dest1, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false){{$}}
define amdgpu_kernel void @multiple_memcpy_flat_to_flat_replace_src_with_group_no_md(i8 addrspace(4)* %dest0, i8 addrspace(4)* %dest1, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 { define amdgpu_kernel void @multiple_memcpy_flat_to_flat_replace_src_with_group_no_md(i8* %dest0, i8* %dest1, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 {
%cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8 addrspace(4)* %cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %dest0, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false) call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %dest0, i8* align 4 %cast.src, i64 %size, i1 false)
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %dest1, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false) call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %dest1, i8* align 4 %cast.src, i64 %size, i1 false)
ret void ret void
} }
; Check for iterator problems if the pointer has 2 uses in the same call ; Check for iterator problems if the pointer has 2 uses in the same call
; CHECK-LABEL: @memcpy_group_flat_to_flat_self( ; CHECK-LABEL: @memcpy_group_flat_to_flat_self(
; CHECK: call void @llvm.memcpy.p3i8.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 addrspace(3)* align 4 %group.ptr, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memcpy.p3i8.p3i8.i64(i8 addrspace(3)* align 4 %group.ptr, i8 addrspace(3)* align 4 %group.ptr, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memcpy_group_flat_to_flat_self(i8 addrspace(3)* %group.ptr) #0 { define amdgpu_kernel void @memcpy_group_flat_to_flat_self(i8 addrspace(3)* %group.ptr) #0 {
%cast = addrspacecast i8 addrspace(3)* %group.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
call void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %cast, i8 addrspace(4)* align 4 %cast, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memcpy.p4i8.p0i8.i64(i8* align 4 %cast, i8* align 4 %cast, i64 32, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
; CHECK-LABEL: @memmove_flat_to_flat_replace_src_with_group( ; CHECK-LABEL: @memmove_flat_to_flat_replace_src_with_group(
; CHECK: call void @llvm.memmove.p4i8.p3i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 ; CHECK: call void @llvm.memmove.p0i8.p3i8.i64(i8* align 4 %dest, i8 addrspace(3)* align 4 %src.group.ptr, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
define amdgpu_kernel void @memmove_flat_to_flat_replace_src_with_group(i8 addrspace(4)* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 { define amdgpu_kernel void @memmove_flat_to_flat_replace_src_with_group(i8* %dest, i8 addrspace(3)* %src.group.ptr, i64 %size) #0 {
%cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8 addrspace(4)* %cast.src = addrspacecast i8 addrspace(3)* %src.group.ptr to i8*
call void @llvm.memmove.p4i8.p4i8.i64(i8 addrspace(4)* align 4 %dest, i8 addrspace(4)* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4 call void @llvm.memmove.p4i8.p0i8.i64(i8* align 4 %dest, i8* align 4 %cast.src, i64 %size, i1 false), !tbaa !0, !alias.scope !3, !noalias !4
ret void ret void
} }
declare void @llvm.memset.p4i8.i64(i8 addrspace(4)* nocapture writeonly, i8, i64, i1) #1 declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) #1
declare void @llvm.memcpy.p4i8.p4i8.i64(i8 addrspace(4)* nocapture writeonly, i8 addrspace(4)* nocapture readonly, i64, i1) #1 declare void @llvm.memcpy.p4i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1
declare void @llvm.memcpy.p4i8.p3i8.i32(i8 addrspace(4)* nocapture writeonly, i8 addrspace(3)* nocapture readonly, i32, i1) #1 declare void @llvm.memcpy.p0i8.p3i8.i32(i8* nocapture writeonly, i8 addrspace(3)* nocapture readonly, i32, i1) #1
declare void @llvm.memmove.p4i8.p4i8.i64(i8 addrspace(4)* nocapture writeonly, i8 addrspace(4)* nocapture readonly, i64, i1) #1 declare void @llvm.memmove.p4i8.p0i8.i64(i8* nocapture writeonly, i8* nocapture readonly, i64, i1) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }
!0 = !{!1, !1, i64 0} !0 = !{!1, !1, i64 0}
!1 = !{!"A", !2} !1 = !{!"A", !2}
!2 = !{!"tbaa root"} !2 = !{!"tbaa root"}
!3 = !{!"B", !2} !3 = !{!"B", !2}
!4 = !{!5} !4 = !{!5}
!5 = distinct !{!5, !6, !"some scope"} !5 = distinct !{!5, !6, !"some scope"}
!6 = distinct !{!6, !"some domain"} !6 = distinct !{!6, !"some domain"}
!7 = !{i64 0, i64 8, null} !7 = !{i64 0, i64 8, null}

test/Transforms/InferAddressSpaces/AMDGPU/old-pass-regressions.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -data-layout=A5 -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; Regression tests from old HSAIL addrspacecast optimization pass ; Regression tests from old HSAIL addrspacecast optimization pass
@data = internal addrspace(1) global [100 x double] [double 0.00, double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 7.000000e-01, double 8.000000e-01, double 9.000000e-01, double 1.00, double 1.10, double 1.20, double 1.30, double 1.40, double 1.50, double 1.60, double 1.70, double 1.80, double 1.90, double 2.00, double 2.10, double 2.20, double 2.30, double 2.40, double 2.50, double 2.60, double 2.70, double 2.80, double 2.90, double 3.00, double 3.10, double 3.20, double 3.30, double 3.40, double 3.50, double 3.60, double 3.70, double 3.80, double 3.90, double 4.00, double 4.10, double 4.20, double 4.30, double 4.40, double 4.50, double 4.60, double 4.70, double 4.80, double 4.90, double 5.00, double 5.10, double 5.20, double 5.30, double 5.40, double 5.50, double 5.60, double 5.70, double 5.80, double 5.90, double 6.00, double 6.10, double 6.20, double 6.30, double 6.40, double 6.50, double 6.60, double 6.70, double 6.80, double 6.90, double 7.00, double 7.10, double 7.20, double 7.30, double 7.40, double 7.50, double 7.60, double 7.70, double 7.80, double 7.90, double 8.00, double 8.10, double 8.20, double 8.30, double 8.40, double 8.50, double 8.60, double 8.70, double 8.80, double 8.90, double 9.00, double 9.10, double 9.20, double 9.30, double 9.40, double 9.50, double 9.60, double 9.70, double 9.80, double 9.90], align 8 @data = internal addrspace(1) global [100 x double] [double 0.00, double 1.000000e-01, double 2.000000e-01, double 3.000000e-01, double 4.000000e-01, double 5.000000e-01, double 6.000000e-01, double 7.000000e-01, double 8.000000e-01, double 9.000000e-01, double 1.00, double 1.10, double 1.20, double 1.30, double 1.40, double 1.50, double 1.60, double 1.70, double 1.80, double 1.90, double 2.00, double 2.10, double 2.20, double 2.30, double 2.40, double 2.50, double 2.60, double 2.70, double 2.80, double 2.90, double 3.00, double 3.10, double 3.20, double 3.30, double 3.40, double 3.50, double 3.60, double 3.70, double 3.80, double 3.90, double 4.00, double 4.10, double 4.20, double 4.30, double 4.40, double 4.50, double 4.60, double 4.70, double 4.80, double 4.90, double 5.00, double 5.10, double 5.20, double 5.30, double 5.40, double 5.50, double 5.60, double 5.70, double 5.80, double 5.90, double 6.00, double 6.10, double 6.20, double 6.30, double 6.40, double 6.50, double 6.60, double 6.70, double 6.80, double 6.90, double 7.00, double 7.10, double 7.20, double 7.30, double 7.40, double 7.50, double 7.60, double 7.70, double 7.80, double 7.90, double 8.00, double 8.10, double 8.20, double 8.30, double 8.40, double 8.50, double 8.60, double 8.70, double 8.80, double 8.90, double 9.00, double 9.10, double 9.20, double 9.30, double 9.40, double 9.50, double 9.60, double 9.70, double 9.80, double 9.90], align 8
; Should generate flat load ; Should generate flat load
; CHECK-LABEL: @generic_address_bitcast_const( ; CHECK-LABEL: @generic_address_bitcast_const(
; CHECK: %vecload1 = load <2 x double>, <2 x double> addrspace(1)* bitcast (double addrspace(1)* getelementptr inbounds ([100 x double], [100 x double] addrspace(1)* @data, i64 0, i64 4) to <2 x double> addrspace(1)*), align 8 ; CHECK: %vecload1 = load <2 x double>, <2 x double> addrspace(1)* bitcast (double addrspace(1)* getelementptr inbounds ([100 x double], [100 x double] addrspace(1)* @data, i64 0, i64 4) to <2 x double> addrspace(1)*), align 8
define amdgpu_kernel void @generic_address_bitcast_const(i64 %arg0, i32 addrspace(1)* nocapture %results) #0 { define amdgpu_kernel void @generic_address_bitcast_const(i64 %arg0, i32 addrspace(1)* nocapture %results) #0 {
entry: entry:
%tmp1 = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = zext i32 %tmp1 to i64 %tmp2 = zext i32 %tmp1 to i64
%tmp3 = add i64 %tmp2, %arg0 %tmp3 = add i64 %tmp2, %arg0
%vecload1 = load <2 x double>, <2 x double> addrspace(4)* bitcast (double addrspace(4)* getelementptr ([100 x double], [100 x double] addrspace(4)* addrspacecast ([100 x double] addrspace(1)* @data to [100 x double] addrspace(4)*), i64 0, i64 4) to <2 x double> addrspace(4)*), align 8 %vecload1 = load <2 x double>, <2 x double>* bitcast (double* getelementptr ([100 x double], [100 x double]* addrspacecast ([100 x double] addrspace(1)* @data to [100 x double]*), i64 0, i64 4) to <2 x double>*), align 8
%cmp = fcmp ord <2 x double> %vecload1, zeroinitializer %cmp = fcmp ord <2 x double> %vecload1, zeroinitializer
%sext = sext <2 x i1> %cmp to <2 x i64> %sext = sext <2 x i1> %cmp to <2 x i64>
%tmp4 = extractelement <2 x i64> %sext, i64 0 %tmp4 = extractelement <2 x i64> %sext, i64 0
%tmp5 = extractelement <2 x i64> %sext, i64 1 %tmp5 = extractelement <2 x i64> %sext, i64 1
%tmp6 = and i64 %tmp4, %tmp5 %tmp6 = and i64 %tmp4, %tmp5
%tmp7 = lshr i64 %tmp6, 63 %tmp7 = lshr i64 %tmp6, 63
%tmp8 = trunc i64 %tmp7 to i32 %tmp8 = trunc i64 %tmp7 to i32
%idxprom = and i64 %tmp3, 4294967295 %idxprom = and i64 %tmp3, 4294967295
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %results, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %results, i64 %idxprom
store i32 %tmp8, i32 addrspace(1)* %arrayidx, align 4 store i32 %tmp8, i32 addrspace(1)* %arrayidx, align 4
ret void ret void
} }
@generic_address_bug9749.val = internal addrspace(1) global float 0.0, align 4 @generic_address_bug9749.val = internal addrspace(1) global float 0.0, align 4
declare i32 @_Z9get_fencePU3AS4v(i8 addrspace(4)*) declare i32 @_Z9get_fencePv(i8*)
%opencl.pipe_t = type opaque %opencl.pipe_t = type opaque
; This is a compile time assert bug, but we still want to check optimization ; This is a compile time assert bug, but we still want to check optimization
; is performed to generate ld_global. ; is performed to generate ld_global.
; CHECK-LABEL: @generic_address_pipe_bug9673( ; CHECK-LABEL: @generic_address_pipe_bug9673(
; CHECK: %tmp1 = bitcast %opencl.pipe_t addrspace(3)* %in_pipe to i32 addrspace(3)* ; CHECK: %tmp1 = bitcast %opencl.pipe_t addrspace(3)* %in_pipe to i32 addrspace(3)*
; CHECK: %add.ptr = getelementptr inbounds i32, i32 addrspace(3)* %tmp1, i32 2 ; CHECK: %add.ptr = getelementptr inbounds i32, i32 addrspace(3)* %tmp1, i32 2
; CHECK: %tmp2 = load i32, i32 addrspace(3)* %add.ptr, align 4 ; CHECK: %tmp2 = load i32, i32 addrspace(3)* %add.ptr, align 4
define amdgpu_kernel void @generic_address_pipe_bug9673(%opencl.pipe_t addrspace(3)* nocapture %in_pipe, i32 addrspace(1)* nocapture %dst) #0 { define amdgpu_kernel void @generic_address_pipe_bug9673(%opencl.pipe_t addrspace(3)* nocapture %in_pipe, i32 addrspace(1)* nocapture %dst) #0 {
entry: entry:
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = bitcast %opencl.pipe_t addrspace(3)* %in_pipe to i32 addrspace(3)* %tmp1 = bitcast %opencl.pipe_t addrspace(3)* %in_pipe to i32 addrspace(3)*
%add.ptr = getelementptr inbounds i32, i32 addrspace(3)* %tmp1, i32 2 %add.ptr = getelementptr inbounds i32, i32 addrspace(3)* %tmp1, i32 2
%tmp2 = load i32, i32 addrspace(3)* %add.ptr, align 4 %tmp2 = load i32, i32 addrspace(3)* %add.ptr, align 4
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %dst, i32 %tmp %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %dst, i32 %tmp
store i32 %tmp2, i32 addrspace(1)* %arrayidx, align 4 store i32 %tmp2, i32 addrspace(1)* %arrayidx, align 4
ret void ret void
} }
; Should generate flat load ; Should generate flat load
; CHECK-LABEL: @generic_address_bug9749( ; CHECK-LABEL: @generic_address_bug9749(
; CHECK: br i1 ; CHECK: br i1
; CHECK: load float, float addrspace(4)* ; CHECK: load float, float*
; CHECK: br label ; CHECK: br label
define amdgpu_kernel void @generic_address_bug9749(i32 addrspace(1)* nocapture %results) #0 { define amdgpu_kernel void @generic_address_bug9749(i32 addrspace(1)* nocapture %results) #0 {
entry: entry:
%ptr = alloca float addrspace(4)*, align 8 %ptr = alloca float*, align 8, addrspace(5)
%tmp = call i32 @llvm.amdgcn.workitem.id.x() %tmp = call i32 @llvm.amdgcn.workitem.id.x()
%tmp1 = zext i32 %tmp to i64 %tmp1 = zext i32 %tmp to i64
store float 0x3FB99999A0000000, float addrspace(1)* @generic_address_bug9749.val, align 4 store float 0x3FB99999A0000000, float addrspace(1)* @generic_address_bug9749.val, align 4
store volatile float addrspace(4)* addrspacecast (float addrspace(1)* @generic_address_bug9749.val to float addrspace(4)*), float addrspace(4)** %ptr, align 8 store volatile float* addrspacecast (float addrspace(1)* @generic_address_bug9749.val to float*), float* addrspace(5)* %ptr, align 8
%tmp2 = load volatile float addrspace(4)*, float addrspace(4)** %ptr, align 8 %tmp2 = load volatile float*, float* addrspace(5)* %ptr, align 8
%tmp3 = load float, float addrspace(1)* @generic_address_bug9749.val, align 4 %tmp3 = load float, float addrspace(1)* @generic_address_bug9749.val, align 4
%tmp4 = bitcast float addrspace(4)* %tmp2 to i8 addrspace(4)* %tmp4 = bitcast float* %tmp2 to i8*
%call.i = call i32 @_Z9get_fencePU3AS4v(i8 addrspace(4)* %tmp4) #1 %call.i = call i32 @_Z9get_fencePv(i8* %tmp4) #1
%switch.i.i = icmp ult i32 %call.i, 4 %switch.i.i = icmp ult i32 %call.i, 4
br i1 %switch.i.i, label %if.end.i, label %helperFunction.exit br i1 %switch.i.i, label %if.end.i, label %helperFunction.exit
if.end.i: ; preds = %entry if.end.i: ; preds = %entry
%tmp5 = load float, float addrspace(4)* %tmp2, align 4 %tmp5 = load float, float* %tmp2, align 4
%not.cmp.i = fcmp oeq float %tmp5, %tmp3 %not.cmp.i = fcmp oeq float %tmp5, %tmp3
%phitmp = zext i1 %not.cmp.i to i32 %phitmp = zext i1 %not.cmp.i to i32
br label %helperFunction.exit br label %helperFunction.exit
helperFunction.exit: ; preds = %if.end.i, %entry helperFunction.exit: ; preds = %if.end.i, %entry
%retval.0.i = phi i32 [ 0, %entry ], [ %phitmp, %if.end.i ] %retval.0.i = phi i32 [ 0, %entry ], [ %phitmp, %if.end.i ]
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %results, i64 %tmp1 %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %results, i64 %tmp1
store i32 %retval.0.i, i32 addrspace(1)* %arrayidx, align 4 store i32 %retval.0.i, i32 addrspace(1)* %arrayidx, align 4
ret void ret void
} }
; CHECK-LABEL: @generic_address_opt_phi_bug9776_simple_phi_kernel( ; CHECK-LABEL: @generic_address_opt_phi_bug9776_simple_phi_kernel(
; CHECK: phi i32 addrspace(3)* ; CHECK: phi i32 addrspace(3)*
; CHECK: store i32 %i.03, i32 addrspace(3)* % ; CHECK: store i32 %i.03, i32 addrspace(3)* %
define amdgpu_kernel void @generic_address_opt_phi_bug9776_simple_phi_kernel(i32 addrspace(3)* nocapture %in, i32 %numElems) #0 { define amdgpu_kernel void @generic_address_opt_phi_bug9776_simple_phi_kernel(i32 addrspace(3)* nocapture %in, i32 %numElems) #0 {
entry: entry:
%cmp1 = icmp eq i32 %numElems, 0 %cmp1 = icmp eq i32 %numElems, 0
br i1 %cmp1, label %for.end, label %for.body.lr.ph br i1 %cmp1, label %for.end, label %for.body.lr.ph
for.body.lr.ph: ; preds = %entry for.body.lr.ph: ; preds = %entry
%tmp = addrspacecast i32 addrspace(3)* %in to i32 addrspace(4)* %tmp = addrspacecast i32 addrspace(3)* %in to i32*
br label %for.body br label %for.body
for.body: ; preds = %for.body, %for.body.lr.ph for.body: ; preds = %for.body, %for.body.lr.ph
%i.03 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ] %i.03 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
%ptr.02 = phi i32 addrspace(4)* [ %tmp, %for.body.lr.ph ], [ %add.ptr, %for.body ] %ptr.02 = phi i32* [ %tmp, %for.body.lr.ph ], [ %add.ptr, %for.body ]
store i32 %i.03, i32 addrspace(4)* %ptr.02, align 4 store i32 %i.03, i32* %ptr.02, align 4
%add.ptr = getelementptr inbounds i32, i32 addrspace(4)* %ptr.02, i64 4 %add.ptr = getelementptr inbounds i32, i32* %ptr.02, i64 4
%inc = add nuw i32 %i.03, 1 %inc = add nuw i32 %i.03, 1
%exitcond = icmp eq i32 %inc, %numElems %exitcond = icmp eq i32 %inc, %numElems
br i1 %exitcond, label %for.end, label %for.body br i1 %exitcond, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
; CHECK-LABEL: @generic_address_bug9899( ; CHECK-LABEL: @generic_address_bug9899(
; CHECK: %vecload = load <2 x i32>, <2 x i32> addrspace(3)* ; CHECK: %vecload = load <2 x i32>, <2 x i32> addrspace(3)*
; CHECK: store <2 x i32> %tmp16, <2 x i32> addrspace(3)* ; CHECK: store <2 x i32> %tmp16, <2 x i32> addrspace(3)*
define amdgpu_kernel void @generic_address_bug9899(i64 %arg0, i32 addrspace(3)* nocapture %sourceA, i32 addrspace(3)* nocapture %destValues) #0 { define amdgpu_kernel void @generic_address_bug9899(i64 %arg0, i32 addrspace(3)* nocapture %sourceA, i32 addrspace(3)* nocapture %destValues) #0 {
entry: entry:
%tmp1 = call i32 @llvm.amdgcn.workitem.id.x() %tmp1 = call i32 @llvm.amdgcn.workitem.id.x()
%tmp2 = zext i32 %tmp1 to i64 %tmp2 = zext i32 %tmp1 to i64
%tmp3 = add i64 %tmp2, %arg0 %tmp3 = add i64 %tmp2, %arg0
%sext = shl i64 %tmp3, 32 %sext = shl i64 %tmp3, 32
%tmp4 = addrspacecast i32 addrspace(3)* %destValues to i32 addrspace(4)* %tmp4 = addrspacecast i32 addrspace(3)* %destValues to i32*
%tmp5 = addrspacecast i32 addrspace(3)* %sourceA to i32 addrspace(4)* %tmp5 = addrspacecast i32 addrspace(3)* %sourceA to i32*
%tmp6 = ashr exact i64 %sext, 31 %tmp6 = ashr exact i64 %sext, 31
%tmp7 = getelementptr inbounds i32, i32 addrspace(4)* %tmp5, i64 %tmp6 %tmp7 = getelementptr inbounds i32, i32* %tmp5, i64 %tmp6
%arrayidx_v4 = bitcast i32 addrspace(4)* %tmp7 to <2 x i32> addrspace(4)* %arrayidx_v4 = bitcast i32* %tmp7 to <2 x i32>*
%vecload = load <2 x i32>, <2 x i32> addrspace(4)* %arrayidx_v4, align 4 %vecload = load <2 x i32>, <2 x i32>* %arrayidx_v4, align 4
%tmp8 = extractelement <2 x i32> %vecload, i32 0 %tmp8 = extractelement <2 x i32> %vecload, i32 0
%tmp9 = extractelement <2 x i32> %vecload, i32 1 %tmp9 = extractelement <2 x i32> %vecload, i32 1
%tmp10 = icmp eq i32 %tmp8, 0 %tmp10 = icmp eq i32 %tmp8, 0
%tmp11 = select i1 %tmp10, i32 32, i32 %tmp8 %tmp11 = select i1 %tmp10, i32 32, i32 %tmp8
%tmp12 = icmp eq i32 %tmp9, 0 %tmp12 = icmp eq i32 %tmp9, 0
%tmp13 = select i1 %tmp12, i32 32, i32 %tmp9 %tmp13 = select i1 %tmp12, i32 32, i32 %tmp9
%tmp14 = getelementptr inbounds i32, i32 addrspace(4)* %tmp4, i64 %tmp6 %tmp14 = getelementptr inbounds i32, i32* %tmp4, i64 %tmp6
%tmp15 = insertelement <2 x i32> undef, i32 %tmp11, i32 0 %tmp15 = insertelement <2 x i32> undef, i32 %tmp11, i32 0
%tmp16 = insertelement <2 x i32> %tmp15, i32 %tmp13, i32 1 %tmp16 = insertelement <2 x i32> %tmp15, i32 %tmp13, i32 1
%arrayidx_v41 = bitcast i32 addrspace(4)* %tmp14 to <2 x i32> addrspace(4)* %arrayidx_v41 = bitcast i32* %tmp14 to <2 x i32>*
store <2 x i32> %tmp16, <2 x i32> addrspace(4)* %arrayidx_v41, align 4 store <2 x i32> %tmp16, <2 x i32>* %arrayidx_v41, align 4
ret void ret void
} }
declare i32 @llvm.amdgcn.workitem.id.x() #2 declare i32 @llvm.amdgcn.workitem.id.x() #2
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { nounwind readonly } attributes #1 = { nounwind readonly }
attributes #2 = { nounwind readnone } attributes #2 = { nounwind readnone }
No newline at end of file

test/Transforms/InferAddressSpaces/AMDGPU/select.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; Instcombine pulls the addrspacecast out of the select, make sure ; Instcombine pulls the addrspacecast out of the select, make sure
; this doesn't do something insane on non-canonical IR. ; this doesn't do something insane on non-canonical IR.
; CHECK-LABEL: @return_select_group_flat( ; CHECK-LABEL: @return_select_group_flat(
; CHECK-NEXT: %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK-NEXT: %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK-NEXT: %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* ; CHECK-NEXT: %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
; CHECK-NEXT: %select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* %cast1 ; CHECK-NEXT: %select = select i1 %c, i32* %cast0, i32* %cast1
; CHECK-NEXT: ret i32 addrspace(4)* %select ; CHECK-NEXT: ret i32* %select
define i32 addrspace(4)* @return_select_group_flat(i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 { define i32* @return_select_group_flat(i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* %cast1 %select = select i1 %c, i32* %cast0, i32* %cast1
ret i32 addrspace(4)* %select ret i32* %select
} }
; CHECK-LABEL: @store_select_group_flat( ; CHECK-LABEL: @store_select_group_flat(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1 ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1
; CHECK: store i32 -1, i32 addrspace(3)* %select ; CHECK: store i32 -1, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat(i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 { define amdgpu_kernel void @store_select_group_flat(i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* %cast1 %select = select i1 %c, i32* %cast0, i32* %cast1
store i32 -1, i32 addrspace(4)* %select store i32 -1, i32* %select
ret void ret void
} }
; Make sure metadata is preserved ; Make sure metadata is preserved
; CHECK-LABEL: @load_select_group_flat_md( ; CHECK-LABEL: @load_select_group_flat_md(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1, !prof !0 ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1, !prof !0
; CHECK: %load = load i32, i32 addrspace(3)* %select ; CHECK: %load = load i32, i32 addrspace(3)* %select
define i32 @load_select_group_flat_md(i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 { define i32 @load_select_group_flat_md(i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* %group.ptr.1) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32 addrspace(4)* %cast1 = addrspacecast i32 addrspace(3)* %group.ptr.1 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* %cast1, !prof !0 %select = select i1 %c, i32* %cast0, i32* %cast1, !prof !0
%load = load i32, i32 addrspace(4)* %select %load = load i32, i32* %select
ret i32 %load ret i32 %load
} }
; CHECK-LABEL: @store_select_mismatch_group_private_flat( ; CHECK-LABEL: @store_select_mismatch_group_private_flat(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %2 = addrspacecast i32* %private.ptr.1 to i32 addrspace(4)* ; CHECK: %2 = addrspacecast i32 addrspace(5)* %private.ptr.1 to i32*
; CHECK: %select = select i1 %c, i32 addrspace(4)* %1, i32 addrspace(4)* %2 ; CHECK: %select = select i1 %c, i32* %1, i32* %2
; CHECK: store i32 -1, i32 addrspace(4)* %select ; CHECK: store i32 -1, i32* %select
define amdgpu_kernel void @store_select_mismatch_group_private_flat(i1 %c, i32 addrspace(3)* %group.ptr.0, i32* %private.ptr.1) #0 { define amdgpu_kernel void @store_select_mismatch_group_private_flat(i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(5)* %private.ptr.1) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%cast1 = addrspacecast i32* %private.ptr.1 to i32 addrspace(4)* %cast1 = addrspacecast i32 addrspace(5)* %private.ptr.1 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* %cast1 %select = select i1 %c, i32* %cast0, i32* %cast1
store i32 -1, i32 addrspace(4)* %select store i32 -1, i32* %select
ret void ret void
} }
@lds0 = internal addrspace(3) global i32 123, align 4 @lds0 = internal addrspace(3) global i32 123, align 4
@lds1 = internal addrspace(3) global i32 456, align 4 @lds1 = internal addrspace(3) global i32 456, align 4
; CHECK-LABEL: @constexpr_select_group_flat( ; CHECK-LABEL: @constexpr_select_group_flat(
; CHECK: %tmp = load i32, i32 addrspace(3)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(3)* @lds0, i32 addrspace(3)* @lds1) ; CHECK: %tmp = load i32, i32 addrspace(3)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(3)* @lds0, i32 addrspace(3)* @lds1)
define i32 @constexpr_select_group_flat() #0 { define i32 @constexpr_select_group_flat() #0 {
bb: bb:
%tmp = load i32, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds0 to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds1 to i32 addrspace(4)*)) %tmp = load i32, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* @lds0 to i32*), i32* addrspacecast (i32 addrspace(3)* @lds1 to i32*))
ret i32 %tmp ret i32 %tmp
} }
; CHECK-LABEL: @constexpr_select_group_global_flat_mismatch( ; CHECK-LABEL: @constexpr_select_group_global_flat_mismatch(
; CHECK: %tmp = load i32, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds0 to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*)) ; CHECK: %tmp = load i32, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* @lds0 to i32*), i32* addrspacecast (i32 addrspace(1)* @global0 to i32*))
define i32 @constexpr_select_group_global_flat_mismatch() #0 { define i32 @constexpr_select_group_global_flat_mismatch() #0 {
bb: bb:
%tmp = load i32, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds0 to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*)) %tmp = load i32, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* @lds0 to i32*), i32* addrspacecast (i32 addrspace(1)* @global0 to i32*))
ret i32 %tmp ret i32 %tmp
} }
; CHECK-LABEL: @store_select_group_flat_null( ; CHECK-LABEL: @store_select_group_flat_null(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* addrspacecast (i32 addrspace(4)* null to i32 addrspace(3)*) ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*)
; CHECK: store i32 -1, i32 addrspace(3)* %select ; CHECK: store i32 -1, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat_null(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_flat_null(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* null %select = select i1 %c, i32* %cast0, i32* null
store i32 -1, i32 addrspace(4)* %select store i32 -1, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_flat_null_swap( ; CHECK-LABEL: @store_select_group_flat_null_swap(
; CHECK: %select = select i1 %c, i32 addrspace(3)* addrspacecast (i32 addrspace(4)* null to i32 addrspace(3)*), i32 addrspace(3)* %group.ptr.0 ; CHECK: %select = select i1 %c, i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*), i32 addrspace(3)* %group.ptr.0
; CHECK: store i32 -1, i32 addrspace(3)* %select ; CHECK: store i32 -1, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat_null_swap(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_flat_null_swap(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* null, i32 addrspace(4)* %cast0 %select = select i1 %c, i32* null, i32* %cast0
store i32 -1, i32 addrspace(4)* %select store i32 -1, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_flat_undef( ; CHECK-LABEL: @store_select_group_flat_undef(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* undef ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* undef
; CHECK: store i32 -1, i32 addrspace(3)* %select ; CHECK: store i32 -1, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat_undef(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_flat_undef(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* undef %select = select i1 %c, i32* %cast0, i32* undef
store i32 -1, i32 addrspace(4)* %select store i32 -1, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_flat_undef_swap( ; CHECK-LABEL: @store_select_group_flat_undef_swap(
; CHECK: %select = select i1 %c, i32 addrspace(3)* undef, i32 addrspace(3)* %group.ptr.0 ; CHECK: %select = select i1 %c, i32 addrspace(3)* undef, i32 addrspace(3)* %group.ptr.0
; CHECK: store i32 -1, i32 addrspace(3)* %select ; CHECK: store i32 -1, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat_undef_swap(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_flat_undef_swap(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* undef, i32 addrspace(4)* %cast0 %select = select i1 %c, i32* undef, i32* %cast0
store i32 -1, i32 addrspace(4)* %select store i32 -1, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_gep_group_flat_null( ; CHECK-LABEL: @store_select_gep_group_flat_null(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* addrspacecast (i32 addrspace(4)* null to i32 addrspace(3)*) ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* addrspacecast (i32* null to i32 addrspace(3)*)
; CHECK: %gep = getelementptr i32, i32 addrspace(3)* %select, i64 16 ; CHECK: %gep = getelementptr i32, i32 addrspace(3)* %select, i64 16
; CHECK: store i32 -1, i32 addrspace(3)* %gep ; CHECK: store i32 -1, i32 addrspace(3)* %gep
define amdgpu_kernel void @store_select_gep_group_flat_null(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_gep_group_flat_null(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* null %select = select i1 %c, i32* %cast0, i32* null
%gep = getelementptr i32, i32 addrspace(4)* %select, i64 16 %gep = getelementptr i32, i32* %select, i64 16
store i32 -1, i32 addrspace(4)* %gep store i32 -1, i32* %gep
ret void ret void
} }
@global0 = internal addrspace(1) global i32 123, align 4 @global0 = internal addrspace(1) global i32 123, align 4
; CHECK-LABEL: @store_select_group_flat_constexpr( ; CHECK-LABEL: @store_select_group_flat_constexpr(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* @lds1 ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* @lds1
; CHECK: store i32 7, i32 addrspace(3)* %select ; CHECK: store i32 7, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat_constexpr(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_flat_constexpr(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds1 to i32 addrspace(4)*) %select = select i1 %c, i32* %cast0, i32* addrspacecast (i32 addrspace(3)* @lds1 to i32*)
store i32 7, i32 addrspace(4)* %select store i32 7, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_flat_inttoptr_flat( ; CHECK-LABEL: @store_select_group_flat_inttoptr_flat(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* addrspacecast (i32 addrspace(4)* inttoptr (i64 12345 to i32 addrspace(4)*) to i32 addrspace(3)*) ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* addrspacecast (i32* inttoptr (i64 12345 to i32*) to i32 addrspace(3)*)
; CHECK: store i32 7, i32 addrspace(3)* %select ; CHECK: store i32 7, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat_inttoptr_flat(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_flat_inttoptr_flat(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* inttoptr (i64 12345 to i32 addrspace(4)*) %select = select i1 %c, i32* %cast0, i32* inttoptr (i64 12345 to i32*)
store i32 7, i32 addrspace(4)* %select store i32 7, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_flat_inttoptr_group( ; CHECK-LABEL: @store_select_group_flat_inttoptr_group(
; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* inttoptr (i32 400 to i32 addrspace(3)*) ; CHECK: %select = select i1 %c, i32 addrspace(3)* %group.ptr.0, i32 addrspace(3)* inttoptr (i32 400 to i32 addrspace(3)*)
; CHECK-NEXT: store i32 7, i32 addrspace(3)* %select ; CHECK-NEXT: store i32 7, i32 addrspace(3)* %select
define amdgpu_kernel void @store_select_group_flat_inttoptr_group(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_flat_inttoptr_group(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* addrspacecast (i32 addrspace(3)* inttoptr (i32 400 to i32 addrspace(3)*) to i32 addrspace(4)*) %select = select i1 %c, i32* %cast0, i32* addrspacecast (i32 addrspace(3)* inttoptr (i32 400 to i32 addrspace(3)*) to i32*)
store i32 7, i32 addrspace(4)* %select store i32 7, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_flat_constexpr( ; CHECK-LABEL: @store_select_group_global_mismatch_flat_constexpr(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %select = select i1 %c, i32 addrspace(4)* %1, i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*) ; CHECK: %select = select i1 %c, i32* %1, i32* addrspacecast (i32 addrspace(1)* @global0 to i32*)
; CHECK: store i32 7, i32 addrspace(4)* %select ; CHECK: store i32 7, i32* %select
define amdgpu_kernel void @store_select_group_global_mismatch_flat_constexpr(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_global_mismatch_flat_constexpr(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*) %select = select i1 %c, i32* %cast0, i32* addrspacecast (i32 addrspace(1)* @global0 to i32*)
store i32 7, i32 addrspace(4)* %select store i32 7, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_flat_constexpr_swap( ; CHECK-LABEL: @store_select_group_global_mismatch_flat_constexpr_swap(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %select = select i1 %c, i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*), i32 addrspace(4)* %1 ; CHECK: %select = select i1 %c, i32* addrspacecast (i32 addrspace(1)* @global0 to i32*), i32* %1
; CHECK: store i32 7, i32 addrspace(4)* %select ; CHECK: store i32 7, i32* %select
define amdgpu_kernel void @store_select_group_global_mismatch_flat_constexpr_swap(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_global_mismatch_flat_constexpr_swap(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*), i32 addrspace(4)* %cast0 %select = select i1 %c, i32* addrspacecast (i32 addrspace(1)* @global0 to i32*), i32* %cast0
store i32 7, i32 addrspace(4)* %select store i32 7, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_null_null( ; CHECK-LABEL: @store_select_group_global_mismatch_null_null(
; CHECK: %select = select i1 %c, i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*) ; CHECK: %select = select i1 %c, i32* addrspacecast (i32 addrspace(3)* null to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)
; CHECK: store i32 7, i32 addrspace(4)* %select ; CHECK: store i32 7, i32* %select
define amdgpu_kernel void @store_select_group_global_mismatch_null_null(i1 %c) #0 { define amdgpu_kernel void @store_select_group_global_mismatch_null_null(i1 %c) #0 {
%select = select i1 %c, i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*) %select = select i1 %c, i32* addrspacecast (i32 addrspace(3)* null to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)
store i32 7, i32 addrspace(4)* %select store i32 7, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_null_null_constexpr( ; CHECK-LABEL: @store_select_group_global_mismatch_null_null_constexpr(
; CHECK: store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*)), align 4 ; CHECK: store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* null to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)), align 4
define amdgpu_kernel void @store_select_group_global_mismatch_null_null_constexpr() #0 { define amdgpu_kernel void @store_select_group_global_mismatch_null_null_constexpr() #0 {
store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*)), align 4 store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* null to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)), align 4
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_gv_null_constexpr( ; CHECK-LABEL: @store_select_group_global_mismatch_gv_null_constexpr(
; CHECK: store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds0 to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*)), align 4 ; CHECK: store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* @lds0 to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)), align 4
define amdgpu_kernel void @store_select_group_global_mismatch_gv_null_constexpr() #0 { define amdgpu_kernel void @store_select_group_global_mismatch_gv_null_constexpr() #0 {
store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* @lds0 to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*)), align 4 store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* @lds0 to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)), align 4
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_null_gv_constexpr( ; CHECK-LABEL: @store_select_group_global_mismatch_null_gv_constexpr(
; CHECK: store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*)), align 4 ; CHECK: store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* null to i32*), i32* addrspacecast (i32 addrspace(1)* @global0 to i32*)), align 4
define amdgpu_kernel void @store_select_group_global_mismatch_null_gv_constexpr() #0 { define amdgpu_kernel void @store_select_group_global_mismatch_null_gv_constexpr() #0 {
store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* @global0 to i32 addrspace(4)*)), align 4 store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* null to i32*), i32* addrspacecast (i32 addrspace(1)* @global0 to i32*)), align 4
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_inttoptr_null_constexpr( ; CHECK-LABEL: @store_select_group_global_mismatch_inttoptr_null_constexpr(
; CHECK: store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* inttoptr (i64 123 to i32 addrspace(3)*) to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*)), align 4 ; CHECK: store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* inttoptr (i64 123 to i32 addrspace(3)*) to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)), align 4
define amdgpu_kernel void @store_select_group_global_mismatch_inttoptr_null_constexpr() #0 { define amdgpu_kernel void @store_select_group_global_mismatch_inttoptr_null_constexpr() #0 {
store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* inttoptr (i64 123 to i32 addrspace(3)*) to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*)), align 4 store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* inttoptr (i64 123 to i32 addrspace(3)*) to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)), align 4
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_inttoptr_flat_null_constexpr( ; CHECK-LABEL: @store_select_group_global_mismatch_inttoptr_flat_null_constexpr(
; CHECK: store i32 7, i32 addrspace(1)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(1)* addrspacecast (i32 addrspace(4)* inttoptr (i64 123 to i32 addrspace(4)*) to i32 addrspace(1)*), i32 addrspace(1)* null), align 4 ; CHECK: store i32 7, i32 addrspace(1)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(1)* addrspacecast (i32* inttoptr (i64 123 to i32*) to i32 addrspace(1)*), i32 addrspace(1)* null), align 4
define amdgpu_kernel void @store_select_group_global_mismatch_inttoptr_flat_null_constexpr() #0 { define amdgpu_kernel void @store_select_group_global_mismatch_inttoptr_flat_null_constexpr() #0 {
store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* inttoptr (i64 123 to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* null to i32 addrspace(4)*)), align 4 store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* inttoptr (i64 123 to i32*), i32* addrspacecast (i32 addrspace(1)* null to i32*)), align 4
ret void ret void
} }
; CHECK-LABEL: @store_select_group_global_mismatch_undef_undef_constexpr( ; CHECK-LABEL: @store_select_group_global_mismatch_undef_undef_constexpr(
; CHECK: store i32 7, i32 addrspace(3)* null ; CHECK: store i32 7, i32 addrspace(3)* null
define amdgpu_kernel void @store_select_group_global_mismatch_undef_undef_constexpr() #0 { define amdgpu_kernel void @store_select_group_global_mismatch_undef_undef_constexpr() #0 {
store i32 7, i32 addrspace(4)* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32 addrspace(4)* addrspacecast (i32 addrspace(3)* null to i32 addrspace(4)*), i32 addrspace(4)* addrspacecast (i32 addrspace(1)* undef to i32 addrspace(4)*)), align 4 store i32 7, i32* select (i1 icmp eq (i32 ptrtoint (i32 addrspace(3)* @lds1 to i32), i32 4), i32* addrspacecast (i32 addrspace(3)* null to i32*), i32* addrspacecast (i32 addrspace(1)* undef to i32*)), align 4
ret void ret void
} }
@lds2 = external addrspace(3) global [1024 x i32], align 4 @lds2 = external addrspace(3) global [1024 x i32], align 4
; CHECK-LABEL: @store_select_group_constexpr_ptrtoint( ; CHECK-LABEL: @store_select_group_constexpr_ptrtoint(
; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* ; CHECK: %1 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
; CHECK: %select = select i1 %c, i32 addrspace(4)* %1, i32 addrspace(4)* addrspacecast (i32 addrspace(1)* inttoptr (i32 add (i32 ptrtoint ([1024 x i32] addrspace(3)* @lds2 to i32), i32 124) to i32 addrspace(1)*) to i32 addrspace(4)*) ; CHECK: %select = select i1 %c, i32* %1, i32* addrspacecast (i32 addrspace(1)* inttoptr (i32 add (i32 ptrtoint ([1024 x i32] addrspace(3)* @lds2 to i32), i32 124) to i32 addrspace(1)*) to i32*)
; CHECK: store i32 7, i32 addrspace(4)* %select ; CHECK: store i32 7, i32* %select
define amdgpu_kernel void @store_select_group_constexpr_ptrtoint(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 { define amdgpu_kernel void @store_select_group_constexpr_ptrtoint(i1 %c, i32 addrspace(3)* %group.ptr.0) #0 {
%cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32 addrspace(4)* %cast0 = addrspacecast i32 addrspace(3)* %group.ptr.0 to i32*
%select = select i1 %c, i32 addrspace(4)* %cast0, i32 addrspace(4)* addrspacecast (i32 addrspace(1)* inttoptr (i32 add (i32 ptrtoint ([1024 x i32] addrspace(3)* @lds2 to i32), i32 124) to i32 addrspace(1)*) to i32 addrspace(4)*) %select = select i1 %c, i32* %cast0, i32* addrspacecast (i32 addrspace(1)* inttoptr (i32 add (i32 ptrtoint ([1024 x i32] addrspace(3)* @lds2 to i32), i32 124) to i32 addrspace(1)*) to i32*)
store i32 7, i32 addrspace(4)* %select store i32 7, i32* %select
ret void ret void
} }
; CHECK-LABEL: @store_select_group_flat_vector( ; CHECK-LABEL: @store_select_group_flat_vector(
; CHECK: %cast0 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.0 to <2 x i32 addrspace(4)*> ; CHECK: %cast0 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.0 to <2 x i32*>
; CHECK: %cast1 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.1 to <2 x i32 addrspace(4)*> ; CHECK: %cast1 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.1 to <2 x i32*>
; CHECK: %select = select i1 %c, <2 x i32 addrspace(4)*> %cast0, <2 x i32 addrspace(4)*> %cast1 ; CHECK: %select = select i1 %c, <2 x i32*> %cast0, <2 x i32*> %cast1
; CHECK: %extract0 = extractelement <2 x i32 addrspace(4)*> %select, i32 0 ; CHECK: %extract0 = extractelement <2 x i32*> %select, i32 0
; CHECK: %extract1 = extractelement <2 x i32 addrspace(4)*> %select, i32 1 ; CHECK: %extract1 = extractelement <2 x i32*> %select, i32 1
; CHECK: store i32 -1, i32 addrspace(4)* %extract0 ; CHECK: store i32 -1, i32* %extract0
; CHECK: store i32 -2, i32 addrspace(4)* %extract1 ; CHECK: store i32 -2, i32* %extract1
define amdgpu_kernel void @store_select_group_flat_vector(i1 %c, <2 x i32 addrspace(3)*> %group.ptr.0, <2 x i32 addrspace(3)*> %group.ptr.1) #0 { define amdgpu_kernel void @store_select_group_flat_vector(i1 %c, <2 x i32 addrspace(3)*> %group.ptr.0, <2 x i32 addrspace(3)*> %group.ptr.1) #0 {
%cast0 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.0 to <2 x i32 addrspace(4)*> %cast0 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.0 to <2 x i32*>
%cast1 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.1 to <2 x i32 addrspace(4)*> %cast1 = addrspacecast <2 x i32 addrspace(3)*> %group.ptr.1 to <2 x i32*>
%select = select i1 %c, <2 x i32 addrspace(4)*> %cast0, <2 x i32 addrspace(4)*> %cast1 %select = select i1 %c, <2 x i32*> %cast0, <2 x i32*> %cast1
%extract0 = extractelement <2 x i32 addrspace(4)*> %select, i32 0 %extract0 = extractelement <2 x i32*> %select, i32 0
%extract1 = extractelement <2 x i32 addrspace(4)*> %select, i32 1 %extract1 = extractelement <2 x i32*> %select, i32 1
store i32 -1, i32 addrspace(4)* %extract0 store i32 -1, i32* %extract0
store i32 -2, i32 addrspace(4)* %extract1 store i32 -2, i32* %extract1
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }
!0 = !{!"branch_weights", i32 2, i32 10} !0 = !{!"branch_weights", i32 2, i32 10}

test/Transforms/InferAddressSpaces/AMDGPU/volatile.ll

; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s ; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -infer-address-spaces %s | FileCheck %s
; Check that volatile users of addrspacecast are not replaced. ; Check that volatile users of addrspacecast are not replaced.
; CHECK-LABEL: @volatile_load_flat_from_global( ; CHECK-LABEL: @volatile_load_flat_from_global(
; CHECK: load volatile i32, i32 addrspace(4)* ; CHECK: load volatile i32, i32*
; CHECK: store i32 %val, i32 addrspace(1)* ; CHECK: store i32 %val, i32 addrspace(1)*
define amdgpu_kernel void @volatile_load_flat_from_global(i32 addrspace(1)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 { define amdgpu_kernel void @volatile_load_flat_from_global(i32 addrspace(1)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 {
%tmp0 = addrspacecast i32 addrspace(1)* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(1)* %input to i32*
%tmp1 = addrspacecast i32 addrspace(1)* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(1)* %output to i32*
%val = load volatile i32, i32 addrspace(4)* %tmp0, align 4 %val = load volatile i32, i32* %tmp0, align 4
store i32 %val, i32 addrspace(4)* %tmp1, align 4 store i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; CHECK-LABEL: @volatile_load_flat_from_constant( ; CHECK-LABEL: @volatile_load_flat_from_constant(
; CHECK: load volatile i32, i32 addrspace(4)* ; CHECK: load volatile i32, i32*
; CHECK: store i32 %val, i32 addrspace(1)* ; CHECK: store i32 %val, i32 addrspace(1)*
define amdgpu_kernel void @volatile_load_flat_from_constant(i32 addrspace(2)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 { define amdgpu_kernel void @volatile_load_flat_from_constant(i32 addrspace(2)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 {
%tmp0 = addrspacecast i32 addrspace(2)* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(2)* %input to i32*
%tmp1 = addrspacecast i32 addrspace(1)* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(1)* %output to i32*
%val = load volatile i32, i32 addrspace(4)* %tmp0, align 4 %val = load volatile i32, i32* %tmp0, align 4
store i32 %val, i32 addrspace(4)* %tmp1, align 4 store i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; CHECK-LABEL: @volatile_load_flat_from_group( ; CHECK-LABEL: @volatile_load_flat_from_group(
; CHECK: load volatile i32, i32 addrspace(4)* ; CHECK: load volatile i32, i32*
; CHECK: store i32 %val, i32 addrspace(3)* ; CHECK: store i32 %val, i32 addrspace(3)*
define amdgpu_kernel void @volatile_load_flat_from_group(i32 addrspace(3)* nocapture %input, i32 addrspace(3)* nocapture %output) #0 { define amdgpu_kernel void @volatile_load_flat_from_group(i32 addrspace(3)* nocapture %input, i32 addrspace(3)* nocapture %output) #0 {
%tmp0 = addrspacecast i32 addrspace(3)* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(3)* %input to i32*
%tmp1 = addrspacecast i32 addrspace(3)* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(3)* %output to i32*
%val = load volatile i32, i32 addrspace(4)* %tmp0, align 4 %val = load volatile i32, i32* %tmp0, align 4
store i32 %val, i32 addrspace(4)* %tmp1, align 4 store i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; CHECK-LABEL: @volatile_load_flat_from_private( ; CHECK-LABEL: @volatile_load_flat_from_private(
; CHECK: load volatile i32, i32 addrspace(4)* ; CHECK: load volatile i32, i32*
; CHECK: store i32 %val, i32* ; CHECK: store i32 %val, i32 addrspace(5)*
define amdgpu_kernel void @volatile_load_flat_from_private(i32* nocapture %input, i32* nocapture %output) #0 { define amdgpu_kernel void @volatile_load_flat_from_private(i32 addrspace(5)* nocapture %input, i32 addrspace(5)* nocapture %output) #0 {
%tmp0 = addrspacecast i32* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(5)* %input to i32*
%tmp1 = addrspacecast i32* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(5)* %output to i32*
%val = load volatile i32, i32 addrspace(4)* %tmp0, align 4 %val = load volatile i32, i32* %tmp0, align 4
store i32 %val, i32 addrspace(4)* %tmp1, align 4 store i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; CHECK-LABEL: @volatile_store_flat_to_global( ; CHECK-LABEL: @volatile_store_flat_to_global(
; CHECK: load i32, i32 addrspace(1)* ; CHECK: load i32, i32 addrspace(1)*
; CHECK: store volatile i32 %val, i32 addrspace(4)* ; CHECK: store volatile i32 %val, i32*
define amdgpu_kernel void @volatile_store_flat_to_global(i32 addrspace(1)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 { define amdgpu_kernel void @volatile_store_flat_to_global(i32 addrspace(1)* nocapture %input, i32 addrspace(1)* nocapture %output) #0 {
%tmp0 = addrspacecast i32 addrspace(1)* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(1)* %input to i32*
%tmp1 = addrspacecast i32 addrspace(1)* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(1)* %output to i32*
%val = load i32, i32 addrspace(4)* %tmp0, align 4 %val = load i32, i32* %tmp0, align 4
store volatile i32 %val, i32 addrspace(4)* %tmp1, align 4 store volatile i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; CHECK-LABEL: @volatile_store_flat_to_group( ; CHECK-LABEL: @volatile_store_flat_to_group(
; CHECK: load i32, i32 addrspace(3)* ; CHECK: load i32, i32 addrspace(3)*
; CHECK: store volatile i32 %val, i32 addrspace(4)* ; CHECK: store volatile i32 %val, i32*
define amdgpu_kernel void @volatile_store_flat_to_group(i32 addrspace(3)* nocapture %input, i32 addrspace(3)* nocapture %output) #0 { define amdgpu_kernel void @volatile_store_flat_to_group(i32 addrspace(3)* nocapture %input, i32 addrspace(3)* nocapture %output) #0 {
%tmp0 = addrspacecast i32 addrspace(3)* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(3)* %input to i32*
%tmp1 = addrspacecast i32 addrspace(3)* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(3)* %output to i32*
%val = load i32, i32 addrspace(4)* %tmp0, align 4 %val = load i32, i32* %tmp0, align 4
store volatile i32 %val, i32 addrspace(4)* %tmp1, align 4 store volatile i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; CHECK-LABEL: @volatile_store_flat_to_private( ; CHECK-LABEL: @volatile_store_flat_to_private(
; CHECK: load i32, i32* ; CHECK: load i32, i32 addrspace(5)*
; CHECK: store volatile i32 %val, i32 addrspace(4)* ; CHECK: store volatile i32 %val, i32*
define amdgpu_kernel void @volatile_store_flat_to_private(i32* nocapture %input, i32* nocapture %output) #0 { define amdgpu_kernel void @volatile_store_flat_to_private(i32 addrspace(5)* nocapture %input, i32 addrspace(5)* nocapture %output) #0 {
%tmp0 = addrspacecast i32* %input to i32 addrspace(4)* %tmp0 = addrspacecast i32 addrspace(5)* %input to i32*
%tmp1 = addrspacecast i32* %output to i32 addrspace(4)* %tmp1 = addrspacecast i32 addrspace(5)* %output to i32*
%val = load i32, i32 addrspace(4)* %tmp0, align 4 %val = load i32, i32* %tmp0, align 4
store volatile i32 %val, i32 addrspace(4)* %tmp1, align 4 store volatile i32 %val, i32* %tmp1, align 4
ret void ret void
} }
; CHECK-LABEL: @volatile_atomicrmw_add_group_to_flat( ; CHECK-LABEL: @volatile_atomicrmw_add_group_to_flat(
; CHECK: addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* ; CHECK: addrspacecast i32 addrspace(3)* %group.ptr to i32*
; CHECK: atomicrmw volatile add i32 addrspace(4)* ; CHECK: atomicrmw volatile add i32*
define i32 @volatile_atomicrmw_add_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %y) #0 { define i32 @volatile_atomicrmw_add_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %y) #0 {
%cast = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* %group.ptr to i32*
%ret = atomicrmw volatile add i32 addrspace(4)* %cast, i32 %y seq_cst %ret = atomicrmw volatile add i32* %cast, i32 %y seq_cst
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @volatile_atomicrmw_add_global_to_flat( ; CHECK-LABEL: @volatile_atomicrmw_add_global_to_flat(
; CHECK: addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* ; CHECK: addrspacecast i32 addrspace(1)* %global.ptr to i32*
; CHECK: %ret = atomicrmw volatile add i32 addrspace(4)* ; CHECK: %ret = atomicrmw volatile add i32*
define i32 @volatile_atomicrmw_add_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %y) #0 { define i32 @volatile_atomicrmw_add_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %y) #0 {
%cast = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %global.ptr to i32*
%ret = atomicrmw volatile add i32 addrspace(4)* %cast, i32 %y seq_cst %ret = atomicrmw volatile add i32* %cast, i32 %y seq_cst
ret i32 %ret ret i32 %ret
} }
; CHECK-LABEL: @volatile_cmpxchg_global_to_flat( ; CHECK-LABEL: @volatile_cmpxchg_global_to_flat(
; CHECK: addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* ; CHECK: addrspacecast i32 addrspace(1)* %global.ptr to i32*
; CHECK: cmpxchg volatile i32 addrspace(4)* ; CHECK: cmpxchg volatile i32*
define { i32, i1 } @volatile_cmpxchg_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %cmp, i32 %val) #0 { define { i32, i1 } @volatile_cmpxchg_global_to_flat(i32 addrspace(1)* %global.ptr, i32 %cmp, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(1)* %global.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(1)* %global.ptr to i32*
%ret = cmpxchg volatile i32 addrspace(4)* %cast, i32 %cmp, i32 %val seq_cst monotonic %ret = cmpxchg volatile i32* %cast, i32 %cmp, i32 %val seq_cst monotonic
ret { i32, i1 } %ret ret { i32, i1 } %ret
} }
; CHECK-LABEL: @volatile_cmpxchg_group_to_flat( ; CHECK-LABEL: @volatile_cmpxchg_group_to_flat(
; CHECK: addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* ; CHECK: addrspacecast i32 addrspace(3)* %group.ptr to i32*
; CHECK: cmpxchg volatile i32 addrspace(4)* ; CHECK: cmpxchg volatile i32*
define { i32, i1 } @volatile_cmpxchg_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %cmp, i32 %val) #0 { define { i32, i1 } @volatile_cmpxchg_group_to_flat(i32 addrspace(3)* %group.ptr, i32 %cmp, i32 %val) #0 {
%cast = addrspacecast i32 addrspace(3)* %group.ptr to i32 addrspace(4)* %cast = addrspacecast i32 addrspace(3)* %group.ptr to i32*
%ret = cmpxchg volatile i32 addrspace(4)* %cast, i32 %cmp, i32 %val seq_cst monotonic %ret = cmpxchg volatile i32* %cast, i32 %cmp, i32 %val seq_cst monotonic
ret { i32, i1 } %ret ret { i32, i1 } %ret
} }
; FIXME: Shouldn't be losing names ; FIXME: Shouldn't be losing names
; CHECK-LABEL: @volatile_memset_group_to_flat( ; CHECK-LABEL: @volatile_memset_group_to_flat(
; CHECK: addrspacecast i8 addrspace(3)* %group.ptr to i8 addrspace(4)* ; CHECK: addrspacecast i8 addrspace(3)* %group.ptr to i8*
; CHECK: call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %1, i8 4, i64 32, i1 true) ; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 4, i64 32, i1 true)
define amdgpu_kernel void @volatile_memset_group_to_flat(i8 addrspace(3)* %group.ptr, i32 %y) #0 { define amdgpu_kernel void @volatile_memset_group_to_flat(i8 addrspace(3)* %group.ptr, i32 %y) #0 {
%cast = addrspacecast i8 addrspace(3)* %group.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(3)* %group.ptr to i8*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %cast, i8 4, i64 32, i1 true) call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 true)
ret void ret void
} }
; CHECK-LABEL: @volatile_memset_global_to_flat( ; CHECK-LABEL: @volatile_memset_global_to_flat(
; CHECK: addrspacecast i8 addrspace(1)* %global.ptr to i8 addrspace(4)* ; CHECK: addrspacecast i8 addrspace(1)* %global.ptr to i8*
; CHECK: call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %1, i8 4, i64 32, i1 true) ; CHECK: call void @llvm.memset.p0i8.i64(i8* align 4 %1, i8 4, i64 32, i1 true)
define amdgpu_kernel void @volatile_memset_global_to_flat(i8 addrspace(1)* %global.ptr, i32 %y) #0 { define amdgpu_kernel void @volatile_memset_global_to_flat(i8 addrspace(1)* %global.ptr, i32 %y) #0 {
%cast = addrspacecast i8 addrspace(1)* %global.ptr to i8 addrspace(4)* %cast = addrspacecast i8 addrspace(1)* %global.ptr to i8*
call void @llvm.memset.p4i8.i64(i8 addrspace(4)* align 4 %cast, i8 4, i64 32, i1 true) call void @llvm.memset.p0i8.i64(i8* align 4 %cast, i8 4, i64 32, i1 true)
ret void ret void
} }
declare void @llvm.memset.p4i8.i64(i8 addrspace(4)* nocapture writeonly, i8, i64, i1) #1 declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i1) #1
attributes #0 = { nounwind } attributes #0 = { nounwind }
attributes #1 = { argmemonly nounwind } attributes #1 = { argmemonly nounwind }

test/Transforms/LoadStoreVectorizer/AMDGPU/adjust-alloca-alignment.ll

; RUN: opt -S -load-store-vectorizer -mattr=-unaligned-buffer-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s ; RUN: opt -data-layout=A5 -S -load-store-vectorizer -mattr=-unaligned-buffer-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=ALIGNED -check-prefix=ALL %s
; RUN: opt -S -load-store-vectorizer -mattr=+unaligned-buffer-access,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s ; RUN: opt -data-layout=A5 -S -load-store-vectorizer -mattr=+unaligned-buffer-access,+unaligned-scratch-access,+max-private-element-size-16 < %s | FileCheck -check-prefix=UNALIGNED -check-prefix=ALL %s
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "amdgcn--" target triple = "amdgcn--"
; ALL-LABEL: @load_unknown_offset_align1_i8( ; ALL-LABEL: @load_unknown_offset_align1_i8(
; ALL: alloca [128 x i8], align 1 ; ALL: alloca [128 x i8], align 1
; UNALIGNED: load <2 x i8>, <2 x i8>* %{{[0-9]+}}, align 1{{$}} ; UNALIGNED: load <2 x i8>, <2 x i8> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
; ALIGNED: load i8, i8* %ptr0, align 1{{$}} ; ALIGNED: load i8, i8 addrspace(5)* %ptr0, align 1{{$}}
; ALIGNED: load i8, i8* %ptr1, align 1{{$}} ; ALIGNED: load i8, i8 addrspace(5)* %ptr1, align 1{{$}}
define amdgpu_kernel void @load_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 { define amdgpu_kernel void @load_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 {
%alloca = alloca [128 x i8], align 1 %alloca = alloca [128 x i8], align 1, addrspace(5)
%ptr0 = getelementptr inbounds [128 x i8], [128 x i8]* %alloca, i32 0, i32 %offset %ptr0 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %alloca, i32 0, i32 %offset
%val0 = load i8, i8* %ptr0, align 1 %val0 = load i8, i8 addrspace(5)* %ptr0, align 1
%ptr1 = getelementptr inbounds i8, i8* %ptr0, i32 1 %ptr1 = getelementptr inbounds i8, i8 addrspace(5)* %ptr0, i32 1
%val1 = load i8, i8* %ptr1, align 1 %val1 = load i8, i8 addrspace(5)* %ptr1, align 1
%add = add i8 %val0, %val1 %add = add i8 %val0, %val1
store i8 %add, i8 addrspace(1)* %out store i8 %add, i8 addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: @load_unknown_offset_align1_i16( ; ALL-LABEL: @load_unknown_offset_align1_i16(
; ALL: alloca [128 x i16], align 1{{$}} ; ALL: alloca [128 x i16], align 1, addrspace(5){{$}}
; UNALIGNED: load <2 x i16>, <2 x i16>* %{{[0-9]+}}, align 1{{$}} ; UNALIGNED: load <2 x i16>, <2 x i16> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
; ALIGNED: load i16, i16* %ptr0, align 1{{$}} ; ALIGNED: load i16, i16 addrspace(5)* %ptr0, align 1{{$}}
; ALIGNED: load i16, i16* %ptr1, align 1{{$}} ; ALIGNED: load i16, i16 addrspace(5)* %ptr1, align 1{{$}}
define amdgpu_kernel void @load_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 { define amdgpu_kernel void @load_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 {
%alloca = alloca [128 x i16], align 1 %alloca = alloca [128 x i16], align 1, addrspace(5)
%ptr0 = getelementptr inbounds [128 x i16], [128 x i16]* %alloca, i32 0, i32 %offset %ptr0 = getelementptr inbounds [128 x i16], [128 x i16] addrspace(5)* %alloca, i32 0, i32 %offset
%val0 = load i16, i16* %ptr0, align 1 %val0 = load i16, i16 addrspace(5)* %ptr0, align 1
%ptr1 = getelementptr inbounds i16, i16* %ptr0, i32 1 %ptr1 = getelementptr inbounds i16, i16 addrspace(5)* %ptr0, i32 1
%val1 = load i16, i16* %ptr1, align 1 %val1 = load i16, i16 addrspace(5)* %ptr1, align 1
%add = add i16 %val0, %val1 %add = add i16 %val0, %val1
store i16 %add, i16 addrspace(1)* %out store i16 %add, i16 addrspace(1)* %out
ret void ret void
} }
; FIXME: Although the offset is unknown here, we know it is a multiple ; FIXME: Although the offset is unknown here, we know it is a multiple
; of the element size, so should still be align 4 ; of the element size, so should still be align 4
; ALL-LABEL: @load_unknown_offset_align1_i32( ; ALL-LABEL: @load_unknown_offset_align1_i32(
; ALL: alloca [128 x i32], align 1 ; ALL: alloca [128 x i32], align 1
; UNALIGNED: load <2 x i32>, <2 x i32>* %{{[0-9]+}}, align 1{{$}} ; UNALIGNED: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
; ALIGNED: load i32, i32* %ptr0, align 1 ; ALIGNED: load i32, i32 addrspace(5)* %ptr0, align 1
; ALIGNED: load i32, i32* %ptr1, align 1 ; ALIGNED: load i32, i32 addrspace(5)* %ptr1, align 1
define amdgpu_kernel void @load_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { define amdgpu_kernel void @load_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 {
%alloca = alloca [128 x i32], align 1 %alloca = alloca [128 x i32], align 1, addrspace(5)
%ptr0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca, i32 0, i32 %offset %ptr0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca, i32 0, i32 %offset
%val0 = load i32, i32* %ptr0, align 1 %val0 = load i32, i32 addrspace(5)* %ptr0, align 1
%ptr1 = getelementptr inbounds i32, i32* %ptr0, i32 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(5)* %ptr0, i32 1
%val1 = load i32, i32* %ptr1, align 1 %val1 = load i32, i32 addrspace(5)* %ptr1, align 1
%add = add i32 %val0, %val1 %add = add i32 %val0, %val1
store i32 %add, i32 addrspace(1)* %out store i32 %add, i32 addrspace(1)* %out
ret void ret void
} }
; FIXME: Should always increase alignment of the load ; FIXME: Should always increase alignment of the load
; Make sure alloca alignment isn't decreased ; Make sure alloca alignment isn't decreased
; ALL-LABEL: @load_alloca16_unknown_offset_align1_i32( ; ALL-LABEL: @load_alloca16_unknown_offset_align1_i32(
; ALL: alloca [128 x i32], align 16 ; ALL: alloca [128 x i32], align 16
; UNALIGNED: load <2 x i32>, <2 x i32>* %{{[0-9]+}}, align 1{{$}} ; UNALIGNED: load <2 x i32>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
; FIXME: Should change alignment ; FIXME: Should change alignment
; ALIGNED: load i32 ; ALIGNED: load i32
; ALIGNED: load i32 ; ALIGNED: load i32
define amdgpu_kernel void @load_alloca16_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { define amdgpu_kernel void @load_alloca16_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 {
%alloca = alloca [128 x i32], align 16 %alloca = alloca [128 x i32], align 16, addrspace(5)
%ptr0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca, i32 0, i32 %offset %ptr0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca, i32 0, i32 %offset
%val0 = load i32, i32* %ptr0, align 1 %val0 = load i32, i32 addrspace(5)* %ptr0, align 1
%ptr1 = getelementptr inbounds i32, i32* %ptr0, i32 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(5)* %ptr0, i32 1
%val1 = load i32, i32* %ptr1, align 1 %val1 = load i32, i32 addrspace(5)* %ptr1, align 1
%add = add i32 %val0, %val1 %add = add i32 %val0, %val1
store i32 %add, i32 addrspace(1)* %out store i32 %add, i32 addrspace(1)* %out
ret void ret void
} }
; ALL-LABEL: @store_unknown_offset_align1_i8( ; ALL-LABEL: @store_unknown_offset_align1_i8(
; ALL: alloca [128 x i8], align 1 ; ALL: alloca [128 x i8], align 1
; UNALIGNED: store <2 x i8> <i8 9, i8 10>, <2 x i8>* %{{[0-9]+}}, align 1{{$}} ; UNALIGNED: store <2 x i8> <i8 9, i8 10>, <2 x i8> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
; ALIGNED: store i8 9, i8* %ptr0, align 1{{$}} ; ALIGNED: store i8 9, i8 addrspace(5)* %ptr0, align 1{{$}}
; ALIGNED: store i8 10, i8* %ptr1, align 1{{$}} ; ALIGNED: store i8 10, i8 addrspace(5)* %ptr1, align 1{{$}}
define amdgpu_kernel void @store_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 { define amdgpu_kernel void @store_unknown_offset_align1_i8(i8 addrspace(1)* noalias %out, i32 %offset) #0 {
%alloca = alloca [128 x i8], align 1 %alloca = alloca [128 x i8], align 1, addrspace(5)
%ptr0 = getelementptr inbounds [128 x i8], [128 x i8]* %alloca, i32 0, i32 %offset %ptr0 = getelementptr inbounds [128 x i8], [128 x i8] addrspace(5)* %alloca, i32 0, i32 %offset
store i8 9, i8* %ptr0, align 1 store i8 9, i8 addrspace(5)* %ptr0, align 1
%ptr1 = getelementptr inbounds i8, i8* %ptr0, i32 1 %ptr1 = getelementptr inbounds i8, i8 addrspace(5)* %ptr0, i32 1
store i8 10, i8* %ptr1, align 1 store i8 10, i8 addrspace(5)* %ptr1, align 1
ret void ret void
} }
; ALL-LABEL: @store_unknown_offset_align1_i16( ; ALL-LABEL: @store_unknown_offset_align1_i16(
; ALL: alloca [128 x i16], align 1 ; ALL: alloca [128 x i16], align 1
; UNALIGNED: store <2 x i16> <i16 9, i16 10>, <2 x i16>* %{{[0-9]+}}, align 1{{$}} ; UNALIGNED: store <2 x i16> <i16 9, i16 10>, <2 x i16> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
; ALIGNED: store i16 9, i16* %ptr0, align 1{{$}} ; ALIGNED: store i16 9, i16 addrspace(5)* %ptr0, align 1{{$}}
; ALIGNED: store i16 10, i16* %ptr1, align 1{{$}} ; ALIGNED: store i16 10, i16 addrspace(5)* %ptr1, align 1{{$}}
define amdgpu_kernel void @store_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 { define amdgpu_kernel void @store_unknown_offset_align1_i16(i16 addrspace(1)* noalias %out, i32 %offset) #0 {
%alloca = alloca [128 x i16], align 1 %alloca = alloca [128 x i16], align 1, addrspace(5)
%ptr0 = getelementptr inbounds [128 x i16], [128 x i16]* %alloca, i32 0, i32 %offset %ptr0 = getelementptr inbounds [128 x i16], [128 x i16] addrspace(5)* %alloca, i32 0, i32 %offset
store i16 9, i16* %ptr0, align 1 store i16 9, i16 addrspace(5)* %ptr0, align 1
%ptr1 = getelementptr inbounds i16, i16* %ptr0, i32 1 %ptr1 = getelementptr inbounds i16, i16 addrspace(5)* %ptr0, i32 1
store i16 10, i16* %ptr1, align 1 store i16 10, i16 addrspace(5)* %ptr1, align 1
ret void ret void
} }
; FIXME: Although the offset is unknown here, we know it is a multiple ; FIXME: Although the offset is unknown here, we know it is a multiple
; of the element size, so it still should be align 4. ; of the element size, so it still should be align 4.
; ALL-LABEL: @store_unknown_offset_align1_i32( ; ALL-LABEL: @store_unknown_offset_align1_i32(
; ALL: alloca [128 x i32], align 1 ; ALL: alloca [128 x i32], align 1
; UNALIGNED: store <2 x i32> <i32 9, i32 10>, <2 x i32>* %{{[0-9]+}}, align 1{{$}} ; UNALIGNED: store <2 x i32> <i32 9, i32 10>, <2 x i32> addrspace(5)* %{{[0-9]+}}, align 1{{$}}
; ALIGNED: store i32 9, i32* %ptr0, align 1 ; ALIGNED: store i32 9, i32 addrspace(5)* %ptr0, align 1
; ALIGNED: store i32 10, i32* %ptr1, align 1 ; ALIGNED: store i32 10, i32 addrspace(5)* %ptr1, align 1
define amdgpu_kernel void @store_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 { define amdgpu_kernel void @store_unknown_offset_align1_i32(i32 addrspace(1)* noalias %out, i32 %offset) #0 {
%alloca = alloca [128 x i32], align 1 %alloca = alloca [128 x i32], align 1, addrspace(5)
%ptr0 = getelementptr inbounds [128 x i32], [128 x i32]* %alloca, i32 0, i32 %offset %ptr0 = getelementptr inbounds [128 x i32], [128 x i32] addrspace(5)* %alloca, i32 0, i32 %offset
store i32 9, i32* %ptr0, align 1 store i32 9, i32 addrspace(5)* %ptr0, align 1
%ptr1 = getelementptr inbounds i32, i32* %ptr0, i32 1 %ptr1 = getelementptr inbounds i32, i32 addrspace(5)* %ptr0, i32 1
store i32 10, i32* %ptr1, align 1 store i32 10, i32 addrspace(5)* %ptr1, align 1
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/Transforms/LoadStoreVectorizer/AMDGPU/merge-stores-private.ll

; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,-unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-ALIGNED,ALIGNED,ALL %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,-unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-ALIGNED,ALIGNED,ALL %s
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,-unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ELT8-ALIGNED,ALIGNED,ALL %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,-unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ELT8-ALIGNED,ALIGNED,ALL %s
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,-unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ELT16-ALIGNED,ALIGNED,ALL %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,-unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ELT16-ALIGNED,ALIGNED,ALL %s
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,+unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-UNALIGNED,UNALIGNED,ALL %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-4,+unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT4,ELT4-UNALIGNED,UNALIGNED,ALL %s
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,+unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ELT8-UNALIGNED,UNALIGNED,ALL %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-8,+unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT8,ELT8-UNALIGNED,UNALIGNED,ALL %s
; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,+unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ELT16-UNALIGNED,UNALIGNED,ALL %s ; RUN: opt -mtriple=amdgcn-amd-amdhsa -mattr=+max-private-element-size-16,+unaligned-scratch-access -load-store-vectorizer -S -o - %s | FileCheck -check-prefixes=ELT16,ELT16-UNALIGNED,UNALIGNED,ALL %s
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-p24:64:64-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32 ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32
; ALIGNED: store i32 ; ALIGNED: store i32
; ALIGNED: store i32 ; ALIGNED: store i32
; ALIGNED: store i32 ; ALIGNED: store i32
; ALIGNED: store i32 ; ALIGNED: store i32
; ELT8-UNALIGNED: store <2 x i32> ; ELT8-UNALIGNED: store <2 x i32>
; ELT8-UNALIGNED: store <2 x i32> ; ELT8-UNALIGNED: store <2 x i32>
; ELT16-UNALIGNED: store <4 x i32> ; ELT16-UNALIGNED: store <4 x i32>
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32(i32* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32(i32 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i32, i32* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1
%out.gep.2 = getelementptr i32, i32* %out, i32 2 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2
%out.gep.3 = getelementptr i32, i32* %out, i32 3 %out.gep.3 = getelementptr i32, i32 addrspace(5)* %out, i32 3
store i32 9, i32* %out store i32 9, i32 addrspace(5)* %out
store i32 1, i32* %out.gep.1 store i32 1, i32 addrspace(5)* %out.gep.1
store i32 23, i32* %out.gep.2 store i32 23, i32 addrspace(5)* %out.gep.2
store i32 19, i32* %out.gep.3 store i32 19, i32 addrspace(5)* %out.gep.3
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32_align1( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32_align1(
; ALIGNED: store i32 9, i32* %out, align 1 ; ALIGNED: store i32 9, i32 addrspace(5)* %out, align 1
; ALIGNED: store i32 1, i32* %out.gep.1, align 1 ; ALIGNED: store i32 1, i32 addrspace(5)* %out.gep.1, align 1
; ALIGNED: store i32 23, i32* %out.gep.2, align 1 ; ALIGNED: store i32 23, i32 addrspace(5)* %out.gep.2, align 1
; ALIGNED: store i32 19, i32* %out.gep.3, align 1 ; ALIGNED: store i32 19, i32 addrspace(5)* %out.gep.3, align 1
; ELT16-UNALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32>* %1, align 1 ; ELT16-UNALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32> addrspace(5)* %1, align 1
; ELT8-UNALIGNED: store <2 x i32> <i32 9, i32 1>, <2 x i32>* %1, align 1 ; ELT8-UNALIGNED: store <2 x i32> <i32 9, i32 1>, <2 x i32> addrspace(5)* %1, align 1
; ELT8-UNALIGNED: store <2 x i32> <i32 23, i32 19>, <2 x i32>* %2, align 1 ; ELT8-UNALIGNED: store <2 x i32> <i32 23, i32 19>, <2 x i32> addrspace(5)* %2, align 1
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align1(i32* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align1(i32 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i32, i32* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1
%out.gep.2 = getelementptr i32, i32* %out, i32 2 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2
%out.gep.3 = getelementptr i32, i32* %out, i32 3 %out.gep.3 = getelementptr i32, i32 addrspace(5)* %out, i32 3
store i32 9, i32* %out, align 1 store i32 9, i32 addrspace(5)* %out, align 1
store i32 1, i32* %out.gep.1, align 1 store i32 1, i32 addrspace(5)* %out.gep.1, align 1
store i32 23, i32* %out.gep.2, align 1 store i32 23, i32 addrspace(5)* %out.gep.2, align 1
store i32 19, i32* %out.gep.3, align 1 store i32 19, i32 addrspace(5)* %out.gep.3, align 1
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32_align2( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i32_align2(
; ALIGNED: store i32 9, i32* %out, align 2 ; ALIGNED: store i32 9, i32 addrspace(5)* %out, align 2
; ALIGNED: store i32 1, i32* %out.gep.1, align 2 ; ALIGNED: store i32 1, i32 addrspace(5)* %out.gep.1, align 2
; ALIGNED: store i32 23, i32* %out.gep.2, align 2 ; ALIGNED: store i32 23, i32 addrspace(5)* %out.gep.2, align 2
; ALIGNED: store i32 19, i32* %out.gep.3, align 2 ; ALIGNED: store i32 19, i32 addrspace(5)* %out.gep.3, align 2
; ELT16-UNALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32>* %1, align 2 ; ELT16-UNALIGNED: store <4 x i32> <i32 9, i32 1, i32 23, i32 19>, <4 x i32> addrspace(5)* %1, align 2
; ELT8-UNALIGNED: store <2 x i32> ; ELT8-UNALIGNED: store <2 x i32>
; ELT8-UNALIGNED: store <2 x i32> ; ELT8-UNALIGNED: store <2 x i32>
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align2(i32* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i32_align2(i32 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i32, i32* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1
%out.gep.2 = getelementptr i32, i32* %out, i32 2 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2
%out.gep.3 = getelementptr i32, i32* %out, i32 3 %out.gep.3 = getelementptr i32, i32 addrspace(5)* %out, i32 3
store i32 9, i32* %out, align 2 store i32 9, i32 addrspace(5)* %out, align 2
store i32 1, i32* %out.gep.1, align 2 store i32 1, i32 addrspace(5)* %out.gep.1, align 2
store i32 23, i32* %out.gep.2, align 2 store i32 23, i32 addrspace(5)* %out.gep.2, align 2
store i32 19, i32* %out.gep.3, align 2 store i32 19, i32 addrspace(5)* %out.gep.3, align 2
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8(
; ALL: store <4 x i8> ; ALL: store <4 x i8>
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8(i8* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8(i8 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i8, i8* %out, i32 1 %out.gep.1 = getelementptr i8, i8 addrspace(5)* %out, i32 1
%out.gep.2 = getelementptr i8, i8* %out, i32 2 %out.gep.2 = getelementptr i8, i8 addrspace(5)* %out, i32 2
%out.gep.3 = getelementptr i8, i8* %out, i32 3 %out.gep.3 = getelementptr i8, i8 addrspace(5)* %out, i32 3
store i8 9, i8* %out, align 4 store i8 9, i8 addrspace(5)* %out, align 4
store i8 1, i8* %out.gep.1 store i8 1, i8 addrspace(5)* %out.gep.1
store i8 23, i8* %out.gep.2 store i8 23, i8 addrspace(5)* %out.gep.2
store i8 19, i8* %out.gep.3 store i8 19, i8 addrspace(5)* %out.gep.3
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8_align1( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v4i8_align1(
; ALIGNED: store i8 ; ALIGNED: store i8
; ALIGNED: store i8 ; ALIGNED: store i8
; ALIGNED: store i8 ; ALIGNED: store i8
; ALIGNED: store i8 ; ALIGNED: store i8
; UNALIGNED: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, <4 x i8>* %1, align 1 ; UNALIGNED: store <4 x i8> <i8 9, i8 1, i8 23, i8 19>, <4 x i8> addrspace(5)* %1, align 1
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8_align1(i8* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v4i8_align1(i8 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i8, i8* %out, i32 1 %out.gep.1 = getelementptr i8, i8 addrspace(5)* %out, i32 1
%out.gep.2 = getelementptr i8, i8* %out, i32 2 %out.gep.2 = getelementptr i8, i8 addrspace(5)* %out, i32 2
%out.gep.3 = getelementptr i8, i8* %out, i32 3 %out.gep.3 = getelementptr i8, i8 addrspace(5)* %out, i32 3
store i8 9, i8* %out, align 1 store i8 9, i8 addrspace(5)* %out, align 1
store i8 1, i8* %out.gep.1, align 1 store i8 1, i8 addrspace(5)* %out.gep.1, align 1
store i8 23, i8* %out.gep.2, align 1 store i8 23, i8 addrspace(5)* %out.gep.2, align 1
store i8 19, i8* %out.gep.3, align 1 store i8 19, i8 addrspace(5)* %out.gep.3, align 1
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16(
; ALL: store <2 x i16> ; ALL: store <2 x i16>
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16(i16* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16(i16 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i16, i16* %out, i32 1 %out.gep.1 = getelementptr i16, i16 addrspace(5)* %out, i32 1
store i16 9, i16* %out, align 4 store i16 9, i16 addrspace(5)* %out, align 4
store i16 12, i16* %out.gep.1 store i16 12, i16 addrspace(5)* %out.gep.1
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align2( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align2(
; ALIGNED: store i16 ; ALIGNED: store i16
; ALIGNED: store i16 ; ALIGNED: store i16
; UNALIGNED: store <2 x i16> <i16 9, i16 12>, <2 x i16>* %1, align 2 ; UNALIGNED: store <2 x i16> <i16 9, i16 12>, <2 x i16> addrspace(5)* %1, align 2
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align2(i16* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align2(i16 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i16, i16* %out, i32 1 %out.gep.1 = getelementptr i16, i16 addrspace(5)* %out, i32 1
store i16 9, i16* %out, align 2 store i16 9, i16 addrspace(5)* %out, align 2
store i16 12, i16* %out.gep.1, align 2 store i16 12, i16 addrspace(5)* %out.gep.1, align 2
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align1( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align1(
; ALIGNED: store i16 ; ALIGNED: store i16
; ALIGNED: store i16 ; ALIGNED: store i16
; UNALIGNED: store <2 x i16> <i16 9, i16 12>, <2 x i16>* %1, align 1 ; UNALIGNED: store <2 x i16> <i16 9, i16 12>, <2 x i16> addrspace(5)* %1, align 1
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align1(i16* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align1(i16 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i16, i16* %out, i32 1 %out.gep.1 = getelementptr i16, i16 addrspace(5)* %out, i32 1
store i16 9, i16* %out, align 1 store i16 9, i16 addrspace(5)* %out, align 1
store i16 12, i16* %out.gep.1, align 1 store i16 12, i16 addrspace(5)* %out.gep.1, align 1
ret void ret void
} }
; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align8( ; ALL-LABEL: @merge_private_store_4_vector_elts_loads_v2i16_align8(
; ALL: store <2 x i16> <i16 9, i16 12>, <2 x i16>* %1, align 8 ; ALL: store <2 x i16> <i16 9, i16 12>, <2 x i16> addrspace(5)* %1, align 8
define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align8(i16* %out) #0 { define amdgpu_kernel void @merge_private_store_4_vector_elts_loads_v2i16_align8(i16 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i16, i16* %out, i32 1 %out.gep.1 = getelementptr i16, i16 addrspace(5)* %out, i32 1
store i16 9, i16* %out, align 8 store i16 9, i16 addrspace(5)* %out, align 8
store i16 12, i16* %out.gep.1, align 2 store i16 12, i16 addrspace(5)* %out.gep.1, align 2
ret void ret void
} }
; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i32 ; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i32
; ELT4: store i32 ; ELT4: store i32
; ELT4: store i32 ; ELT4: store i32
; ELT4: store i32 ; ELT4: store i32
; ELT8-ALIGNED: store i32 ; ELT8-ALIGNED: store i32
; ELT8-ALIGNED: store i32 ; ELT8-ALIGNED: store i32
; ELT8-ALIGNED: store i32 ; ELT8-ALIGNED: store i32
; ELT8-UNALIGNED: store <2 x i32> ; ELT8-UNALIGNED: store <2 x i32>
; ELT8-UNALIGNED: store i32 ; ELT8-UNALIGNED: store i32
; ELT16-ALIGNED: store i32 ; ELT16-ALIGNED: store i32
; ELT16-ALIGNED: store i32 ; ELT16-ALIGNED: store i32
; ELT16-ALIGNED: store i32 ; ELT16-ALIGNED: store i32
; ELT16-UNALIGNED: store <3 x i32> ; ELT16-UNALIGNED: store <3 x i32>
define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i32(i32* %out) #0 { define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i32(i32 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i32, i32* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1
%out.gep.2 = getelementptr i32, i32* %out, i32 2 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2
store i32 9, i32* %out store i32 9, i32 addrspace(5)* %out
store i32 1, i32* %out.gep.1 store i32 1, i32 addrspace(5)* %out.gep.1
store i32 23, i32* %out.gep.2 store i32 23, i32 addrspace(5)* %out.gep.2
ret void ret void
} }
; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i32_align1( ; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i32_align1(
; ALIGNED: store i32 ; ALIGNED: store i32
; ALIGNED: store i32 ; ALIGNED: store i32
; ALIGNED: store i32 ; ALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT4-UNALIGNED: store i32 ; ELT4-UNALIGNED: store i32
; ELT8-UNALIGNED: store <2 x i32> ; ELT8-UNALIGNED: store <2 x i32>
; ELT8-UNALIGNED: store i32 ; ELT8-UNALIGNED: store i32
; ELT16-UNALIGNED: store <3 x i32> ; ELT16-UNALIGNED: store <3 x i32>
define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i32_align1(i32* %out) #0 { define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i32_align1(i32 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i32, i32* %out, i32 1 %out.gep.1 = getelementptr i32, i32 addrspace(5)* %out, i32 1
%out.gep.2 = getelementptr i32, i32* %out, i32 2 %out.gep.2 = getelementptr i32, i32 addrspace(5)* %out, i32 2
store i32 9, i32* %out, align 1 store i32 9, i32 addrspace(5)* %out, align 1
store i32 1, i32* %out.gep.1, align 1 store i32 1, i32 addrspace(5)* %out.gep.1, align 1
store i32 23, i32* %out.gep.2, align 1 store i32 23, i32 addrspace(5)* %out.gep.2, align 1
ret void ret void
} }
; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i8_align1( ; ALL-LABEL: @merge_private_store_3_vector_elts_loads_v4i8_align1(
; ALIGNED: store i8 ; ALIGNED: store i8
; ALIGNED: store i8 ; ALIGNED: store i8
; ALIGNED: store i8 ; ALIGNED: store i8
; UNALIGNED: store <3 x i8> ; UNALIGNED: store <3 x i8>
define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i8_align1(i8* %out) #0 { define amdgpu_kernel void @merge_private_store_3_vector_elts_loads_v4i8_align1(i8 addrspace(5)* %out) #0 {
%out.gep.1 = getelementptr i8, i8* %out, i8 1 %out.gep.1 = getelementptr i8, i8 addrspace(5)* %out, i8 1
%out.gep.2 = getelementptr i8, i8* %out, i8 2 %out.gep.2 = getelementptr i8, i8 addrspace(5)* %out, i8 2
store i8 9, i8* %out, align 1 store i8 9, i8 addrspace(5)* %out, align 1
store i8 1, i8* %out.gep.1, align 1 store i8 1, i8 addrspace(5)* %out.gep.1, align 1
store i8 23, i8* %out.gep.2, align 1 store i8 23, i8 addrspace(5)* %out.gep.2, align 1
ret void ret void
} }
attributes #0 = { nounwind } attributes #0 = { nounwind }

test/Transforms/LoopStrengthReduce/AMDGPU/different-addrspace-crash.ll

; RUN: llc < %s | FileCheck %s ; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
target triple = "amdgcn--" target triple = "amdgcn--"
; We need to compile this for a target where we have different address spaces, ; We need to compile this for a target where we have different address spaces,
; and where pointers in those address spaces have different size. ; and where pointers in those address spaces have different size.
; E.g. for amdgcn-- pointers in address space 0 are 32 bits and pointers in ; E.g. for amdgcn-- pointers in address space 0 are 32 bits and pointers in
; address space 1 are 64 bits. ; address space 1 are 64 bits.
; We shouldn't crash. Check that we get a loop with the two stores. ; We shouldn't crash. Check that we get a loop with the two stores.
;CHECK-LABEL: foo: ;CHECK-LABEL: foo:
;CHECK: [[LOOP_LABEL:BB[0-9]+_[0-9]+]]: ;CHECK: [[LOOP_LABEL:BB[0-9]+_[0-9]+]]:
;CHECK: buffer_store_dword ;CHECK: buffer_store_dword
;CHECK: buffer_store_dword ;CHECK: buffer_store_dword
;CHECK: s_branch [[LOOP_LABEL]] ;CHECK: s_branch [[LOOP_LABEL]]
define amdgpu_kernel void @foo() { define amdgpu_kernel void @foo() {
entry: entry:
br label %loop br label %loop
loop: loop:
%idx0 = phi i32 [ %next_idx0, %loop ], [ 0, %entry ] %idx0 = phi i32 [ %next_idx0, %loop ], [ 0, %entry ]
%0 = getelementptr inbounds i32, i32* null, i32 %idx0 %0 = getelementptr inbounds i32, i32 addrspace(5)* null, i32 %idx0
%1 = getelementptr inbounds i32, i32 addrspace(1)* null, i32 %idx0 %1 = getelementptr inbounds i32, i32 addrspace(1)* null, i32 %idx0
store i32 1, i32* %0 store i32 1, i32 addrspace(5)* %0
store i32 7, i32 addrspace(1)* %1 store i32 7, i32 addrspace(1)* %1
%next_idx0 = add nuw nsw i32 %idx0, 1 %next_idx0 = add nuw nsw i32 %idx0, 1
br label %loop br label %loop
} }

test/Transforms/LoopUnroll/AMDGPU/unroll-for-private.ll

; RUN: opt -mtriple=amdgcn-unknown-amdhsa -loop-unroll -S -amdgpu-unroll-threshold-private=20000 %s | FileCheck %s ; RUN: opt -data-layout=A5 -mtriple=amdgcn-unknown-amdhsa -loop-unroll -S -amdgpu-unroll-threshold-private=20000 %s | FileCheck %s
; Check that we full unroll loop to be able to eliminate alloca ; Check that we full unroll loop to be able to eliminate alloca
; CHECK-LABEL: @non_invariant_ind ; CHECK-LABEL: @non_invariant_ind
; CHECK: for.body: ; CHECK: for.body:
; CHECK-NOT: br ; CHECK-NOT: br
; CHECK: store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4 ; CHECK: store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4
; CHECK: ret void ; CHECK: ret void
define amdgpu_kernel void @non_invariant_ind(i32 addrspace(1)* nocapture %a, i32 %x) { define amdgpu_kernel void @non_invariant_ind(i32 addrspace(1)* nocapture %a, i32 %x) {
entry: entry:
%arr = alloca [64 x i32], align 4 %arr = alloca [64 x i32], align 4, addrspace(5)
%tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1
br label %for.body br label %for.body
for.cond.cleanup: ; preds = %for.body for.cond.cleanup: ; preds = %for.body
%arrayidx5 = getelementptr inbounds [64 x i32], [64 x i32]* %arr, i32 0, i32 %x %arrayidx5 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %arr, i32 0, i32 %x
%tmp15 = load i32, i32* %arrayidx5, align 4 %tmp15 = load i32, i32 addrspace(5)* %arrayidx5, align 4
%arrayidx7 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1 %arrayidx7 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1
store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4 store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4
ret void ret void
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%i.015 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i.015 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%idxprom = sext i32 %i.015 to i64 %idxprom = sext i32 %i.015 to i64
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom
%tmp16 = load i32, i32 addrspace(1)* %arrayidx, align 4 %tmp16 = load i32, i32 addrspace(1)* %arrayidx, align 4
%add = add nsw i32 %i.015, %tmp1 %add = add nsw i32 %i.015, %tmp1
%rem = srem i32 %add, 64 %rem = srem i32 %add, 64
%arrayidx3 = getelementptr inbounds [64 x i32], [64 x i32]* %arr, i32 0, i32 %rem %arrayidx3 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %arr, i32 0, i32 %rem
store i32 %tmp16, i32* %arrayidx3, align 4 store i32 %tmp16, i32 addrspace(5)* %arrayidx3, align 4
%inc = add nuw nsw i32 %i.015, 1 %inc = add nuw nsw i32 %i.015, 1
%exitcond = icmp eq i32 %inc, 100 %exitcond = icmp eq i32 %inc, 100
br i1 %exitcond, label %for.cond.cleanup, label %for.body br i1 %exitcond, label %for.cond.cleanup, label %for.body
} }
; Check that we unroll inner loop but not outer ; Check that we unroll inner loop but not outer
; CHECK-LABEL: @invariant_ind ; CHECK-LABEL: @invariant_ind
; CHECK: %[[exitcond:[^ ]+]] = icmp eq i32 %{{.*}}, 32 ; CHECK: %[[exitcond:[^ ]+]] = icmp eq i32 %{{.*}}, 32
; CHECK: br i1 %[[exitcond]] ; CHECK: br i1 %[[exitcond]]
; CHECK-NOT: icmp eq i32 %{{.*}}, 100 ; CHECK-NOT: icmp eq i32 %{{.*}}, 100
define amdgpu_kernel void @invariant_ind(i32 addrspace(1)* nocapture %a, i32 %x) { define amdgpu_kernel void @invariant_ind(i32 addrspace(1)* nocapture %a, i32 %x) {
entry: entry:
%arr = alloca [64 x i32], align 4 %arr = alloca [64 x i32], align 4, addrspace(5)
%tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1
br label %for.cond2.preheader br label %for.cond2.preheader
for.cond2.preheader: ; preds = %for.cond.cleanup5, %entry for.cond2.preheader: ; preds = %for.cond.cleanup5, %entry
%i.026 = phi i32 [ 0, %entry ], [ %inc10, %for.cond.cleanup5 ] %i.026 = phi i32 [ 0, %entry ], [ %inc10, %for.cond.cleanup5 ]
%idxprom = sext i32 %i.026 to i64 %idxprom = sext i32 %i.026 to i64
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom
%tmp15 = load i32, i32 addrspace(1)* %arrayidx, align 4 %tmp15 = load i32, i32 addrspace(1)* %arrayidx, align 4
br label %for.body6 br label %for.body6
for.cond.cleanup: ; preds = %for.cond.cleanup5 for.cond.cleanup: ; preds = %for.cond.cleanup5
%arrayidx13 = getelementptr inbounds [64 x i32], [64 x i32]* %arr, i32 0, i32 %x %arrayidx13 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %arr, i32 0, i32 %x
%tmp16 = load i32, i32* %arrayidx13, align 4 %tmp16 = load i32, i32 addrspace(5)* %arrayidx13, align 4
%arrayidx15 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1 %arrayidx15 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1
store i32 %tmp16, i32 addrspace(1)* %arrayidx15, align 4 store i32 %tmp16, i32 addrspace(1)* %arrayidx15, align 4
ret void ret void
for.cond.cleanup5: ; preds = %for.body6 for.cond.cleanup5: ; preds = %for.body6
%inc10 = add nuw nsw i32 %i.026, 1 %inc10 = add nuw nsw i32 %i.026, 1
%exitcond27 = icmp eq i32 %inc10, 32 %exitcond27 = icmp eq i32 %inc10, 32
br i1 %exitcond27, label %for.cond.cleanup, label %for.cond2.preheader br i1 %exitcond27, label %for.cond.cleanup, label %for.cond2.preheader
for.body6: ; preds = %for.body6, %for.cond2.preheader for.body6: ; preds = %for.body6, %for.cond2.preheader
%j.025 = phi i32 [ 0, %for.cond2.preheader ], [ %inc, %for.body6 ] %j.025 = phi i32 [ 0, %for.cond2.preheader ], [ %inc, %for.body6 ]
%add = add nsw i32 %j.025, %tmp1 %add = add nsw i32 %j.025, %tmp1
%rem = srem i32 %add, 64 %rem = srem i32 %add, 64
%arrayidx8 = getelementptr inbounds [64 x i32], [64 x i32]* %arr, i32 0, i32 %rem %arrayidx8 = getelementptr inbounds [64 x i32], [64 x i32] addrspace(5)* %arr, i32 0, i32 %rem
store i32 %tmp15, i32* %arrayidx8, align 4 store i32 %tmp15, i32 addrspace(5)* %arrayidx8, align 4
%inc = add nuw nsw i32 %j.025, 1 %inc = add nuw nsw i32 %j.025, 1
%exitcond = icmp eq i32 %inc, 100 %exitcond = icmp eq i32 %inc, 100
br i1 %exitcond, label %for.cond.cleanup5, label %for.body6 br i1 %exitcond, label %for.cond.cleanup5, label %for.body6
} }
; Check we do not enforce unroll if alloca is too big ; Check we do not enforce unroll if alloca is too big
; CHECK-LABEL: @too_big ; CHECK-LABEL: @too_big
; CHECK: for.body: ; CHECK: for.body:
; CHECK: icmp eq i32 %{{.*}}, 100 ; CHECK: icmp eq i32 %{{.*}}, 100
; CHECK: br ; CHECK: br
define amdgpu_kernel void @too_big(i32 addrspace(1)* nocapture %a, i32 %x) { define amdgpu_kernel void @too_big(i32 addrspace(1)* nocapture %a, i32 %x) {
entry: entry:
%arr = alloca [256 x i32], align 4 %arr = alloca [256 x i32], align 4, addrspace(5)
%tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1
br label %for.body br label %for.body
for.cond.cleanup: ; preds = %for.body for.cond.cleanup: ; preds = %for.body
%arrayidx5 = getelementptr inbounds [256 x i32], [256 x i32]* %arr, i32 0, i32 %x %arrayidx5 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(5)* %arr, i32 0, i32 %x
%tmp15 = load i32, i32* %arrayidx5, align 4 %tmp15 = load i32, i32 addrspace(5)* %arrayidx5, align 4
%arrayidx7 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1 %arrayidx7 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1
store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4 store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4
ret void ret void
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%i.015 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i.015 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%idxprom = sext i32 %i.015 to i64 %idxprom = sext i32 %i.015 to i64
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom
%tmp16 = load i32, i32 addrspace(1)* %arrayidx, align 4 %tmp16 = load i32, i32 addrspace(1)* %arrayidx, align 4
%add = add nsw i32 %i.015, %tmp1 %add = add nsw i32 %i.015, %tmp1
%rem = srem i32 %add, 64 %rem = srem i32 %add, 64
%arrayidx3 = getelementptr inbounds [256 x i32], [256 x i32]* %arr, i32 0, i32 %rem %arrayidx3 = getelementptr inbounds [256 x i32], [256 x i32] addrspace(5)* %arr, i32 0, i32 %rem
store i32 %tmp16, i32* %arrayidx3, align 4 store i32 %tmp16, i32 addrspace(5)* %arrayidx3, align 4
%inc = add nuw nsw i32 %i.015, 1 %inc = add nuw nsw i32 %i.015, 1
%exitcond = icmp eq i32 %inc, 100 %exitcond = icmp eq i32 %inc, 100
br i1 %exitcond, label %for.cond.cleanup, label %for.body br i1 %exitcond, label %for.cond.cleanup, label %for.body
} }
; Check we do not enforce unroll if alloca is dynamic ; Check we do not enforce unroll if alloca is dynamic
; CHECK-LABEL: @dynamic_size_alloca( ; CHECK-LABEL: @dynamic_size_alloca(
; CHECK: alloca i32, i32 %n ; CHECK: alloca i32, i32 %n
; CHECK: for.body: ; CHECK: for.body:
; CHECK: icmp eq i32 %{{.*}}, 100 ; CHECK: icmp eq i32 %{{.*}}, 100
; CHECK: br ; CHECK: br
define amdgpu_kernel void @dynamic_size_alloca(i32 addrspace(1)* nocapture %a, i32 %n, i32 %x) { define amdgpu_kernel void @dynamic_size_alloca(i32 addrspace(1)* nocapture %a, i32 %n, i32 %x) {
entry: entry:
%arr = alloca i32, i32 %n, align 4 %arr = alloca i32, i32 %n, align 4, addrspace(5)
%tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1 %tmp1 = tail call i32 @llvm.amdgcn.workitem.id.x() #1
br label %for.body br label %for.body
for.cond.cleanup: ; preds = %for.body for.cond.cleanup: ; preds = %for.body
%arrayidx5 = getelementptr inbounds i32, i32* %arr, i32 %x %arrayidx5 = getelementptr inbounds i32, i32 addrspace(5)* %arr, i32 %x
%tmp15 = load i32, i32* %arrayidx5, align 4 %tmp15 = load i32, i32 addrspace(5)* %arrayidx5, align 4
%arrayidx7 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1 %arrayidx7 = getelementptr inbounds i32, i32 addrspace(1)* %a, i32 %tmp1
store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4 store i32 %tmp15, i32 addrspace(1)* %arrayidx7, align 4
ret void ret void
for.body: ; preds = %for.body, %entry for.body: ; preds = %for.body, %entry
%i.015 = phi i32 [ 0, %entry ], [ %inc, %for.body ] %i.015 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%idxprom = sext i32 %i.015 to i64 %idxprom = sext i32 %i.015 to i64
%arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom %arrayidx = getelementptr inbounds i32, i32 addrspace(1)* %a, i64 %idxprom
%tmp16 = load i32, i32 addrspace(1)* %arrayidx, align 4 %tmp16 = load i32, i32 addrspace(1)* %arrayidx, align 4
%add = add nsw i32 %i.015, %tmp1 %add = add nsw i32 %i.015, %tmp1
%rem = srem i32 %add, 64 %rem = srem i32 %add, 64
%arrayidx3 = getelementptr inbounds i32, i32* %arr, i32 %rem %arrayidx3 = getelementptr inbounds i32, i32 addrspace(5)* %arr, i32 %rem
store i32 %tmp16, i32* %arrayidx3, align 4 store i32 %tmp16, i32 addrspace(5)* %arrayidx3, align 4
%inc = add nuw nsw i32 %i.015, 1 %inc = add nuw nsw i32 %i.015, 1
%exitcond = icmp eq i32 %inc, 100 %exitcond = icmp eq i32 %inc, 100
br i1 %exitcond, label %for.cond.cleanup, label %for.body br i1 %exitcond, label %for.cond.cleanup, label %for.body
} }
declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1 declare i8 addrspace(2)* @llvm.amdgcn.dispatch.ptr() #1
declare i32 @llvm.amdgcn.workitem.id.x() #1 declare i32 @llvm.amdgcn.workitem.id.x() #1
declare i32 @llvm.amdgcn.workgroup.id.x() #1 declare i32 @llvm.amdgcn.workgroup.id.x() #1
declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #1 declare i8 addrspace(2)* @llvm.amdgcn.implicitarg.ptr() #1
attributes #1 = { nounwind readnone } attributes #1 = { nounwind readnone }