DAG: Match truncated rotation (PR35487)

[hans]

Summary

If the truncation has been pushed past the or-node, look through it and truncate afterwards.

[escha]

LGTM, though it'd be interesting to see if there's any other cases where (FOO (ROTATE pattern) [...]) gets torn apart besides FOO == truncate.

[scanon]

Yup, there's likely something more general that we could match, but it's also worth taking this as is.

[efriedma]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4657

Do you need to check that LHS.getOperand(0).getValueType() == RHS.getOperand(0).getValueType()?

[hans]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4657

Sorry, just hit commit before I saw this. You're right, I need to check that.

[hans]

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

4657

r319695

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, const SDLoc &DL) {
   EVT VT = LHS.getValueType();
   if (!TLI.isTypeLegal(VT)) return nullptr;
 
   // The target must have at least one rotate flavor.
   bool HasROTL = TLI.isOperationLegalOrCustom(ISD::ROTL, VT);
   bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT);
   if (!HasROTL && !HasROTR) return nullptr;
 
+  // Check for truncated rotate.
+  if (LHS.getOpcode() == ISD::TRUNCATE && RHS.getOpcode() == ISD::TRUNCATE) {
+    assert(LHS.getValueType() == RHS.getValueType());
+    if (SDNode *Rot = MatchRotate(LHS.getOperand(0), RHS.getOperand(0), DL)) {
+      return DAG.getNode(ISD::TRUNCATE, SDLoc(LHS), LHS.getValueType(),
+                         SDValue(Rot, 0)).getNode();
+    }
+  }
+
   // Match "(X shl/srl V1) & V2" where V2 may not be present.
   SDValue LHSShift;   // The shift.
   SDValue LHSMask;    // AND value if any.
   if (!MatchRotateHalf(LHS, LHSShift, LHSMask))
     return nullptr; // Not part of a rotate.
 
   SDValue RHSShift;   // The shift.
   SDValue RHSMask;    // AND value if any.

test/CodeGen/X86/rotate.ll

 ; 64-NEXT:    retq
   %A = load i8, i8 *%Aptr
   %B = shl i8 %A, 7
   %C = lshr i8 %A, 1
   %D = or i8 %B, %C
   store i8 %D, i8* %Aptr
   ret void
 }
+
+define i64 @truncated_rot(i64 %x, i32 %amt) {
+entry:
+  %sh_prom = zext i32 %amt to i64
+  %shl = shl i64 %x, %sh_prom
+  %sub = sub nsw i32 64, %amt
+  %sh_prom1 = zext i32 %sub to i64
+  %shr = lshr i64 %x, %sh_prom1
+  %or = or i64 %shr, %shl
+  %and = and i64 %or, 4294967295
+  ret i64 %and
+
+; 64-LABEL: truncated_rot:
+; 64:       # %bb.0:
+; 64-NEXT:    movl %esi, %ecx
+; 64-NEXT:    rolq %cl, %rdi
+; 64-NEXT:    movl %edi, %eax
+; 64-NEXT:    retq
+}