[AMDGPU] Convert test/tools/llvm-objdump/AMDGPU/source-lines.ll to amdgiz

[yaxunl]

Summary

This test needs manual conversion.

[kzhuravl]

LGTM.

llvm/trunk/test/tools/llvm-objdump/AMDGPU/source-lines.ll

 ; RUN: sed -e "s,SRC_COMPDIR,%/p/Inputs,g" %s > %t.ll
-; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx800 -filetype=obj -O0 -o %t.o %t.ll
-; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -disassemble -line-numbers %t.o | FileCheck --check-prefix=LINE %t.ll
-; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa -mcpu=gfx800 -disassemble -source %t.o | FileCheck --check-prefix=SOURCE %t.ll
+; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -filetype=obj -O0 -o %t.o %t.ll
+; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -disassemble -line-numbers %t.o | FileCheck --check-prefix=LINE %t.ll
+; RUN: llvm-objdump -triple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx800 -disassemble -source %t.o | FileCheck --check-prefix=SOURCE %t.ll
 
 ; Prologue.
 ; LINE:      source_lines_test:
 ; LINE-NEXT: ; {{.*}}source-lines.cl:1
 ; Kernel.
 ; LINE: ; {{.*}}source-lines.cl:2
 ; LINE: v_mov_b32_e32 v{{[0-9]+}}, 0x777
 ; LINE: ; {{.*}}source-lines.cl:3

 ; SOURCE: ; *Out = var2;
 ; SOURCE: flat_store_dword
 ; Epilogue.
 ; SOURCE:      ; }
 ; SOURCE-NEXT: s_endpgm
 
 ; ModuleID = 'source-lines.cl'
 source_filename = "source-lines.cl"
-target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64"
-target triple = "amdgcn-amd-amdhsa"
+target datalayout = "e-p:32:32-p1:64:64-p2:64:64-p3:32:32-p4:64:64-p5:32:32-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024-v2048:2048-n32:64-A5"
+target triple = "amdgcn-amd-amdhsa-amdgiz"
 
 ; Function Attrs: noinline nounwind
 define amdgpu_kernel void @source_lines_test(i32 addrspace(1)* %Out) #0 !dbg !7 !kernel_arg_addr_space !12 !kernel_arg_access_qual !13 !kernel_arg_type !14 !kernel_arg_base_type !14 !kernel_arg_type_qual !15 {
 entry:
-  %Out.addr = alloca i32 addrspace(1)*, align 4
-  %var0 = alloca i32, align 4
-  %var1 = alloca i32, align 4
-  %var2 = alloca i32, align 4
-  store i32 addrspace(1)* %Out, i32 addrspace(1)** %Out.addr, align 4
-  call void @llvm.dbg.declare(metadata i32 addrspace(1)** %Out.addr, metadata !16, metadata !17), !dbg !18
-  call void @llvm.dbg.declare(metadata i32* %var0, metadata !19, metadata !17), !dbg !20
-  store i32 1911, i32* %var0, align 4, !dbg !20
-  call void @llvm.dbg.declare(metadata i32* %var1, metadata !21, metadata !17), !dbg !22
-  store i32 2184, i32* %var1, align 4, !dbg !22
-  call void @llvm.dbg.declare(metadata i32* %var2, metadata !23, metadata !17), !dbg !24
-  %0 = load i32, i32* %var0, align 4, !dbg !25
-  %1 = load i32, i32* %var1, align 4, !dbg !26
+  %Out.addr = alloca i32 addrspace(1)*, align 4, addrspace(5)
+  %var0 = alloca i32, align 4, addrspace(5)
+  %var1 = alloca i32, align 4, addrspace(5)
+  %var2 = alloca i32, align 4, addrspace(5)
+  store i32 addrspace(1)* %Out, i32 addrspace(1)* addrspace(5)* %Out.addr, align 4
+  call void @llvm.dbg.declare(metadata i32 addrspace(1)* addrspace(5)* %Out.addr, metadata !16, metadata !17), !dbg !18
+  call void @llvm.dbg.declare(metadata i32 addrspace(5)* %var0, metadata !19, metadata !17), !dbg !20
+  store i32 1911, i32 addrspace(5)* %var0, align 4, !dbg !20
+  call void @llvm.dbg.declare(metadata i32 addrspace(5)* %var1, metadata !21, metadata !17), !dbg !22
+  store i32 2184, i32 addrspace(5)* %var1, align 4, !dbg !22
+  call void @llvm.dbg.declare(metadata i32 addrspace(5)* %var2, metadata !23, metadata !17), !dbg !24
+  %0 = load i32, i32 addrspace(5)* %var0, align 4, !dbg !25
+  %1 = load i32, i32 addrspace(5)* %var1, align 4, !dbg !26
   %add = add nsw i32 %0, %1, !dbg !27
-  store i32 %add, i32* %var2, align 4, !dbg !24
-  %2 = load i32, i32* %var2, align 4, !dbg !28
-  %3 = load i32 addrspace(1)*, i32 addrspace(1)** %Out.addr, align 4, !dbg !29
+  store i32 %add, i32 addrspace(5)* %var2, align 4, !dbg !24
+  %2 = load i32, i32 addrspace(5)* %var2, align 4, !dbg !28
+  %3 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(5)* %Out.addr, align 4, !dbg !29
   store i32 %2, i32 addrspace(1)* %3, align 4, !dbg !30
   ret void, !dbg !31
 }
 
 ; Function Attrs: nounwind readnone
 declare void @llvm.dbg.declare(metadata, metadata, metadata) #1
 
 attributes #0 = { noinline nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="gfx700" "target-features"="+fp64-fp16-denormals,-fp32-denormals" "unsafe-fp-math"="false" "use-soft-float"="false" }