clang-format ExecutionDepsFix

[myatsina]

Summary

Clang-format ExecutionDepsFix.
Includes small refactoring to favor early exit.

This change is NFC.

This is the second of 5 patches that fix bugzilla https://bugs.llvm.org/show_bug.cgi?id=33869

Previous patches:
https://reviews.llvm.org/D40330

Next patches:
https://reviews.llvm.org/D40332
https://reviews.llvm.org/D40333
https://reviews.llvm.org/D40334

[MatzeB]

LGTM. In the future feel free to just commit obvious reformatting patches without review.

include/llvm/CodeGen/ExecutionDepsFix.h

struct DomainValue {
   bool hasDomain(unsigned domain) const {
     assert(domain <
                static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
            "undefined behavior");
     return AvailableDomains & (1u << domain);
   }
 
   // Mark domain as available.
-  void addDomain(unsigned domain) {
-    AvailableDomains |= 1u << domain;
-  }
+  void addDomain(unsigned domain) { AvailableDomains |= 1u << domain; }
 
   // Restrict to a single domain available.
-  void setSingleDomain(unsigned domain) {
-    AvailableDomains = 1u << domain;
-  }
+  void setSingleDomain(unsigned domain) { AvailableDomains = 1u << domain; }
 
   // Return bitmask of domains that are available and in mask.
   unsigned getCommonDomains(unsigned mask) const {
     return AvailableDomains & mask;
   }
 
   // First domain available.
   unsigned getFirstDomain() const {
protected:
   virtual void processBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass) = 0;
 
   // Traversal operations
   void runOnBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass);
   bool isBlockDone(MachineBasicBlock *MBB);
   bool traverse(MachineFunction &mf);
 };
 
-
 class ExecutionDomainFix : public MachineFunctionPass, LoopTraversal {
   SpecificBumpPtrAllocator<DomainValue> Allocator;
   SmallVector<DomainValue *, 16> Avail;
 
   const TargetRegisterClass *const RC;
   MachineFunction *MF;
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
public:
   }
 
 private:
   iterator_range<SmallVectorImpl<int>::const_iterator>
   regIndices(unsigned Reg) const;
   // DomainValue allocation.
   DomainValue *alloc(int domain = -1);
   DomainValue *retain(DomainValue *DV) {
-    if (DV) ++DV->Refs;
+    if (DV)
+      ++DV->Refs;
     return DV;
   }
-  void release(DomainValue*);
-  DomainValue *resolve(DomainValue*&);
+  void release(DomainValue *);
+  DomainValue *resolve(DomainValue *&);
 
   // LiveRegs manipulations.
   void setLiveReg(int rx, DomainValue *DV);
   void kill(int rx);
   void force(int rx, unsigned domain);
   void collapse(DomainValue *dv, unsigned domain);
   bool merge(DomainValue *A, DomainValue *B);
 
   // LoopTraversal overrides
   void enterBasicBlock(MachineBasicBlock *) override;
   void leaveBasicBlock(MachineBasicBlock *) override;
   void processBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass) override;
 
   // Instruction processing
   bool visitInstr(MachineInstr *);
   void processDefs(MachineInstr *, bool Kill);
-  void visitSoftInstr(MachineInstr*, unsigned mask);
-  void visitHardInstr(MachineInstr*, unsigned domain);
+  void visitSoftInstr(MachineInstr *, unsigned mask);
+  void visitHardInstr(MachineInstr *, unsigned domain);
 };
 
 class BreakFalseDeps : public MachineFunctionPass, LoopTraversal {
 private:
   MachineFunction *MF;
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
   RegisterClassInfo RegClassInfo;
MachineFunctionProperties getRequiredProperties() const override {
     return MachineFunctionProperties().set(
         MachineFunctionProperties::Property::NoVRegs);
   }
 
 private:
   // Dependency breaking.
   bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
                                 unsigned Pref);
-  bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
-  void processUndefReads(MachineBasicBlock*);
+  bool shouldBreakDependence(MachineInstr *, unsigned OpIdx, unsigned Pref);
+  void processUndefReads(MachineBasicBlock *);
 
   // LoopTraversal overrides.
   void enterBasicBlock(MachineBasicBlock *) override;
   void leaveBasicBlock(MachineBasicBlock *) override;
   void processBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass) override;
 
   // Instruction processing.
   void processDefs(MachineInstr *, bool breakDependency);
 };
 
-} // end namepsace llvm
+} // namespace llvm
 
 #endif // LLVM_CODEGEN_EXECUTIONDEPSFIX_H

lib/CodeGen/ExecutionDepsFix.cpp

 iterator_range<SmallVectorImpl<int>::const_iterator>
 ExecutionDomainFix::regIndices(unsigned Reg) const {
   assert(Reg < AliasMap.size() && "Invalid register");
   const auto &Entry = AliasMap[Reg];
   return make_range(Entry.begin(), Entry.end());
 }
 
 DomainValue *ExecutionDomainFix::alloc(int domain) {
-  DomainValue *dv = Avail.empty() ?
-                      new(Allocator.Allocate()) DomainValue :
-                      Avail.pop_back_val();
+  DomainValue *dv = Avail.empty() ? new (Allocator.Allocate()) DomainValue
+                                  : Avail.pop_back_val();
   if (domain >= 0)
     dv->addDomain(domain);
   assert(dv->Refs == 0 && "Reference count wasn't cleared");
   assert(!dv->Next && "Chained DomainValue shouldn't have been recycled");
   return dv;
 }
 
 /// Release a reference to DV.  When the last reference is released,

 /// Follow the chain of dead DomainValues until a live DomainValue is reached.
 /// Update the referenced pointer when necessary.
 DomainValue *ExecutionDomainFix::resolve(DomainValue *&DVRef) {
   DomainValue *DV = DVRef;
   if (!DV || !DV->Next)
     return DV;
 
   // DV has a chain. Find the end.
-  do DV = DV->Next;
+  do
+    DV = DV->Next;
   while (DV->Next);
 
   // Update DVRef to point to DV.
   retain(DV);
   release(DVRef);
   DVRef = DV;
   return DV;
 }
for (const auto &LI : MBB->liveins()) {
       }
     }
     DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
     return;
   }
 
   // Try to coalesce live-out register units from predecessors.
   for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
-       pe = MBB->pred_end(); pi != pe; ++pi) {
+                                              pe = MBB->pred_end();
+       pi != pe; ++pi) {
     const RegDefInfo &IncomingDefs = OutDefs[(*pi)->getNumber()];
     // Incoming is empty if this is a backedge from a BB
     // we haven't processed yet
     if (!IncomingDefs.size())
       continue;
 
     for (unsigned Unit = 0; Unit < NumRegUnits; ++Unit) {
       // Use the most recent predecessor def for each register unit.
void ExecutionDomainFix::enterBasicBlock(MachineBasicBlock *MBB) {
   // This is the entry block.
   if (MBB->pred_empty()) {
     DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": entry\n");
     return;
   }
 
   // Try to coalesce live-out registers from predecessors.
   for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
-       pe = MBB->pred_end(); pi != pe; ++pi) {
+                                              pe = MBB->pred_end();
+       pi != pe; ++pi) {
     RegsDVInfo &Incoming = OutRegs[(*pi)->getNumber()];
     // Incoming is empty if this is a backedge from a BB
     // we haven't processed yet
     if (Incoming.empty()) {
       continue;
     }
 
     for (unsigned rx = 0; rx != NumRegs; ++rx) {
bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
   return !DomP.first;
 }
 
 /// \brief Helps avoid false dependencies on undef registers by updating the
 /// machine instructions' undef operand to use a register that the instruction
 /// is truly dependent on, or use a register with clearance higher than Pref.
 /// Returns true if it was able to find a true dependency, thus not requiring
 /// a dependency breaking instruction regardless of clearance.
-bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI,
-                                                unsigned OpIdx, unsigned Pref) {
+bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
+                                              unsigned Pref) {
   MachineOperand &MO = MI->getOperand(OpIdx);
   assert(MO.isUndef() && "Expected undef machine operand");
 
   unsigned OriginalReg = MO.getReg();
 
   // Update only undef operands that have reg units that are mapped to one root.
   for (MCRegUnitIterator Unit(OriginalReg, TRI); Unit.isValid(); ++Unit) {
     unsigned NumRoots = 0;

 // Update def-ages for registers defined by MI.
 // If Kill is set, also kill off DomainValues clobbered by the defs.
 //
 // Also break dependencies on partial defs and undef uses.
 void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
   assert(!MI->isDebugValue() && "Won't process debug values");
   const MCInstrDesc &MCID = MI->getDesc();
   for (unsigned i = 0,
                 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
-         i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg())
       continue;
     if (MO.isUse())
       continue;
     for (int rx : regIndices(MO.getReg())) {
       // This instruction explicitly defines rx.
       DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << *MI);
if (Pref) {
       // instruction has a true dependency on that register through another
       // operand - we'll have to wait for it to be available regardless.
       if (!HadTrueDependency && shouldBreakDependence(MI, OpNum, Pref))
         UndefReads.push_back(std::make_pair(MI, OpNum));
     }
   }
   const MCInstrDesc &MCID = MI->getDesc();
   for (unsigned i = 0,
                 e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
-         i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg() || !MO.getReg())
       continue;
     if (MO.isUse())
       continue;
     for (MCRegUnitIterator Unit(MO.getReg(), TRI); Unit.isValid(); ++Unit) {
       // This instruction explicitly defines rx.
       DEBUG(dbgs() << TRI->getName(MO.getReg()) << ":\t" << CurInstr << '\t'
void BreakFalseDeps::processUndefReads(MachineBasicBlock *MBB) {
   }
 }
 
 // A hard instruction only works in one domain. All input registers will be
 // forced into that domain.
 void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
   // Collapse all uses.
   for (unsigned i = mi->getDesc().getNumDefs(),
-                e = mi->getDesc().getNumOperands(); i != e; ++i) {
+                e = mi->getDesc().getNumOperands();
+       i != e; ++i) {
     MachineOperand &mo = mi->getOperand(i);
-    if (!mo.isReg()) continue;
+    if (!mo.isReg())
+      continue;
     for (int rx : regIndices(mo.getReg())) {
       force(rx, domain);
     }
   }
 
   // Kill all defs and force them.
   for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
     MachineOperand &mo = mi->getOperand(i);
-    if (!mo.isReg()) continue;
+    if (!mo.isReg())
+      continue;
     for (int rx : regIndices(mo.getReg())) {
       kill(rx);
       force(rx, domain);
     }
   }
 }
 
 // A soft instruction can be changed to work in other domains given by mask.
 void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
   // Bitmask of available domains for this instruction after taking collapsed
   // operands into account.
   unsigned available = mask;
 
   // Scan the explicit use operands for incoming domains.
   SmallVector<int, 4> used;
   if (!LiveRegs.empty())
     for (unsigned i = mi->getDesc().getNumDefs(),
-                  e = mi->getDesc().getNumOperands(); i != e; ++i) {
+                  e = mi->getDesc().getNumOperands();
+         i != e; ++i) {
       MachineOperand &mo = mi->getOperand(i);
-      if (!mo.isReg()) continue;
+      if (!mo.isReg())
+        continue;
       for (int rx : regIndices(mo.getReg())) {
         DomainValue *dv = LiveRegs[rx];
         if (dv == nullptr)
           continue;
         // Bitmask of domains that dv and available have in common.
         unsigned common = dv->getCommonDomains(available);
         // Is it possible to use this collapsed register for free?
         if (dv->isCollapsed()) {
           // Restrict available domains to the ones in common with the operand.
           // If there are no common domains, we must pay the cross-domain
           // penalty for this operand.
-          if (common) available = common;
+          if (common)
+            available = common;
         } else if (common)
           // Open DomainValue is compatible, save it for merging.
           used.push_back(rx);
         else
           // Open DomainValue is not compatible with instruction. It is useless
           // now.
           kill(rx);
       }
if (!dv) {
     dv->AvailableDomains = available;
   }
   dv->Instrs.push_back(mi);
 
   // Finally set all defs and non-collapsed uses to dv. We must iterate through
   // all the operators, including imp-def ones.
   for (MachineInstr::mop_iterator ii = mi->operands_begin(),
                                   ee = mi->operands_end();
-                                  ii != ee; ++ii) {
     MachineOperand &mo = *ii;
-    if (!mo.isReg()) continue;
+    if (!mo.isReg())
+      continue;
     for (int rx : regIndices(mo.getReg())) {
       if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx] != dv)) {
         kill(rx);
         setLiveReg(rx, dv);
       }
     }
   }
 }
 
 void ExecutionDomainFix::processBasicBlock(MachineBasicBlock *MBB,
                                            bool PrimaryPass) {
   // Go over the instructions.
   // Kill domain values only in the primary traversal pass.
   for (MachineInstr &MI : *MBB) {
-    if (!MI.isDebugValue()) {
-      bool Kill = false;
-      if (PrimaryPass)
-        Kill = visitInstr(&MI);
-      processDefs(&MI, Kill);
-    }
-  }
-}
+    if (MI.isDebugValue())
+      continue;
 
 void BreakFalseDeps::processBasicBlock(MachineBasicBlock *MBB,
-                                         bool PrimaryPass) {
   // If this block is not done, it makes little sense to make any decisions
   // based on clearance information. We need to make a second pass anyway,
   // and by then we'll have better information, so we can avoid doing the work
   // to try and break dependencies now.
   bool breakDependency = isBlockDone(MBB);
   for (MachineInstr &MI : *MBB) {
-    if (!MI.isDebugValue()) {
-      processDefs(&MI, breakDependency);
-    }
-  }
+    if (MI.isDebugValue())
+      continue;
   if (breakDependency)
     processUndefReads(MBB);
 }
 
 /// Includes the general logic of handeling a basic block, activating sub phases
 /// that are implemented by the derived classes.
 void LoopTraversal::runOnBasicBlock(MachineBasicBlock *MBB, bool PrimaryPass) {
   enterBasicBlock(MBB);
bool LoopTraversal::traverse(MachineFunction &mf) {
    *  Note that we avoid processing D twice, because we can entirely process
    *  the predecessors before getting to D. We call a block that is ready
    *  for its second round of processing `done` (isBlockDone). Once we finish
    *  processing some block, we update the counters in MBBInfos and re-process
    *  any successors that are now done.
    */
 
   MachineBasicBlock *Entry = &*mf.begin();
-  ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
+  ReversePostOrderTraversal<MachineBasicBlock *> RPOT(Entry);
   SmallVector<MachineBasicBlock *, 4> Workqueue;
-  for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
-         MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
+  for (ReversePostOrderTraversal<MachineBasicBlock *>::rpo_iterator
+           MBBI = RPOT.begin(),
+           MBBE = RPOT.end();
+       MBBI != MBBE; ++MBBI) {
     MachineBasicBlock *MBB = *MBBI;
     // N.B: IncomingProcessed and IncomingCompleted were already updated while
     // processing this block's predecessors.
     MBBInfos[MBB].PrimaryCompleted = true;
     MBBInfos[MBB].PrimaryIncoming = MBBInfos[MBB].IncomingProcessed;
     bool Primary = true;
     Workqueue.push_back(MBB);
     while (!Workqueue.empty()) {