clang-format ExecutionDepsFix

[myatsina]

Summary

Clang-format ExecutionDepsFix.
Includes small refactoring to favor early exit.

This change is NFC.

This is the second of 5 patches that fix bugzilla https://bugs.llvm.org/show_bug.cgi?id=33869

Previous patches:
https://reviews.llvm.org/D40330

Next patches:
https://reviews.llvm.org/D40332
https://reviews.llvm.org/D40333
https://reviews.llvm.org/D40334

[MatzeB]

LGTM. In the future feel free to just commit obvious reformatting patches without review.

llvm/trunk/include/llvm/CodeGen/ExecutionDepsFix.h

 /// This pass changes the variant instructions to minimize domain crossings.
 //
 //===----------------------------------------------------------------------===//
 
 #ifndef LLVM_CODEGEN_EXECUTIONDEPSFIX_H
 #define LLVM_CODEGEN_EXECUTIONDEPSFIX_H
 
 #include "llvm/ADT/DenseMap.h"
-#include "llvm/ADT/iterator_range.h"
 #include "llvm/ADT/SmallVector.h"
+#include "llvm/ADT/iterator_range.h"
 #include "llvm/CodeGen/LivePhysRegs.h"
-#include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/RegisterClassInfo.h"
-#include "llvm/Pass.h"
-#include "llvm/Support/Allocator.h"
-#include "llvm/Support/MathExtras.h"
-#include <cassert>
-#include <limits>
-#include <utility>
-#include <vector>
 
 namespace llvm {
 
 class MachineBasicBlock;
 class MachineInstr;
 class TargetInstrInfo;
 
 /// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
struct TraversedMBBInfo {
     bool IsDone = true;
 
     TraversedMBBInfo(MachineBasicBlock *BB = nullptr, bool Primary = true,
                      bool Done = true)
         : MBB(BB), PrimaryPass(Primary), IsDone(Done) {}
   };
   LoopTraversal() {}
 
-  SmallVector<TraversedMBBInfo, 4> traverse(MachineFunction &MF);
+  typedef SmallVector<TraversedMBBInfo, 4> TraversalOrder;
+  TraversalOrder traverse(MachineFunction &MF);
 
 private:
   bool isBlockDone(MachineBasicBlock *MBB);
 
 };
 
 /// This class provides the reaching def analysis.
 class ReachingDefAnalysis : public MachineFunctionPass {
 private:
   MachineFunction *MF;
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
-  RegisterClassInfo RegClassInfo;
   unsigned NumRegUnits;
   LiveReg *LiveRegs;
 
   // Keeps clearance information for all registers. Note that this
   // is different from the usual definition notion of liveness. The CPU
   // doesn't care whether or not we consider a register killed.
   using OutRegsInfoMap = DenseMap<MachineBasicBlock *, LiveReg *>;
   OutRegsInfoMap MBBOutRegsInfos;
private:
   /// All reaching defs of a given RegUnit for a given MBB.
   using MBBRegUnitDefs = SmallVector<int, 1>;
   /// All reaching defs of all reg units for a given MBB
   using MBBDefsInfo = std::vector<MBBRegUnitDefs>;
   /// All reaching defs of all reg units for a all MBBs
   using MBBReachingDefsInfo = SmallVector<MBBDefsInfo, 4>;
   MBBReachingDefsInfo MBBReachingDefs;
 
+  // Default values are 'nothing happened a long time ago'.
+  const int ReachingDedDefaultVal = -(1 << 20);
+
 public:
   static char ID; // Pass identification, replacement for typeid
 
   ReachingDefAnalysis() : MachineFunctionPass(ID) {
     initializeReachingDefAnalysisPass(*PassRegistry::getPassRegistry());
   }
   void releaseMemory() override;
 

 class ExecutionDomainFix : public MachineFunctionPass {
   SpecificBumpPtrAllocator<DomainValue> Allocator;
   SmallVector<DomainValue*,16> Avail;
 
   const TargetRegisterClass *const RC;
   MachineFunction *MF;
   const TargetInstrInfo *TII;
   const TargetRegisterInfo *TRI;
-  RegisterClassInfo RegClassInfo;
   std::vector<SmallVector<int, 1>> AliasMap;
   const unsigned NumRegs;
   LiveReg *LiveRegs;
   // Keeps domain information for all registers. Note that this
   // is different from the usual definition notion of liveness. The CPU
   // doesn't care whether or not we consider a register killed.
   using OutRegsInfoMap = DenseMap<MachineBasicBlock *, LiveReg *>;
   OutRegsInfoMap MBBOutRegsInfos;

llvm/trunk/lib/CodeGen/ExecutionDepsFix.cpp

 //===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/CodeGen/ExecutionDepsFix.h"
-
 #include "llvm/ADT/PostOrderIterator.h"
-#include "llvm/ADT/iterator_range.h"
-#include "llvm/CodeGen/LivePhysRegs.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/CodeGen/RegisterClassInfo.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
-#include "llvm/CodeGen/TargetSubtargetInfo.h"
-#include "llvm/Support/Allocator.h"
-#include "llvm/Support/Debug.h"
-#include "llvm/Support/raw_ostream.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "execution-deps-fix"
 
 char ReachingDefAnalysis::ID = 0;
 INITIALIZE_PASS(ReachingDefAnalysis, "reaching-deps-analysis",
                 "ReachingDefAnalysis", false, true)
void ReachingDefAnalysis::enterBasicBlock(
 
   // Reset instruction counter in each basic block.
   CurInstr = 0;
 
   // Set up LiveRegs to represent registers entering MBB.
   if (!LiveRegs)
     LiveRegs = new LiveReg[NumRegUnits];
 
-  // Default values are 'nothing happened a long time ago'.
-  for (unsigned rx = 0; rx != NumRegUnits; ++rx) {
-    LiveRegs[rx].Def = -(1 << 20);
+  for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
+    LiveRegs[Unit].Def = ReachingDedDefaultVal;
   }
 
   // This is the entry block.
   if (MBB->pred_empty()) {
     for (const auto &LI : MBB->liveins()) {
-      for (MCRegUnitIterator rx(LI.PhysReg, TRI); rx.isValid(); ++rx) {
+      for (MCRegUnitIterator Unit(LI.PhysReg, TRI); Unit.isValid(); ++Unit) {
         // Treat function live-ins as if they were defined just before the first
         // instruction.  Usually, function arguments are set up immediately
         // before the call.
-        LiveRegs[*rx].Def = -1;
-        MBBReachingDefs[MBBNumber][*rx].push_back(LiveRegs[*rx].Def);
+        LiveRegs[*Unit].Def = -1;
+        MBBReachingDefs[MBBNumber][*Unit].push_back(LiveRegs[*Unit].Def);
       }
     }
     DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
     return;
   }
 
   // Try to coalesce live-out registers from predecessors.
-  for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
-       pe = MBB->pred_end(); pi != pe; ++pi) {
-    auto fi = MBBOutRegsInfos.find(*pi);
+  for (MachineBasicBlock* pred : MBB->predecessors()) {
+    auto fi = MBBOutRegsInfos.find(pred);
     assert(fi != MBBOutRegsInfos.end() &&
            "Should have pre-allocated MBBInfos for all MBBs");
     LiveReg *Incoming = fi->second;
     // Incoming is null if this is a backedge from a BB
     // we haven't processed yet
-    if (Incoming == nullptr) {
+    if (Incoming == nullptr)
       continue;
-    }
 
-    for (unsigned rx = 0; rx != NumRegUnits; ++rx) {
+    for (unsigned Unit = 0; Unit != NumRegUnits; ++Unit) {
       // Use the most recent predecessor def for each register.
-      LiveRegs[rx].Def = std::max(LiveRegs[rx].Def, Incoming[rx].Def);
-      if ((LiveRegs[rx].Def  != -(1 << 20))) 
-        MBBReachingDefs[MBBNumber][rx].push_back(LiveRegs[rx].Def);
+      LiveRegs[Unit].Def = std::max(LiveRegs[Unit].Def, Incoming[Unit].Def);
+      if ((LiveRegs[Unit].Def  != ReachingDedDefaultVal))
+        MBBReachingDefs[MBBNumber][Unit].push_back(LiveRegs[Unit].Def);
     }
   }
 
   DEBUG(
       dbgs() << printMBBReference(*MBB)
              << (!TraversedMBB.IsDone ? ": incomplete\n" : ": all preds known\n"));
 }
 
 /// Set up LiveRegs by merging predecessor live-out values.
 void ExecutionDomainFix::enterBasicBlock(
     const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
 
   MachineBasicBlock *MBB = TraversedMBB.MBB;
 
   // Set up LiveRegs to represent registers entering MBB.
   if (!LiveRegs)
     LiveRegs = new LiveReg[NumRegs];
 
-  // Default values are 'nothing happened a long time ago'.
   for (unsigned rx = 0; rx != NumRegs; ++rx) {
     LiveRegs[rx].Value = nullptr;
   }
 
   // This is the entry block.
   if (MBB->pred_empty()) {
     DEBUG(dbgs() << printMBBReference(*MBB) << ": entry\n");
     return;
   }
 
   // Try to coalesce live-out registers from predecessors.
-  for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
-       pe = MBB->pred_end(); pi != pe; ++pi) {
-    auto fi = MBBOutRegsInfos.find(*pi);
+  for (MachineBasicBlock* pred : MBB->predecessors()) {
+    auto fi = MBBOutRegsInfos.find(pred);
     assert(fi != MBBOutRegsInfos.end() &&
       "Should have pre-allocated MBBInfos for all MBBs");
     LiveReg *Incoming = fi->second;
     // Incoming is null if this is a backedge from a BB
     // we haven't processed yet
-    if (Incoming == nullptr) {
+    if (Incoming == nullptr)
       continue;
-    }
 
     for (unsigned rx = 0; rx != NumRegs; ++rx) {
       DomainValue *pdv = resolve(Incoming[rx].Value);
       if (!pdv)
         continue;
       if (!LiveRegs[rx].Value) {
         setLiveReg(rx, pdv);
         continue;
for (MachineOperand &CurrMO : MI->operands()) {
     return true;
   }
 
   // Go over all registers in the register class and find the register with
   // max clearance or clearance higher than Pref.
   unsigned MaxClearance = 0;
   unsigned MaxClearanceReg = OriginalReg;
   ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC);
-  for (auto Reg : Order) {
+  for (MCPhysReg Reg : Order) {
     unsigned Clearance = RDA->getClearance(MI, Reg);
     if (Clearance <= MaxClearance)
       continue;
     MaxClearance = Clearance;
     MaxClearanceReg = Reg;
 
     if (MaxClearance > Pref)
       break;
void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
   for (unsigned i = 0,
          e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
          i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg() || !MO.getReg())
       continue;
     if (MO.isUse())
       continue;
-    for (MCRegUnitIterator rx(MO.getReg(), TRI); rx.isValid(); ++rx) {
-      // This instruction explicitly defines rx.
+    for (MCRegUnitIterator Unit(MO.getReg(), TRI); Unit.isValid(); ++Unit) {
+      // This instruction explicitly defines the current reg unit.
       DEBUG(dbgs() << printReg(MO.getReg(), TRI) << ":\t" << CurInstr << '\t'
                    << *MI);
 
       // How many instructions since this reg unit was last written?
-      LiveRegs[*rx].Def = CurInstr;
-      MBBReachingDefs[MBBNumber][*rx].push_back(CurInstr);
+      LiveRegs[*Unit].Def = CurInstr;
+      MBBReachingDefs[MBBNumber][*Unit].push_back(CurInstr);
     }
   }
   InstIds[MI] = CurInstr;
   ++CurInstr;
 }
 
 // Update def-ages for registers defined by MI.
 // Also break dependencies on partial defs and undef uses.
for (unsigned i = 0,
          e = MI->isVariadic() ? MI->getNumOperands() : MCID.getNumDefs();
          i != e; ++i) {
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg() || !MO.getReg())
       continue;
     if (MO.isUse())
       continue;
     // Check clearance before partial register updates.
-    // Call breakDependence before setting LiveRegs[rx].Def.
     unsigned Pref = TII->getPartialRegUpdateClearance(*MI, i, TRI);
     if (Pref && shouldBreakDependence(MI, i, Pref))
       TII->breakPartialRegDependency(*MI, i, TRI);
   }
 }
 
 /// \break Break false dependencies on undefined register reads.
 ///
void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
   if (!dv) {
     dv = alloc();
     dv->AvailableDomains = available;
   }
   dv->Instrs.push_back(mi);
 
   // Finally set all defs and non-collapsed uses to dv. We must iterate through
   // all the operators, including imp-def ones.
-  for (MachineInstr::mop_iterator ii = mi->operands_begin(),
-                                  ee = mi->operands_end();
-                                  ii != ee; ++ii) {
-    MachineOperand &mo = *ii;
+  for (MachineOperand &mo : mi->operands()) {
     if (!mo.isReg()) continue;
     for (int rx : regIndices(mo.getReg())) {
       if (!LiveRegs[rx].Value || (mo.isDef() && LiveRegs[rx].Value != dv)) {
         kill(rx);
         setLiveReg(rx, dv);
       }
     }
   }

 
 void BreakFalseDeps::processBasicBlock(MachineBasicBlock* MBB) {
   UndefReads.clear();
   // If this block is not done, it makes little sense to make any decisions
   // based on clearance information. We need to make a second pass anyway,
   // and by then we'll have better information, so we can avoid doing the work
   // to try and break dependencies now.
   for (MachineInstr &MI : *MBB) {
-    if (!MI.isDebugValue()) {
+    if (!MI.isDebugValue())
       processDefs(&MI);
-    }
-  }
   processUndefReads(MBB);
 }
 
 bool LoopTraversal::isBlockDone(MachineBasicBlock *MBB) {
   return MBBInfos[MBB].PrimaryCompleted &&
          MBBInfos[MBB].IncomingCompleted == MBBInfos[MBB].PrimaryIncoming &&
          MBBInfos[MBB].IncomingProcessed == MBB->pred_size();
 }
 
-SmallVector<LoopTraversal::TraversedMBBInfo, 4>
+LoopTraversal::TraversalOrder
 LoopTraversal::traverse(MachineFunction &MF) {
   // Initialize the MMBInfos
-  for (auto &MBB : MF) {
+  for (MachineBasicBlock &MBB : MF) {
     MBBInfo InitialInfo;
     MBBInfos.insert(std::make_pair(&MBB, InitialInfo));
   }
 
   /*
    *  We want to visit every instruction in every basic block in order to update
    *  it's execution domain or break any false dependencies. However, for the
    *  dependency breaking, we need to know clearances from all predecessors
LoopTraversal::traverse(MachineFunction &MF) {
    *  processing some block, we update the counters in MBBInfos and re-process
    *  any successors that are now done.
    */
 
   MachineBasicBlock *Entry = &*MF.begin();
   ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
   SmallVector<MachineBasicBlock *, 4> Workqueue;
   SmallVector<TraversedMBBInfo, 4> MBBTraversalOrder;
-  for (ReversePostOrderTraversal<MachineBasicBlock*>::rpo_iterator
-         MBBI = RPOT.begin(), MBBE = RPOT.end(); MBBI != MBBE; ++MBBI) {
-    MachineBasicBlock *MBB = *MBBI;
+  for (MachineBasicBlock *MBB : RPOT) {
     // N.B: IncomingProcessed and IncomingCompleted were already updated while
     // processing this block's predecessors.
     MBBInfos[MBB].PrimaryCompleted = true;
     MBBInfos[MBB].PrimaryIncoming = MBBInfos[MBB].IncomingProcessed;
     bool Primary = true;
     Workqueue.push_back(MBB);
     while (!Workqueue.empty()) {
       MachineBasicBlock *ActiveMBB = &*Workqueue.back();
       Workqueue.pop_back();
       bool Done = isBlockDone(ActiveMBB);
       MBBTraversalOrder.push_back(TraversedMBBInfo(ActiveMBB, Primary, Done));
-      for (auto *Succ : ActiveMBB->successors()) {
+      for (MachineBasicBlock *Succ : ActiveMBB->successors()) {
         if (!isBlockDone(Succ)) {
-          if (Primary) {
+          if (Primary)
             MBBInfos[Succ].IncomingProcessed++;
-          }
-          if (Done) {
+          if (Done)
             MBBInfos[Succ].IncomingCompleted++;
-          }
-          if (isBlockDone(Succ)) {
+          if (isBlockDone(Succ))
             Workqueue.push_back(Succ);
-          }
-        }
-      }
       Primary = false;
     }
   }
 
   // We need to go through again and finalize any blocks that are not done yet.
   // This is possible if blocks have dead predecessors, so we didn't visit them
   // above.
-  for (ReversePostOrderTraversal<MachineBasicBlock *>::rpo_iterator
-           MBBI = RPOT.begin(),
-           MBBE = RPOT.end();
-       MBBI != MBBE; ++MBBI) {
-    MachineBasicBlock *MBB = *MBBI;
-    if (!isBlockDone(MBB)) {
+  for (MachineBasicBlock *MBB : RPOT) {
+    if (!isBlockDone(MBB))
       MBBTraversalOrder.push_back(TraversedMBBInfo(MBB, false, true));
       // Don't update successors here. We'll get to them anyway through this
       // loop.
-    }
-  }
 
   MBBInfos.clear();
 
   return MBBTraversalOrder;
 }
 
 bool ExecutionDomainFix::runOnMachineFunction(MachineFunction &mf) {
   if (skipFunction(mf.getFunction()))
     return false;
   MF = &mf;
   TII = MF->getSubtarget().getInstrInfo();
   TRI = MF->getSubtarget().getRegisterInfo();
   LiveRegs = nullptr;
   assert(NumRegs == RC->getNumRegs() && "Bad regclass");
 
-  RDA = &getAnalysis<ReachingDefAnalysis>();
-
   DEBUG(dbgs() << "********** FIX EXECUTION DOMAIN: "
                << TRI->getRegClassName(RC) << " **********\n");
 
   // If no relevant registers are used in the function, we can skip it
   // completely.
   bool anyregs = false;
   const MachineRegisterInfo &MRI = mf.getRegInfo();
   for (unsigned Reg : *RC) {
     if (MRI.isPhysRegUsed(Reg)) {
       anyregs = true;
       break;
     }
   }
   if (!anyregs) return false;
 
+  RDA = &getAnalysis<ReachingDefAnalysis>();
+
   // Initialize the AliasMap on the first use.
   if (AliasMap.empty()) {
     // Given a PhysReg, AliasMap[PhysReg] returns a list of indices into RC and
     // therefore the LiveRegs array.
     AliasMap.resize(TRI->getNumRegs());
     for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
       for (MCRegAliasIterator AI(RC->getRegister(i), TRI, true);
            AI.isValid(); ++AI)
         AliasMap[*AI].push_back(i);
   }
 
   // Initialize the MBBOutRegsInfos
-  for (auto &MBB : mf) {
+  for (MachineBasicBlock &MBB : mf) {
     MBBOutRegsInfos.insert(std::make_pair(&MBB, nullptr));
   }
 
   // Traverse the basic blocks.
   LoopTraversal Traversal;
-  SmallVector<LoopTraversal::TraversedMBBInfo, 4> TraversedMBBInfoOrder =
-      Traversal.traverse(mf);
-  for (auto TraversedMBB : TraversedMBBInfoOrder) {
+  LoopTraversal::TraversalOrder TraversedMBBOrder = Traversal.traverse(mf);
+  for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder) {
     processBasicBlock(TraversedMBB);
   }
 
   for (auto MBBOutRegs : MBBOutRegsInfos) {
     if (!MBBOutRegs.second)
       continue;
     for (unsigned i = 0, e = NumRegs; i != e; ++i)
       if (MBBOutRegs.second[i].Value)
bool ReachingDefAnalysis::runOnMachineFunction(MachineFunction &mf) {
   LiveRegs = nullptr;
   NumRegUnits = TRI->getNumRegUnits();
 
   MBBReachingDefs.resize(mf.getNumBlockIDs());
 
   DEBUG(dbgs() << "********** REACHING DEFINITION ANALYSIS **********\n");
 
   // Initialize the MBBOutRegsInfos
-  for (auto &MBB : mf) {
+  for (MachineBasicBlock &MBB : mf) {
     MBBOutRegsInfos.insert(std::make_pair(&MBB, nullptr));
   }
 
   // Traverse the basic blocks.
   LoopTraversal Traversal;
-  SmallVector<LoopTraversal::TraversedMBBInfo, 4> TraversedMBBInfoOrder =
-      Traversal.traverse(mf);
-  for (auto TraversedMBB : TraversedMBBInfoOrder) {
+  LoopTraversal::TraversalOrder TraversedMBBOrder = Traversal.traverse(mf);
+  for (LoopTraversal::TraversedMBBInfo TraversedMBB : TraversedMBBOrder) {
     processBasicBlock(TraversedMBB);
   }
 
   // Sorting all reaching defs found for a ceartin reg unit in a given BB.
   for (MBBDefsInfo &MBBDefs : MBBReachingDefs) {
     for (MBBRegUnitDefs &RegUnitDefs : MBBDefs)
       std::sort(RegUnitDefs.begin(), RegUnitDefs.end());
   }
for (MachineBasicBlock &MBB : mf) {
     processBasicBlock(&MBB);
   }
 
   return false;
 }
 
 int ReachingDefAnalysis::getReachingDef(MachineInstr *MI, int PhysReg) {
   int InstId = InstIds[MI];
-  int DefRes = -(1 << 20);
+  int DefRes = ReachingDedDefaultVal;
   int MBBNumber = MI->getParent()->getNumber();
-  int LatestDef = -(1 << 20);
+  int LatestDef = ReachingDedDefaultVal;
   for (MCRegUnitIterator Unit(PhysReg, TRI); Unit.isValid(); ++Unit) {
     for (int Def : MBBReachingDefs[MBBNumber][*Unit]) {
       if (Def >= InstId)
         break;
       DefRes = Def;
     }
     LatestDef = std::max(LatestDef, DefRes);
   }
   return LatestDef;
 }
 
 int ReachingDefAnalysis::getClearance(MachineInstr *MI, MCPhysReg PhysReg) {
   return InstIds[MI] - getReachingDef(MI, PhysReg);
 }