[ARM] Fix an off-by-one error when restoring LR for 16-bit Thumb

[chill]

Summary

This commit https://reviews.llvm.org/rL318143 computes incorrectly to offset to restore LR from.

The number of tPOP operands is 2 (condition) + 2 (implicit def and use of SP) + count of the popped registers. We need to load LR from just past the last register, hence the correct offset should be either getNumOperands() - 4 and getNumExplicitOperands() - 2 (multiplied by 4).

[efriedma]

LGTM, but please test your patches more carefully in the future.

[chill]

In D40305#931984, @efriedma wrote:

LGTM, but please test your patches more carefully in the future.

Sorry about that. Many thanks for the review and comments.

llvm/trunk/lib/Target/ARM/Thumb1FrameLowering.cpp

bool Thumb1FrameLowering::emitPopSpecialFixUp(MachineBasicBlock &MBB,
   assert((PopReg || TemporaryReg) && "Cannot get LR");
 
   if (UseLDRSP) {
     assert(PopReg && "Do not know how to get LR");
     // Load the LR via LDR tmp, [SP, #off]
     BuildMI(MBB, MBBI, dl, TII.get(ARM::tLDRspi))
       .addReg(PopReg, RegState::Define)
       .addReg(ARM::SP)
-      .addImm(MBBI->getNumOperands() - 3)
+      .addImm(MBBI->getNumExplicitOperands() - 2)
       .add(predOps(ARMCC::AL));
     // Move from the temporary register to the LR.
     BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr))
       .addReg(ARM::LR, RegState::Define)
       .addReg(PopReg, RegState::Kill)
       .add(predOps(ARMCC::AL));
     // Advance past the pop instruction.
     MBBI++;

llvm/trunk/test/CodeGen/ARM/thumb1_return_sequence.ll

; CHECK-V5T:    push {[[SAVED:(r[4567](, )?)+]], lr}
   store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
   %0 = load <4 x i32>, <4 x i32>* %a, align 16
   ret <4 x i32> %0
 
 ; Epilogue
 ; --------
 ; Stack realignment means sp is restored from frame pointer
 ; CHECK-V4T:         mov sp
-; CHECK-V4T-NEXT:    ldr [[POP:r[4567]]], [sp, #{{.*}}]
+; CHECK-V4T-NEXT:    ldr [[POP:r[4567]]], [sp, #16]
 ; CHECK-V4T-NEXT:    mov lr, [[POP]]
 ; CHECK-V4T-NEXT:    pop {[[SAVED]]}
 ; CHECK-V4T-NEXT     add sp, sp, #4
 ; The ISA for v4 does not support pop pc, so make sure we do not emit
 ; one even when we do not need to update SP.
 ; CHECK-V4T-NOT:     pop {pc}
 ; CHECK-V4T:         bx lr
 ; CHECK-V5T:         pop {[[SAVED]], pc}
; CHECK-V5T:    push {[[SAVED:(r[4567](, )?)+]], lr}
   store <4 x i32> <i32 42, i32 42, i32 42, i32 42>, <4 x i32>* %b, align 16
   store <4 x i32> <i32 0, i32 1, i32 2, i32 3>, <4 x i32>* %a, align 16
   %0 = load <4 x i32>, <4 x i32>* %a, align 16
   call void @llvm.va_start(i8* null)
   ret <4 x i32> %0
 
 ; Epilogue
 ; --------
-; CHECK-V4T:         ldr [[POP:r[4567]]], [sp, #{{.*}}]
+; CHECK-V4T:         ldr [[POP:r[4567]]], [sp, #12]
 ; CHECK-V4T-NEXT:    mov lr, [[POP]]
 ; CHECK-V4T-NEXT:    pop {[[SAVED]]}
 ; CHECK-V4T-NEXT:    add sp, #16
 ; CHECK-V4T-NEXT:    bx  lr
 ; CHECK-V5T:         lsls r4
 ; CHECK-V5T-NEXT:    mov sp, r4
-; CHECK-V5T:         ldr [[POP:r[4567]]], [sp, #{{.*}}]
+; CHECK-V5T:         ldr [[POP:r[4567]]], [sp, #12]
 ; CHECK-V5T-NEXT:    mov lr, [[POP]]
 ; CHECK-V5T-NEXT:    pop {[[SAVED]]}
 ; CHECK-V5T-NEXT:    add sp, #16
 ; CHECK-V5T-NEXT:    bx  lr
 }
 
 ; CHECK-V4T-LABEL: simpleframe
 ; CHECK-V5T-LABEL: simpleframe

llvm/trunk/test/CodeGen/ARM/v8m-tail-call.ll

 ; RUN: llc %s -o - -mtriple=thumbv8m.base | FileCheck %s
 
 declare i32 @g(...)
 
 declare i32 @h0(i32, i32, i32, i32)
 define hidden i32 @f0() {
   %1 = tail call i32 bitcast (i32 (...)* @g to i32 ()*)()
   %2 = tail call i32 @h0(i32 %1, i32 1, i32 2, i32 3)
   ret i32 %2
 ; CHECK-LABEL: f0
-; CHECK:      ldr     [[POP:r[4567]]], [sp
+; CHECK:      ldr     [[POP:r[4567]]], [sp, #4]
 ; CHECK-NEXT: mov     lr, [[POP]]
 ; CHECK-NEXT: pop     {{.*}}[[POP]]
 ; CHECK-NEXT: add     sp, #4
 ; CHECK-NEXT: b       h0
 }
 
 declare i32 @h1(i32)
 define hidden i32 @f1() {
define hidden i32 @f2(i32, i32, i32, i32, i32) {
   br i1 %7, label %10, label %8
 
   %9 = tail call i32 @h2(i32 %6, i32 %1, i32 %2, i32 %3, i32 %4)
   br label %10
 
   %11 = phi i32 [ %9, %8 ], [ -1, %5 ]
   ret i32 %11
 ; CHECK-LABEL: f2
-; CHECK:      ldr     [[POP:r[4567]]], [sp
+; CHECK:      ldr     [[POP:r[4567]]], [sp, #12]
 ; CHECK-NEXT: mov     lr, [[POP]]
 ; CHECK-NEXT: pop     {{.*}}[[POP]]
 ; CHECK-NEXT: add     sp, #4
 ; CHECK-NEXT: b       h2
 }

llvm/trunk/test/CodeGen/Thumb/thumb-shrink-wrapping.ll

 define i1 @beq_to_bx(i32* %y, i32 %head) {
 ; CHECK-LABEL: beq_to_bx:
 ; DISABLE: push {r4, lr}
 ; CHECK: cmp r2, #0
 ; CHECK-NEXT: beq [[EXIT_LABEL:LBB[0-9_]+]]
 ; ENABLE: push {r4, lr}
 
 ; CHECK: tst r3, r4
-; ENABLE-NEXT: ldr [[POP:r[4567]]], [sp, #8]
+; ENABLE-NEXT: ldr [[POP:r[4567]]], [sp, #4]
 ; ENABLE-NEXT: mov lr, [[POP]]
 ; ENABLE-NEXT: pop {[[POP]]}
 ; ENABLE-NEXT: add sp, #4
 ; CHECK-NEXT: beq [[EXIT_LABEL]]
 
 ; CHECK: str r1, [r2]
 ; CHECK: str r3, [r2]
 ; CHECK-NEXT: movs r0, #0