[mir] Print/Parse both MOLoad and MOStore when they occur together.

[dsanders]

Summary

They're not always mutually exclusive. read-modify-write atomics are both
at the same time. One example of this is the SWP instructions on AArch64.
Another example is GlobalISel's G_ATOMICRMW_* generic instructions which
will be added in a later patch.

[dsanders]

Include the CHECK lines in the patch.

[dsanders]

ping

[aemerson]

LGTM.

[dsanders]

Thanks

lib/CodeGen/MIRParser/MIParser.cpp

if (Token.isNot(MIToken::Identifier) ||
       (Token.stringValue() != "load" && Token.stringValue() != "store"))
     return error("expected 'load' or 'store' memory operation");
   if (Token.stringValue() == "load")
     Flags |= MachineMemOperand::MOLoad;
   else
     Flags |= MachineMemOperand::MOStore;
   lex();
 
+  // Optional 'store' for operands that both load and store.
+  if (Token.is(MIToken::Identifier) && Token.stringValue() == "store") {
+    Flags |= MachineMemOperand::MOStore;
+    lex();
+  }
+
   // Optional synchronization scope.
   SyncScope::ID SSID;
   if (parseOptionalScope(MF.getFunction()->getContext(), SSID))
     return true;
 
   // Up to two atomic orderings (cmpxchg provides guarantees on failure).
   AtomicOrdering Order, FailureOrder;
   if (parseOptionalAtomicOrdering(Order))
     return true;
 
   if (parseOptionalAtomicOrdering(FailureOrder))
     return true;
 
   if (Token.isNot(MIToken::IntegerLiteral))
     return error("expected the size integer literal after memory operation");
   uint64_t Size;
   if (getUint64(Size))
     return true;
   lex();
 
   MachinePointerInfo Ptr = MachinePointerInfo();
   if (Token.is(MIToken::Identifier)) {
-    const char *Word = Flags & MachineMemOperand::MOLoad ? "from" : "into";
+    const char *Word =
+        ((Flags & MachineMemOperand::MOLoad) &&
+         (Flags & MachineMemOperand::MOStore))
+            ? "on"
+            : Flags & MachineMemOperand::MOLoad ? "from" : "into";
     if (Token.stringValue() != Word)
       return error(Twine("expected '") + Word + "'");
     lex();
 
     if (parseMachinePointerInfo(Ptr))
       return true;
   }
   unsigned BaseAlignment = Size;

lib/CodeGen/MIRPrinter.cpp

if (Op.getFlags() & MachineMemOperand::MOTargetFlag1)
     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag1)
        << "\" ";
   if (Op.getFlags() & MachineMemOperand::MOTargetFlag2)
     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag2)
        << "\" ";
   if (Op.getFlags() & MachineMemOperand::MOTargetFlag3)
     OS << '"' << getTargetMMOFlagName(TII, MachineMemOperand::MOTargetFlag3)
        << "\" ";
+
+  assert((Op.isLoad() || Op.isStore()) && "machine memory operand must be a load or store (or both)");
   if (Op.isLoad())
     OS << "load ";
-  else {
-    assert(Op.isStore() && "Non load machine operand must be a store");
+  if (Op.isStore())
     OS << "store ";
-  }
 
   printSyncScope(Context, Op.getSyncScopeID());
 
   if (Op.getOrdering() != AtomicOrdering::NotAtomic)
     OS << toIRString(Op.getOrdering()) << ' ';
   if (Op.getFailureOrdering() != AtomicOrdering::NotAtomic)
     OS << toIRString(Op.getFailureOrdering()) << ' ';
 
   OS << Op.getSize();
   if (const Value *Val = Op.getValue()) {
-    OS << (Op.isLoad() ? " from " : " into ");
+    OS << ((Op.isLoad() && Op.isStore()) ? " on "
+                                         : Op.isLoad() ? " from " : " into ");
     printIRValueReference(*Val);
   } else if (const PseudoSourceValue *PVal = Op.getPseudoValue()) {
-    OS << (Op.isLoad() ? " from " : " into ");
+    OS << ((Op.isLoad() && Op.isStore()) ? " on "
+                                         : Op.isLoad() ? " from " : " into ");
     assert(PVal && "Expected a pseudo source value");
     switch (PVal->kind()) {
     case PseudoSourceValue::Stack:
       OS << "stack";
       break;
     case PseudoSourceValue::GOT:
       OS << "got";
       break;

test/CodeGen/MIR/AArch64/swp.mir

+# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass none -o - %s | FileCheck %s
+
+--- |
+  define i32 @swp(i32* %addr) #0 {
+  entry:
+    %0 = atomicrmw xchg i32* %addr, i32 1 monotonic
+    ret i32 %0
+  }
+
+  attributes #0 = { "target-features"="+lse" }
+...
+---
+name:            swp
+alignment:       2
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gpr64common }
+  - { id: 1, class: gpr32 }
+  - { id: 2, class: gpr32 }
+liveins:
+  - { reg: '%x0', virtual-reg: '%0' }
+body:             |
+  bb.0.entry:
+    liveins: %x0
+
+    %0:gpr64common = COPY %x0
+    %1:gpr32 = MOVi32imm 1
+    %2:gpr32 = SWPW killed %1, %0 :: (volatile load store monotonic 4 on %ir.addr)
+    %w0 = COPY %2
+    RET_ReallyLR implicit %w0
+...