[RISCV] MC layer support for the jump/branch instructions of standard compress instruction set

[shiva0217]

Summary

1. Add CR CB CJ instruction format for C extension instructions

2. Add C extension jump/branch instructions

3. Identify/check SImm9Lsb0/SImm12Lsb0 operands by RISCVAsmParser

4. Add MC testcases for C extension jump/branch instructions

5. Support fixup branch/jump target immediate of compress instructions

6. Add Fixup MC testcases for C extension branch/jump instruction

[mgrang]

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

194

This return is unneeded as the default case is handled.

[apazos]

lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

39

compressed jump instruction

[shiva0217]

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

194

Remove redundant return.

lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

39

Fixup comments.

[asb]

lib/Target/RISCV/RISCVInstrInfoC.td

118

Given that Jump_imm, Call_Imm, Jump_Reg and Call_Reg only have a single instruction in that class, I think it makes sense to drop the intermediate classes and just define the instructions directly.

[shiva0217]

lib/Target/RISCV/RISCVInstrInfoC.td

118

Remove Jump_imm, Call_Imm, Jump_Reg and Call_Reg only have a single instruction in that class and define the instruction directly.

[shiva0217]

Add test cases to check the instruction operands should not be x0.

[shiva0217]

Change fixup_riscv_rvc_branch fixup field in getFixupKindInfo to avoid assert build trigger error

[asb]

Thanks Shiva. The simm9lsb0 and simm12lsb0 functions and match cases are added out of the usual order (ascending by bit-width), but I'll fix during commit.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

     return IsConstantImm && isUInt<12>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
 
+  bool isSImm9Lsb0() const { return isBareSimmNLsb0<9>(); }
+
+  bool isSImm12Lsb0() const { return isBareSimmNLsb0<12>(); }
+
   bool isSImm13Lsb0() const { return isBareSimmNLsb0<13>(); }
 
   bool isUImm20() const {

                                       (1 << 11) - 1);
   case Match_InvalidUImm12:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 12) - 1);
+  case Match_InvalidSImm9Lsb0:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, -(1 << 8), (1 << 8) - 2,
+        "immediate must be a multiple of 2 bytes in the range");
+  case Match_InvalidSImm12Lsb0:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, -(1 << 11), (1 << 11) - 2,
+        "immediate must be a multiple of 2 bytes in the range");
   case Match_InvalidSImm13Lsb0:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 12), (1 << 12) - 2,

lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp

       { "fixup_riscv_lo12_s",      0,     32,  0 },
       { "fixup_riscv_pcrel_hi20", 12,     20,  MCFixupKindInfo::FKF_IsPCRel },
       { "fixup_riscv_jal",        12,     20,  MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_riscv_branch",      0,     32,  MCFixupKindInfo::FKF_IsPCRel }
+      { "fixup_riscv_branch",      0,     32,  MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_riscv_rvc_jump",    2,     11,  MCFixupKindInfo::FKF_IsPCRel },
+      { "fixup_riscv_rvc_branch",  2,     11,  MCFixupKindInfo::FKF_IsPCRel }
     };
 
     if (Kind < FirstTargetFixupKind)

     Value = (Sbit << 31) | (Mid6 << 25) | (Lo4 << 8) | (Hi1 << 7);
     return Value;
   }
+  case RISCV::fixup_riscv_rvc_jump: {
+    // Need to produce offset[11|4|9:8|10|6|7|3:1|5] from the 11-bit Value.
+    unsigned Bit11  = (Value >> 11) & 0x1;
+    unsigned Bit4   = (Value >> 4) & 0x1;
+    unsigned Bit9_8 = (Value >> 8) & 0x3;
+    unsigned Bit10  = (Value >> 10) & 0x1;
+    unsigned Bit6   = (Value >> 6) & 0x1;
+    unsigned Bit7   = (Value >> 7) & 0x1;
+    unsigned Bit3_1 = (Value >> 1) & 0x7;
+    unsigned Bit5   = (Value >> 5) & 0x1;
+    Value = (Bit11 << 10) | (Bit4 << 9) | (Bit9_8 << 7) | (Bit10 << 6) |
+            (Bit6 << 5) | (Bit7 << 4) | (Bit3_1 << 1) | Bit5;
+    return Value;
+  }
+  case RISCV::fixup_riscv_rvc_branch: {
+    // Need to produce offset[8|4:3], [reg 3 bit], offset[7:6|2:1|5]
+    unsigned Bit8   = (Value >> 8) & 0x1;
+    unsigned Bit7_6 = (Value >> 6) & 0x3;
+    unsigned Bit5   = (Value >> 5) & 0x1;
+    unsigned Bit4_3 = (Value >> 3) & 0x3;
+    unsigned Bit2_1 = (Value >> 1) & 0x3;
+    Value = (Bit8 << 10) | (Bit4_3 << 8) | (Bit7_6 << 3) |
+            (Bit2_1 << 1) | Bit5;
+    return Value;
+  }
 
   }
 }
 
+static unsigned getSize(unsigned Kind) {
+  switch (Kind) {
+  default:
+    return 4;
+  case RISCV::fixup_riscv_rvc_jump:
+  case RISCV::fixup_riscv_rvc_branch:
+    return 2;
+  }
+  return 4;
+}
+
 void RISCVAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
                                  const MCValue &Target,
                                  MutableArrayRef<char> Data, uint64_t Value,

   Value <<= Info.TargetOffset;
 
   unsigned Offset = Fixup.getOffset();
+  unsigned FullSize = getSize(Fixup.getKind());
 
 #ifndef NDEBUG
   unsigned NumBytes = (Info.TargetSize + 7) / 8;

 
   // For each byte of the fragment that the fixup touches, mask in the
   // bits from the fixup value.
-  for (unsigned i = 0; i != 4; ++i) {
+  for (unsigned i = 0; i != FullSize; ++i) {
     Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
   }
 }

lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp

     return ELF::R_RISCV_JAL;
   case RISCV::fixup_riscv_branch:
     return ELF::R_RISCV_BRANCH;
+  case RISCV::fixup_riscv_rvc_jump:
+    return ELF::R_RISCV_RVC_JUMP;
+  case RISCV::fixup_riscv_rvc_branch:
+    return ELF::R_RISCV_RVC_BRANCH;
   }
 }
 

lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h

   // fixup_riscv_branch - 12-bit fixup for symbol references in the branch
   // instructions
   fixup_riscv_branch,
+  // fixup_riscv_rvc_jump - 11-bit fixup for symbol references in the
+  // compressed instruction
+  fixup_riscv_rvc_jump,
+  // fixup_riscv_rvc_branch - 8-bit fixup for symbol references in the
+  // compressed branch instruction
+  fixup_riscv_rvc_branch,
 
   // fixup_riscv_invalid - used as a sentinel and a marker, must be last fixup
   fixup_riscv_invalid,

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

       FixupKind = RISCV::fixup_riscv_jal;
     } else if (MIFrm == RISCVII::InstFormatB) {
       FixupKind = RISCV::fixup_riscv_branch;
+    } else if (MIFrm == RISCVII::InstFormatCJ) {
+      FixupKind = RISCV::fixup_riscv_rvc_jump;
+    } else if (MIFrm == RISCVII::InstFormatCB) {
+      FixupKind = RISCV::fixup_riscv_rvc_branch;
     }
   }
 

lib/Target/RISCV/RISCVInstrFormatsC.td

   let TSFlags{4-0} = format.Value;
 }
 
+class CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
+         string opcodestr, string argstr>
+    : RV16Inst<outs, ins, opcodestr, argstr, [], InstFormatCR> {
+  bits<5> rs1;
+  bits<5> rs2;
+
+  let Inst{15-12} = funct4;
+  let Inst{11-7} = rs1;
+  let Inst{6-2} = rs2;
+  let Inst{1-0} = opcode;
+}
+
 class CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
          string opcodestr, string argstr>
     : RV16Inst<outs, ins, opcodestr, argstr, [], InstFormatCI> {

   let Inst{4-2} = rs2;
   let Inst{1-0} = opcode;
 }
+
+class CB<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
+         string opcodestr, string argstr>
+    : RV16Inst<outs, ins, opcodestr, argstr, [], InstFormatCB> {
+  bits<9> imm;
+  bits<3> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{9-7} = rs1;
+  let Inst{1-0} = opcode;
+}
+
+class CJ<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
+         string opcodestr, string argstr>
+    : RV16Inst<outs, ins, opcodestr, argstr, [], InstFormatCJ> {
+  bits<12> offset;
+
+  let Inst{15-13} = funct3;
+  let Inst{12} = offset{11};
+  let Inst{11} = offset{4};
+  let Inst{10-9} = offset{9-8};
+  let Inst{8} = offset{10};
+  let Inst{7} = offset{6};
+  let Inst{6} = offset{7};
+  let Inst{5-3} = offset{3-1};
+  let Inst{2} = offset{5};
+  let Inst{1-0} = opcode;
+}

lib/Target/RISCV/RISCVInstrInfoC.td

 // Operand definitions.
 //===----------------------------------------------------------------------===//
 
+// A 9-bit signed immediate where the least significant bit is zero.
+def simm9_lsb0 : Operand<OtherVT> {
+  let ParserMatchClass = SImmAsmOperand<9, "Lsb0">;
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<9>";
+}
+
+// A 12-bit signed immediate where the least significant bit is zero.
+def simm12_lsb0 : Operand<OtherVT> {
+  let ParserMatchClass = SImmAsmOperand<12, "Lsb0">;
+  let EncoderMethod = "getImmOpValueAsr1";
+  let DecoderMethod = "decodeSImmOperandAndLsl1<12>";
+}
+
 // A 7-bit unsigned immediate where the least two bits are zero.
 def uimm7_lsb00 : Operand<XLenVT>,
                   ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {

       CS<funct3, 0b00, (outs), (ins cls:$rs2, cls:$rs1, opnd:$imm),
          OpcodeStr, "$rs2, ${imm}(${rs1})">;
 
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Jump_Imm : CJ<0b101, 0b01, (outs), (ins simm12_lsb0:$offset),
+                    "c.j", "$offset"> {
+  let isBranch = 1;
+  let isTerminator=1;
+  let isBarrier=1;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1 in
+class Call_Imm : CJ<0b001, 0b01, (outs), (ins simm12_lsb0:$offset),
+                    "c.jal", "$offset">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Jump_Reg<RegisterClass cls> :
+      CR<0b1000, 0b10, (outs), (ins cls:$rs1),
+         "c.jr", "$rs1"> {
+  let isBranch = 1;
+  let isBarrier = 1;
+  let isTerminator = 1;
+  let isIndirectBranch = 1;
+  let rs2 = 0;
+}
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+    isCall=1, Defs=[X1], rs2 = 0 in
+class Call_Reg<RegisterClass cls> :
+      CR<0b1001, 0b10, (outs), (ins cls:$rs1),
+         "c.jalr", "$rs1">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
+class Bcz<bits<3> funct3, string OpcodeStr, PatFrag CondOp,
+          RegisterClass cls> :
+      CB<funct3, 0b01, (outs), (ins cls:$rs1, simm9_lsb0:$imm),
+         OpcodeStr, "$rs1, $imm"> {
+  let isBranch = 1;
+  let isTerminator = 1;
+  let Inst{12} = imm{8};
+  let Inst{11-10} = imm{4-3};
+  let Inst{6-5} = imm{7-6};
+  let Inst{4-3} = imm{2-1};
+  let Inst{2} = imm{5};
+}
+
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//

   let Inst{12-10} = imm{5-3};
   let Inst{6-5} = imm{7-6};
 }
+
+def CJ : Jump_Imm, Requires<[HasStdExtC]>;
+
+def CJAL : Call_Imm, Requires<[HasStdExtC]>;
+
+def CJR : Jump_Reg<GPR>, Requires<[HasStdExtC]>;
+
+def CJALR : Call_Reg<GPR>, Requires<[HasStdExtC]>;
+
+def CBEQZ   : Bcz<0b110, "c.beqz",  seteq, GPRC>, Requires<[HasStdExtC]>;
+def CBNEZ   : Bcz<0b111, "c.bnez",  setne, GPRC>, Requires<[HasStdExtC]>;

test/MC/RISCV/fixups-compressed.s

+# RUN: llvm-mc %s -mattr=+c -show-encoding \
+# RUN:     | FileCheck -check-prefix=CHECK-FIXUP %s
+# RUN: llvm-mc -filetype=obj -mattr=+c < %s \
+# RUN:     | llvm-objdump -d - | FileCheck -check-prefix=CHECK-INSTR %s
+
+.LBB0_2:
+# CHECK-FIXUP: encoding: [0bAAAAAA01,0b101AAAAA]
+# CHECK-FIXUP:   fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_jump
+# CHECK-INSTR: c.j     0
+c.j     .LBB0_2
+# CHECK-FIXUP: encoding: [0bAAAAAA01,0b110AAAAA]
+# CHECK-FIXUP:   fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch
+# CHECK-INSTR: c.beqz  a3, -4
+c.beqz  a3, .LBB0_2
+# CHECK-FIXUP: encoding: [0bAAAAAA01,0b111AAAAA]
+# CHECK-FIXUP:   fixup A - offset: 0, value: .LBB0_2, kind: fixup_riscv_rvc_branch
+# CHECK-INSTR: c.bnez  a5, -8
+c.bnez  a5, .LBB0_2

test/MC/RISCV/relocations.s

-# RUN: llvm-mc -triple riscv32 < %s -show-encoding \
+# RUN: llvm-mc -triple riscv32 -mattr=+c < %s -show-encoding \
 # RUN:     | FileCheck -check-prefix=INSTR -check-prefix=FIXUP %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
 # RUN:     | llvm-readobj -r | FileCheck -check-prefix=RELOC %s
 
 # Check prefixes:

 # RELOC: R_RISCV_BRANCH
 # INSTR: bgeu a0, a1, foo
 # FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_branch
+
+c.jal foo
+# RELOC: R_RISCV_RVC_JUMP
+# INSTR: c.jal foo
+# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_jump
+
+c.bnez a0, foo
+# RELOC: R_RISCV_RVC_BRANCH
+# INSTR: c.bnez a0, foo
+# FIXUP: fixup A - offset: 0, value: foo, kind: fixup_riscv_rvc_branch

test/MC/RISCV/rv32c-invalid.s

 # RUN: not llvm-mc -triple=riscv32 -mattr=+c < %s 2>&1 | FileCheck %s
 
+.LBB:
 ## GPRC
 c.lw  ra, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
 c.sw  sp, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+c.beqz  t0, .LBB # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
+c.bnez  s8, .LBB # CHECK: :[[@LINE]]:9: error: invalid operand for instruction
 
 # Out of range immediates
 

 ## uimm7_lsb00
 c.lw  s0, -4(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
 c.sw  s0, 130(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
+
+## simm9_lsb0
+c.bnez  s1, -1028 # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-256, 254]
+c.beqz  a0, 280 # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 2 bytes in the range [-256, 254]
+
+## simm12_lsb0
+c.j 4096 # CHECK: :[[@LINE]]:5: error: immediate must be a multiple of 2 bytes in the range [-2048, 2046]
+c.jal -3000 # CHECK: :[[@LINE]]:7: error: immediate must be a multiple of 2 bytes in the range [-2048, 2046]

test/MC/RISCV/rv32c-valid.s

 # CHECK-INST: c.sw    a5, 8(a3)
 # CHECK: encoding: [0x9c,0xc6]
 c.sw    a5, 8(a3)
+
+# CHECK-INST: c.j     -16
+# CHECK: encoding: [0xe5,0xbf]
+c.j     -16
+# CHECK-INST: c.jr    a7
+# CHECK: encoding: [0x82,0x88]
+c.jr    a7
+# CHECK-INST: c.jalr  a1
+# CHECK: encoding: [0x82,0x95]
+c.jalr  a1
+# CHECK-INST: c.beqz  a3, -8
+# CHECK: encoding: [0xf5,0xde]
+c.beqz  a3, -8
+# CHECK-INST: c.bnez  a5, -12
+# CHECK: encoding: [0xed,0xff]
+c.bnez  a5, -12