[RISCV] MC layer support for the load/store instructions of standard compress instruction set

[shiva0217]

Summary

1. Define SubtargetFeature and Predicate for C extension

2. Add IsRV64 Predicate for RV64 only C extension instructions

3. Support decode 16-bit instructions

4. Support encode 16-bit instructions

5. Add GPRC, SP,GPRNonX0 register class for C extension load/store instructions

6. Add compress InstFormat enum format

7. TSFlags in RISCVInstrFormats.td/RISCVInstrFormatsC.td have increase 1 bit

8. Add CI CSS CL CS instruction format for C extension load/store instructions

9. Add C extension load/store instructions

10. Support decode GPRC,GPRNonX0 register class

11. Identify/check UImm8Lsb00/UImm7Lsb00/UImm8Lsb000/UImm9Lsb000 operands by RISCVAsmParser

12. Add imply SP operand while decoding CLWSP/CLWLP/CLDSP/CSDSP

13. Add rv32c-valid.s, rv32c-invalid.s, rv64c-valid.s, rv64c-invalid.s MC testcases

[simoncook]

lib/Target/RISCV/RISCV.td

29

Should this be "'C' (Compressed Instructions)", and presumably aligned similarly with FeatureStdExtA?

test/MC/RISCV/compressed-invalid.s

1

This test is missing the triple to run the assembler for. I would expect a "-triple=riscv32" or "-triple=riscv64" here.

test/MC/RISCV/compressed-valid.s

1

This test is missing the triple to run the assembler for. I would expect a "-triple=riscv32" or "-triple=riscv64" here.

[asb]

Thanks Shiva. A whole bunch of inline comments are below. Thanks to Simon for spotting the missing -triple in the tests, I was struggling to see why I couldn't get the tests to pass.

compressed-valid.s and compressed-invalid.s should be named rv32c-valid.s and rv32c-invalid.s to match the naming conventions of the existing tests. You can also add check lines for a -riscv64 triple. RV64C specific instructions can go in rv64c-valid.s

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

212

These methods are sorted by bit-width of the operand, so should be in the order isUImm5, isUImm6Lsb00, isUImm8Lsb00.

424

Should ideally be ordered like the methods.

[InvalidFenceArg doesn't match the method order here, I should fix that next time that piece of code gets touched].

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

87

Shouldn't you be checking RegNo > 8?

172

The previous code was using support::endian::read32le(Bytes.data()). Can't you use support::endian::read16le(Bytes.data())) for C instructions and avoid adding the extra helper functions?

lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

32

I've tried to keep the instruction formats matching those in the ISA manual. I'd be inclined to use more bits of TSFlags and have the instruction format names match those in Table 12.1 in the ISA manual.

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

86

TmpInst seems unnecessary.

94

Replace the assert a couple of lines above with an llvm_unreachable here?

lib/Target/RISCV/RISCVInstrFormats.td

41

Same comment as before regarding InstFormats

lib/Target/RISCV/RISCVInstrFormatsC.td

15

Indentation

31

I'd prefer using opcodestr+argstr like the formats in RISCVInstrFormats.td. I found this reduced the amount of string manipulation needed overall.

lib/Target/RISCV/RISCVInstrInfo.cpp

55

These RISCVInstrInfo.cpp changes should go in a later codegen patch, as they're not necessary for MC layer support

lib/Target/RISCV/RISCVInstrInfoC.td

60

I'd prefer to use headers similarly to RISCVInstrInfo.td. i.e. for "Instruction class templates" and "Instructions" - we can always change later if we want, keeping things consistent across all the .td files.

67

Maybe I'm missing something, but can't the CL class take care of placing these immediate bits where appropriate (same for the instructions below)

[shiva0217]

Thanks, Simon, I adding the missing -triple argument in testcases and fix the typo.
Thanks, Alex, I rename the tesecase to rv32/64c-valid/invalid.s and reorganize the code as you suggest.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

212

Sorting the method as @asb suggest.

424

Sorting the method as @asb suggest.
If the order still not as you expect, please feel free to reorder the method in next patch.

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

87

Yes, should check >8.
Thanks.

172

Using support::endian::read32le(Bytes.data()) and support::endian::read16le(Bytes.data())) to avoid adding extra helper functions.

lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

32

Adding all compress instruction InstFormat and increase TSFlags 1 bit.

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

86

remove redundant TmpInst.

94

Adding llvm_unreachable in default which is the case that instruction length, not 2 or 4.

lib/Target/RISCV/RISCV.td

29

Yes, Thanks, fix the typo here.

lib/Target/RISCV/RISCVInstrFormats.td

41

Add all compress instruction InstFormats

lib/Target/RISCV/RISCVInstrFormatsC.td

15

Fix the Indentation

31

Using opcodestr+argstr like the formats in RISCVInstrFormats.td.

lib/Target/RISCV/RISCVInstrInfo.cpp

55

Remove the code which will add later in C codegen support patch.

lib/Target/RISCV/RISCVInstrInfoC.td

60

Remove other header names.
Using the same naming "Instructions" as in RISCVInstrInfo.td

67

The reason we put immediate encode in CLW is that CLD use the same encoding format(CL) except the immediate encoding is different.
To reuse the format class, we extract the immediate encoding in each instruction.

test/MC/RISCV/compressed-invalid.s

1

Adding missing -triple in testcases.

test/MC/RISCV/compressed-valid.s

1

Adding missing -triple in testcases.

[simoncook]

Thanks, I found one nitpick with a couple of the tests, but the rest looks good to me.

test/MC/RISCV/rv32c-valid.s

1 ↗

(On Diff #122980)

Should this be < %s instead to be consistent with the other calls to llvm-mc below?

test/MC/RISCV/rv64c-valid.s

1 ↗

(On Diff #122980)

Likewise with rv32c-valid.s

[shiva0217]

test/MC/RISCV/rv32c-valid.s

1 ↗

(On Diff #122980)

Make the call llvm-mc command in test case consistent as Simon suggest.

test/MC/RISCV/rv64c-valid.s

1 ↗

(On Diff #122980)

Make the call llvm-mc command in test case consistent as Simon suggest.

[mgrang]

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

96

Period after comment.

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

87

Period after comment.

98

Can you order the cases in the ascending order of Size?

[apazos]

Shiva, next time you update this patch (and the other patches), can you please generate the patch with more context?
git diff HEAD~1 HEAD -U9999999999
See https://llvm.org/docs/Phabricator.html#requesting-a-review-via-the-web-interface

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

87

no need to add { }

149

if bit 0 and 1 are 1.

[shiva0217]

Hi @mgrang, @apazos

Thanks for the comments.
I update the patch using "-U 9999999999" and also using clang-format to check indentation.

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

87

remove unnecessary {}.

96

Add period after comment.

149

Fixup comments.

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

87

Add period after comment.

98

Order the case by ascending order as @mgrang suggest.

[asb]

Hi Shiva, now I've got this building on top of head I see I was incorrect to suggest removing the RISCVInstrInfo.cpp changes, as you get assertions in some of the tests if you don't. I haven't done much work with cases like this where you have multiple register classes with overlapping contents but I _think_ the most correct fix to storeRegToStackSlot and loadRegtoStackSlot is to use if (RISCV::GPRRegClass.hasSubClassEq(RC)) rather than if (RC == &RISCV::GPRRegClasss). The original code probably should have been written using this in the first place.

[asb]

Hi Shiva, I think we're almost there. Primarily naming and style nits below. The most important issue to resolve is the implied SP operand I think.

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

97

Is there a reason we can't use let Uses = [X2] and/or let Defs = [X2] for instructions that implicitly read/write the stack pointer register?

lib/Target/RISCV/RISCVInstrFormatsC.td

38

I started off by using very short class names in RISCVInforFormats.td, but found it's ultimately easy to confuse a class name with an instruction. RVInstCI or RVInst16CI and so on would probably be preferable.

lib/Target/RISCV/RISCVInstrInfoC.td

17

"where the least significant two bits are zero." (same fix for other operand types defined below).

54

StackLoad_ri or `CStackLoad would match the naming convention used in RISCVInstrInfo.td and others. Same for the other classes. See also my query regarding the sp operand and whether we can use Defs and Uses instead.

67

I see. In that case, it would make sense to add a comment to the CL and CS classes that explains subclasses must set the immediate bits. An alternative could be to define different classes for these variants as is done with RVInstIShift and RVInstIShiftW.

81

It would match the other RISCVInstrInfo*.td files use let Predicates = [HasStdExtC] in a way similar to a C++ namespace.

81

Just one space is needed after the instruction name and before :

87

I try to keep the MC layer instruction definitions as close to the ISA manual as possible, ordering based on the the quickref table on page 104 of the spec. It might be nice to order based on the tables in section 12.7 "RVC Instruction Set Listings" (page 82 and 83). There's probably less benefit in doing so than for the RV32IMAFD extensions though, so it's up to you. Generally, it's nice to be able to see at a glance that every instruction in that listing is represented.

test/MC/RISCV/rv32c-invalid.s

10 ↗

(On Diff #123533)

It would be good to check values that are just outside the valid range.

test/MC/RISCV/rv32c-valid.s

3 ↗

(On Diff #123533)

There's no need to explicitly state +64bit in this or the other tests.

13 ↗

(On Diff #123533)

It would be good to check the maximum and minimum immediate values (same with other *-valid.s tests).

[shiva0217]

Hi Alex, if (RISCV::GPRRegClass.hasSubClassEq(RC)) in storeRegToStackSlot and loadRegtoStackSlot looks like a good a solution to me. About imply SP I have explained in the inline comments, let me know if you have other thought about it. Thanks for your comments, I really appreciate that.

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

97

The reason is that InstPrinter has to print SP operand "c.lwsp ra, 12(sp)".
We could print sp as string and remove it in input operand list rather than add imply SP,
but the parser will parse sp as input operand and we'll need to add other logic to deal with it.
If we add imply SP operand while disassembling, then printer and parser could work fine without extra code.

lib/Target/RISCV/RISCVInstrFormatsC.td

38

Rename the instruction formats for compress instructions with "RVInst16" prefix.

lib/Target/RISCV/RISCVInstrInfoC.td

17

Fixup comments.

54

Rename the class to CStackLoad to match the naming rule in RISCVInstrInfo.td.

67

Adding comments to CL and CS classes that subclasses must set the immediate bits.

81

Using let Predicates = [HasStdExtC] instead of using require.

87

OK, I'll list the instructions base on the table in section 12.7 "RVC Instruction Set Listings" (page 82 and 83). Let me know if I still misorder something.

test/MC/RISCV/rv32c-invalid.s

10 ↗

(On Diff #123533)

Testing the invalid value just outside the valid range.

test/MC/RISCV/rv32c-valid.s

3 ↗

(On Diff #123533)

Remove redundant +64bit argument in the testcase.

13 ↗

(On Diff #123533)

check the maximum and minimum immediate values in -valids tests.

[asb]

Many many thanks for the patch update Shiva, this is looking pretty good. I have a concern in the comment about the immediate encoding for C.LWSP.

Shouldn't rv32c-invalid.s also check for cases like c.lwsp with rd as x0?

Thanks for clarifying the reasoning behind implySP - I can see now why you implemented things that way. Let me think a little more about it.

lib/Target/RISCV/RISCVInstrFormatsC.td

53

Perhaps phrase as something like "The immediate value encoding differs for each instruction, so each subclass is responsible for setting the appropriate bits in the Inst field." In fact, it would be even better to document the bits that must be set, e.g. Inst{12-10}.

lib/Target/RISCV/RISCVInstrInfoC.td

114

What about Inst{12}? I think we need more tests in rv32c-valid.s that verify the immediate encoding is correct.

[shiva0217]

Hi Alex, yes, the test case for operand should not x0 is missing. New revision updates the test case and adds GPRNonX0 register class for it.

lib/Target/RISCV/RISCVInstrFormatsC.td

53

Update the comment and specify the bits need to be set for each instruction.

lib/Target/RISCV/RISCVInstrInfoC.td

114

The Inst{12} is set by RVInst16CI due to the bit encoding is the same for each instruction in CI format.

[asb]

Thanks Shiva. I think we may revisit the "implied" SP operands later, but I'll go ahead and commit as-is.

lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

bool isSImm12() const {
     if (!IsConstantImm)
       IsValid = RISCVAsmParser::classifySymbolRef(getImm(), VK, Imm);
     else
       IsValid = isInt<12>(Imm);
     return IsValid &&
            (VK == RISCVMCExpr::VK_RISCV_None || VK == RISCVMCExpr::VK_RISCV_LO);
   }
 
+  bool isUImm8Lsb00() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK;
+    bool IsConstantImm = evaluateConstantImm(Imm, VK);
+    return IsConstantImm && isShiftedUInt<6, 2>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
+  bool isUImm7Lsb00() const {
+    int64_t Imm;
+    RISCVMCExpr::VariantKind VK;
+    bool IsConstantImm = evaluateConstantImm(Imm, VK);
+    return IsConstantImm && isShiftedUInt<5, 2>(Imm) &&
+           VK == RISCVMCExpr::VK_RISCV_None;
+  }
+
   bool isUImm12() const {
     int64_t Imm;
     RISCVMCExpr::VariantKind VK;
     if (!isImm())
       return false;
     bool IsConstantImm = evaluateConstantImm(Imm, VK);
     return IsConstantImm && isUInt<12>(Imm) && VK == RISCVMCExpr::VK_RISCV_None;
   }
return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 12), (1 << 12) - 2,
         "immediate must be a multiple of 2 bytes in the range");
   case Match_InvalidUImm20:
     return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 20) - 1);
   case Match_InvalidSImm21Lsb0:
     return generateImmOutOfRangeError(
         Operands, ErrorInfo, -(1 << 20), (1 << 20) - 2,
         "immediate must be a multiple of 2 bytes in the range");
+  case Match_InvalidUImm7Lsb00:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, 0, (1 << 7) - 4,
+        "immediate must be a multiple of 4 bytes in the range");
+  case Match_InvalidUImm8Lsb00:
+    return generateImmOutOfRangeError(
+        Operands, ErrorInfo, 0, (1 << 8) - 4,
+        "immediate must be a multiple of 4 bytes in the range");
   case Match_InvalidFenceArg: {
     SMLoc ErrorLoc = ((RISCVOperand &)*Operands[ErrorInfo]).getStartLoc();
     return Error(
         ErrorLoc,
         "operand must be formed of letters selected in-order from 'iorw'");
   }
   }
 

lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp

static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint64_t RegNo,
    // We must define our own mapping from RegNo to register identifier.
    // Accessing index RegNo in the register class will work in the case that
    // registers were added in ascending order, but not in general.
    unsigned Reg = GPRDecoderTable[RegNo];
    Inst.addOperand(MCOperand::createReg(Reg));
    return MCDisassembler::Success;
 }
 
+static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+                                            uint64_t Address,
+                                            const void *Decoder) {
+   if (RegNo > sizeof(GPRDecoderTable)) {
+     return MCDisassembler::Fail;
+   }
+   unsigned Reg = GPRDecoderTable[RegNo + 8];
+   Inst.addOperand(MCOperand::createReg(Reg));
+   return MCDisassembler::Success;
+}
+
+// Add Imply SP operand for SP imply instructions(The instruction SP not encode
+// in bit field)
+static void addImplySP(MCInst &Inst, int64_t Address, const void *Decoder) {
+  if (Inst.getOpcode() == RISCV::CLWSP ||
+      Inst.getOpcode() == RISCV::CSWSP) {
+    DecodeGPRRegisterClass(Inst, 2, Address, Decoder);
+  }
+}
+
 template <unsigned N>
 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address, const void *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
+  addImplySP(Inst, Address, Decoder);
   Inst.addOperand(MCOperand::createImm(Imm));
   return MCDisassembler::Success;
 }
 
 template <unsigned N>
 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
                                       int64_t Address, const void *Decoder) {
   assert(isUInt<N>(Imm) && "Invalid immediate");
static DecodeStatus decodeSImmOperandAndLsl1(MCInst &Inst, uint64_t Imm,
   // the fact that the N bit immediate is stored in N-1 bits (the LSB is
   // always zero)
   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm << 1)));
   return MCDisassembler::Success;
 }
 
 #include "RISCVGenDisassemblerTables.inc"
 
+/// Read two bytes from the ArrayRef and return 16 bit halfword
+static DecodeStatus readInstruction16(ArrayRef<uint8_t> Bytes, uint64_t Address,
+                                      uint64_t &Size, uint32_t &Insn) {
+  // We want to read exactly 2 Bytes of data.
+  if (Bytes.size() < 2) {
+    Size = 0;
+    return MCDisassembler::Fail;
+  }
+
+  Insn = (Bytes[1] << 8) | Bytes[0];
+
+  return MCDisassembler::Success;
+}
+
+/// Read four bytes from the ArrayRef and return 32 bit word
+static DecodeStatus readInstruction32(ArrayRef<uint8_t> Bytes, uint64_t Address,
+                                      uint64_t &Size, uint32_t &Insn) {
+  // We want to read exactly 4 Bytes of data.
+  if (Bytes.size() < 4) {
+    Size = 0;
+    return MCDisassembler::Fail;
+  }
+
+  Insn = (Bytes[0] << 0) | (Bytes[1] << 8) | (Bytes[2] << 16) |
+         (Bytes[3] << 24);
+
+  return MCDisassembler::Success;
+}
+
 DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
                                                ArrayRef<uint8_t> Bytes,
                                                uint64_t Address,
                                                raw_ostream &OS,
                                                raw_ostream &CS) const {
-  // TODO: although assuming 4-byte instructions is sufficient for RV32 and
-  // RV64, this will need modification when supporting the compressed
-  // instruction set extension (RVC) which uses 16-bit instructions. Other
-  // instruction set extensions have the option of defining instructions up to
+  // TODO: This will need modification when supporting the instruction
+  // set extensions have the option of defining instructions up to
   // 176 bits wide.
+  uint32_t Insn;
+  DecodeStatus Result;
+
+  // It's a 32 bit instruction if bit 0 and 1 is 1.
+  if ((Bytes[0] & 0x3) == 0x3) {
+    Result = readInstruction32(Bytes, Address, Size, Insn);
+    if (Result == MCDisassembler::Fail)
+      return MCDisassembler::Fail;
+
+    DEBUG(dbgs() << "Trying RISCV32 table :\n");
+    Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
     Size = 4;
-  if (Bytes.size() < 4) {
-    Size = 0;
+  } else {
+    Result = readInstruction16(Bytes, Address, Size, Insn);
+    if (Result == MCDisassembler::Fail)
       return MCDisassembler::Fail;
+
+    DEBUG(dbgs() << "Trying RISCV_C table (16-bit Instruction):\n");
+    // Calling the auto-generated decoder function.
+    Result =
+      decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
+    Size = 2;
   }
 
-  // Get the four bytes of the instruction.
-  uint32_t Inst = support::endian::read32le(Bytes.data());
+  if (Result != MCDisassembler::Fail) {
+    return Result;
+  }
 
-  return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
+  return MCDisassembler::Fail;
 }

lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h

 enum {
   InstFormatPseudo = 0,
   InstFormatR = 1,
   InstFormatI = 2,
   InstFormatS = 3,
   InstFormatB = 4,
   InstFormatU = 5,
   InstFormatJ = 6,
-  InstFormatOther = 7,
+  InstFormatC = 7,
+  InstFormatCB = 8,
+  InstFormatCJ = 9,
+  InstFormatOther = 10,
  
   InstFormatMask = 15
 };
 
 enum {
   MO_None,
   MO_LO,
   MO_HI,
   MO_PCREL_HI,

lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp

MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
                                               const MCRegisterInfo &MRI,
                                               MCContext &Ctx) {
   return new RISCVMCCodeEmitter(Ctx, MCII);
 }
 
 void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
                                            SmallVectorImpl<MCFixup> &Fixups,
                                            const MCSubtargetInfo &STI) const {
-  // For now, we only support RISC-V instructions with 32-bit length
+  MCInst TmpInst = MI;
+  const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
+  // Get byte count of instruction
+  unsigned Size = Desc.getSize();
+  assert(Size && "Desc.getSize() returns 0");
+
+  switch (Size) {
+  default:
+    break;
+  case 4: {
     uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
     support::endian::Writer<support::little>(OS).write(Bits);
+    break;
+  }
+  case 2: {
+    uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
+    support::endian::Writer<support::little>(OS).write<uint16_t>(Bits);
+    break;
+  }
+  }
+
   ++MCNumEmitted; // Keep track of the # of mi's emitted.
 }
 
 unsigned
 RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
                                       SmallVectorImpl<MCFixup> &Fixups,
                                       const MCSubtargetInfo &STI) const {
 

lib/Target/RISCV/RISCV.td

def HasStdExtM : Predicate<"Subtarget->hasStdExtM()">,
                            AssemblerPredicate<"FeatureStdExtM">;
 
 def FeatureStdExtA
     : SubtargetFeature<"a", "HasStdExtA", "true",
                        "'A' (Atomic Instructions)">;
 def HasStdExtA : Predicate<"Subtarget->hasStdExtA()">,
                            AssemblerPredicate<"FeatureStdExtA">;
 
+def FeatureStdExtC : SubtargetFeature<"c", "HasStdExtC", "true",
+                           "'A' (Atomic Instructions)">;
+def HasStdExtC     :  Predicate<"Subtarget->hasStdExtC()">,
+                           AssemblerPredicate<"FeatureStdExtC">;
+
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 
 def RV64           : HwMode<"+64bit">;
 def RV32           : HwMode<"-64bit">;
 
 //===----------------------------------------------------------------------===//
 // Registers, calling conventions, instruction descriptions.

lib/Target/RISCV/RISCVInstrFormats.td

 }
 def InstFormatPseudo : InstFormat<0>;
 def InstFormatR      : InstFormat<1>;
 def InstFormatI      : InstFormat<2>;
 def InstFormatS      : InstFormat<3>;
 def InstFormatB      : InstFormat<4>;
 def InstFormatU      : InstFormat<5>;
 def InstFormatJ      : InstFormat<6>;
-def InstFormatOther  : InstFormat<7>;
+def InstFormatC      : InstFormat<7>;
+def InstFormatCB     : InstFormat<8>;
+def InstFormatCJ     : InstFormat<9>;
+def InstFormatOther  : InstFormat<10>;
 
 // The following opcode names and match those given in Table 19.1 in the
 // RISC-V User-level ISA specification ("RISC-V base opcode map").
 class RISCVOpcode<bits<7> val> {
   bits<7> Value = val;
 }
 def OPC_LOAD      : RISCVOpcode<0b0000011>;
 def OPC_LOAD_FP   : RISCVOpcode<0b0000111>;

lib/Target/RISCV/RISCVInstrFormatsC.td

+//===-- RISCVInstrFormatsC.td - RISCV C Instruction Formats --*- tablegen -*-=//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+//  This file describes the RISC-V C extension instruction formats.
+//
+//===----------------------------------------------------------------------===//
+
+class RV16Inst<dag outs, dag ins, string asmstr, list<dag> pattern,
+                  InstFormat format>
+    : Instruction {
+  field bits<16> Inst;
+  // SoftFail is a field the disassembler can use to provide a way for
+  // instructions to not match without killing the whole decode process. It is
+  // mainly used for ARM, but Tablegen expects this field to exist or it fails
+  // to build the decode table.
+  field bits<16> SoftFail = 0;
+  let Size = 2;
+
+  bits<2> Opcode = 0;
+
+  let Namespace = "RISCV";
+
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString = asmstr;
+  let Pattern = pattern;
+
+  let TSFlags{3-0} = format.Value;
+}
+
+class CI<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
+         string asmstr>
+    : RV16Inst<outs, ins, asmstr, [], InstFormatC> {
+  bits<10> imm;
+  bits<5> rd;
+  bits<5> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{12} = imm{5};
+  let Inst{11-7} = rd;
+  let Inst{1-0} = opcode;
+}
+
+class CSS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
+          string asmstr>
+    : RV16Inst<outs, ins, asmstr, [], InstFormatC> {
+  bits<10> imm;
+  bits<5> rs2;
+  bits<5> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{6-2} = rs2;
+  let Inst{1-0} = opcode;
+}
+
+class CL<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
+         string asmstr>
+    : RV16Inst<outs, ins, asmstr, [], InstFormatC> {
+  bits<3> rd;
+  bits<3> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{9-7} = rs1;
+  let Inst{4-2} = rd;
+  let Inst{1-0} = opcode;
+}
+
+class CS<bits<3> funct3, bits<2> opcode, dag outs, dag ins,
+         string asmstr>
+    : RV16Inst<outs, ins, asmstr, [], InstFormatC> {
+  bits<3> rs2;
+  bits<3> rs1;
+
+  let Inst{15-13} = funct3;
+  let Inst{9-7} = rs1;
+  let Inst{4-2} = rs2;
+  let Inst{1-0} = opcode;
+}

lib/Target/RISCV/RISCVInstrInfo.cpp

void RISCVInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                          MachineBasicBlock::iterator I,
                                          unsigned SrcReg, bool IsKill, int FI,
                                          const TargetRegisterClass *RC,
                                          const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RC == &RISCV::GPRRegClass)
+  if (RC == &RISCV::GPRRegClass || RC == &RISCV::GPRCRegClass)
     BuildMI(MBB, I, DL, get(RISCV::SW))
         .addReg(SrcReg, getKillRegState(IsKill))
         .addFrameIndex(FI)
         .addImm(0);
   else
     llvm_unreachable("Can't store this register to stack slot");
 }
 
 void RISCVInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
                                           MachineBasicBlock::iterator I,
                                           unsigned DstReg, int FI,
                                           const TargetRegisterClass *RC,
                                           const TargetRegisterInfo *TRI) const {
   DebugLoc DL;
   if (I != MBB.end())
     DL = I->getDebugLoc();
 
-  if (RC == &RISCV::GPRRegClass)
+  if (RC == &RISCV::GPRRegClass || RC == &RISCV::GPRCRegClass)
     BuildMI(MBB, I, DL, get(RISCV::LW), DstReg).addFrameIndex(FI).addImm(0);
   else
     llvm_unreachable("Can't load this register from stack slot");
 }

lib/Target/RISCV/RISCVInstrInfo.td

 } // Defs = [X2], Uses = [X2]
 
 //===----------------------------------------------------------------------===//
 // Standard extensions
 //===----------------------------------------------------------------------===//
 
 include "RISCVInstrInfoM.td"
 include "RISCVInstrInfoA.td"
+include "RISCVInstrInfoC.td"

lib/Target/RISCV/RISCVInstrInfoC.td

+//===- RISCVInstrInfoC.td - Compressed RISCV instructions -*- tblgen-*-----===//
+//
+//                     The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+
+include "RISCVInstrFormatsC.td"
+
+//===----------------------------------------------------------------------===//
+// Operand definitions.
+//===----------------------------------------------------------------------===//
+
+// A 8-bit unsigned immediate where the least two bits are zero.
+def uimm8_lsb00 : Operand<XLenVT>,
+                  ImmLeaf<XLenVT, [{return isShiftedUInt<6, 2>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<8, "Lsb00">;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<8>";
+}
+
+// A 7-bit unsigned immediate where the least two bits are zero.
+def uimm7_lsb00 : Operand<XLenVT>,
+                  ImmLeaf<XLenVT, [{return isShiftedUInt<5, 2>(Imm);}]> {
+  let ParserMatchClass = UImmAsmOperand<7, "Lsb00">;
+  let EncoderMethod = "getImmOpValue";
+  let DecoderMethod = "decodeUImmOperand<7>";
+}
+
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class Stack_Load<bits<3> funct3, string OpcodeStr,
+                 RegisterClass cls> :
+      CI<funct3, 0b10, (outs cls:$rd), (ins SP:$rs1, uimm8_lsb00:$imm),
+         OpcodeStr#"\t$rd, ${imm}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class Stack_Store<bits<3> funct3, string OpcodeStr,
+                  RegisterClass cls> :
+      CSS<funct3, 0b10, (outs), (ins cls:$rs2, SP:$rs1, uimm8_lsb00:$imm),
+          OpcodeStr#"\t$rs2, ${imm}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
+class Reg_Load<bits<3> funct3, string OpcodeStr, SDPatternOperator Op,
+               RegisterClass cls> :
+      CL<funct3, 0b00, (outs cls:$rd), (ins cls:$rs1, uimm7_lsb00:$imm),
+         OpcodeStr#"\t$rd, ${imm}(${rs1})">;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
+class Reg_Store<bits<3> funct3, string OpcodeStr, SDPatternOperator Op,
+                RegisterClass cls> :
+      CS<funct3, 0b00, (outs), (ins cls:$rs2, cls:$rs1, uimm7_lsb00:$imm),
+         OpcodeStr#"\t$rs2, ${imm}(${rs1})">;
+
+//===----------------------------------------------------------------------===//
+// Stack-Pointer-Based Loads and Stores
+//===----------------------------------------------------------------------===//
+
+def CLWSP  : Stack_Load<0b010, "c.lwsp", GPR>,
+             Requires<[HasStdExtC]> {
+  let Inst{6-4} = imm{4-2};
+  let Inst{3-2} = imm{7-6};
+}
+
+def CSWSP  : Stack_Store<0b110, "c.swsp", GPR>,
+             Requires<[HasStdExtC]> {
+  let Inst{12-9} = imm{5-2};
+  let Inst{8-7}  = imm{7-6};
+}
+
+//===----------------------------------------------------------------------===//
+// Register-Based Loads and Stores
+//===----------------------------------------------------------------------===//
+
+def CLW  : Reg_Load<0b010, "c.lw", load, GPRC>, Requires<[HasStdExtC]> {
+  bits<7> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6} = imm{2};
+  let Inst{5} = imm{6};
+}
+
+def CSW  : Reg_Store<0b110, "c.sw", store, GPRC>,
+           Requires<[HasStdExtC]> {
+  bits<7> imm;
+  let Inst{12-10} = imm{5-3};
+  let Inst{6} = imm{2};
+  let Inst{5} = imm{6};
+}

lib/Target/RISCV/RISCVRegisterInfo.td

def GPR : RegisterClass<"RISCV", [XLenVT], 32, (add
     (sequence "X%u", 8, 9),
     (sequence "X%u", 18, 27),
     (sequence "X%u", 0, 4)
   )> {
   let RegInfos = RegInfoByHwMode<
       [RV32,              RV64,              DefaultMode],
       [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
 }
+
+def GPRC : RegisterClass<"RISCV", [XLenVT], 32, (add
+    (sequence "X%u", 10, 15),
+    (sequence "X%u", 8, 9)
+  )> {
+  let RegInfos = RegInfoByHwMode<
+      [RV32,              RV64,              DefaultMode],
+      [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
+}
+
+def SP : RegisterClass<"RISCV", [XLenVT], 32, (add X2)> {
+  let RegInfos = RegInfoByHwMode<
+      [RV32,              RV64,              DefaultMode],
+      [RegInfo<32,32,32>, RegInfo<64,64,64>, RegInfo<32,32,32>]>;
+}

lib/Target/RISCV/RISCVSubtarget.h

 
 namespace llvm {
 class StringRef;
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
   virtual void anchor();
   bool HasStdExtM = false;
   bool HasStdExtA = false;
+  bool HasStdExtC = false;
   bool HasRV64 = false;
   unsigned XLen = 32;
   MVT XLenVT = MVT::i32;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
   SelectionDAGTargetInfo TSInfo;
public:
   const RISCVTargetLowering *getTargetLowering() const override {
     return &TLInfo;
   }
   const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
     return &TSInfo;
   }
   bool hasStdExtM() const { return HasStdExtM; }
   bool hasStdExtA() const { return HasStdExtA; }
+  bool hasStdExtC() const { return HasStdExtC; }
   bool is64Bit() const { return HasRV64; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
 };
 } // End llvm namespace
 
 #endif

test/MC/RISCV/compressed-invalid.s

+# RUN: not llvm-mc -mattr=+c < %s 2>&1 | FileCheck %s
+
+## GPRC
+c.lw  ra, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+c.sw  sp, 4(sp) # CHECK: :[[@LINE]]:7: error: invalid operand for instruction
+
+# Out of range immediates
+
+## uimm8_lsb00
+c.lwsp  ra, 300(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 252]
+c.swsp  ra, -20(sp) # CHECK: :[[@LINE]]:13: error: immediate must be a multiple of 4 bytes in the range [0, 252]
+## uimm7_lsb00
+c.lw  s0, -4(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]
+c.sw  s0, 130(sp) # CHECK: :[[@LINE]]:11: error: immediate must be a multiple of 4 bytes in the range [0, 124]

test/MC/RISCV/compressed-valid.s

+# RUN: llvm-mc %s -mattr=+c -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -mattr=+c < %s \
+# RUN:     | llvm-objdump -d -mattr=+c - | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: c.lwsp  ra, 12(sp)
+# CHECK: encoding: [0xb2,0x40]
+c.lwsp  ra, 12(sp)
+# CHECK-INST: c.swsp  ra, 12(sp)
+# CHECK: encoding: [0x06,0xc6]
+c.swsp  ra, 12(sp)
+# CHECK-INST: c.lw    a2, 4(a0)
+# CHECK: encoding: [0x50,0x41]
+c.lw    a2, 4(a0)
+# CHECK-INST: c.sw    a5, 8(a3)
+# CHECK: encoding: [0x9c,0xc6]
+c.sw    a5, 8(a3)