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CodeGen: Fix TargetLowering::LowerCallTo for sret value type
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Authored by yaxunl on Nov 13 2017, 8:18 PM.

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Reviewers

rampitec
arsenm

Commits

rG0b2f73fd84ca: CodeGen: Fix TargetLowering::LowerCallTo for sret value type
rL318167: CodeGen: Fix TargetLowering::LowerCallTo for sret value type

Summary

TargetLowering::LowerCallTo assumes that sret value type corresponds to a
pointer in default address space, which is incorrect, since sret value type
should correspond to a pointer in alloca address space, which may not
be the default address space. This causes assertion for amdgcn target
in amdgiz environment.

This patch fixes that.

Diff Detail

Event Timeline

yaxunl created this revision.Nov 13 2017, 8:18 PM

Herald added subscribers: inglorion, mehdi_amini, nhaehnle, wdng. · View Herald TranscriptNov 13 2017, 8:18 PM

LGTM

This revision is now accepted and ready to land.Nov 13 2017, 10:08 PM

Closed by commit rL318167: CodeGen: Fix TargetLowering::LowerCallTo for sret value type (authored by yaxunl). · Explain WhyNov 14 2017, 10:47 AM

This revision was automatically updated to reflect the committed changes.

Revision Contents

Path

Size

lib/

CodeGen/

SelectionDAG/

SelectionDAGBuilder.cpp

2 lines

test/

CodeGen/

AMDGPU/

call-return-types.ll

6 lines

Diff 122769

lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

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	}			}
	#endif			#endif

	SmallVector<SDValue, 4> ReturnValues;			SmallVector<SDValue, 4> ReturnValues;
	if (!CanLowerReturn) {			if (!CanLowerReturn) {
	// The instruction result is the result of loading from the			// The instruction result is the result of loading from the
	// hidden sret parameter.			// hidden sret parameter.
	SmallVector<EVT, 1> PVTs;			SmallVector<EVT, 1> PVTs;
	Type *PtrRetTy = PointerType::getUnqual(OrigRetTy);			Type *PtrRetTy = OrigRetTy->getPointerTo(DL.getAllocaAddrSpace());

	ComputeValueVTs(*this, DL, PtrRetTy, PVTs);			ComputeValueVTs(*this, DL, PtrRetTy, PVTs);
	assert(PVTs.size() == 1 && "Pointers should fit in one register");			assert(PVTs.size() == 1 && "Pointers should fit in one register");
	EVT PtrVT = PVTs[0];			EVT PtrVT = PVTs[0];

	unsigned NumValues = RetTys.size();			unsigned NumValues = RetTys.size();
	ReturnValues.resize(NumValues);			ReturnValues.resize(NumValues);
	SmallVector<SDValue, 4> Chains(NumValues);			SmallVector<SDValue, 4> Chains(NumValues);
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test/CodeGen/AMDGPU/call-return-types.ll

	; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s			; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s
	; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s			; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=hawaii -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s
	; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s			; RUN: llc -mtriple=amdgcn-amd-amdhsa-amdgiz -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s

	declare void @external_void_func_void() #0			declare void @external_void_func_void() #0

	declare i1 @external_i1_func_void() #0			declare i1 @external_i1_func_void() #0
	declare zeroext i1 @external_i1_zeroext_func_void() #0			declare zeroext i1 @external_i1_zeroext_func_void() #0
	declare signext i1 @external_i1_signext_func_void() #0			declare signext i1 @external_i1_signext_func_void() #0

	declare i8 @external_i8_func_void() #0			declare i8 @external_i8_func_void() #0
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