[X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class

[RKSimon]

Summary

Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default.

[gadi.haber]

Note that WriteALU means 1 cycle latency using Port 0156

This is true for CBW, CDQE and CWDE.
However, CQO and CDQ do not use port0156 and CWD takes 2 cycles and 2 ports.
See below:

iform: , latency: ports:
XED_IFORM_CBW 1 0156
XED_IFORM_CDQE 1 0156
XED_IFORM_CWDE 1 0156

XED_IFORM_CQO 1 06
XED_IFORM_CDQ 1 06

XED_IFORM_CWD 2 06, 0156

[RKSimon]

So do you want me add a fix for the SB model? What about the SLM are you happy with it using the defaults?

[gadi.haber]

yes. SLM is good enough

[RKSimon]

Added SandyBridge tweak

[RKSimon]

@gadi.haber Does that match what you were after? IIRC you auto-generate X86SchedSandyBridge.td - will my edit cause a problem?

[gadi.haber]

Ah you're right. For SNB this is fine.
My comment was for HSW. Sorry.

lib/Target/X86/X86InstrExtension.td

 //===-- X86InstrExtension.td - Sign and Zero Extensions ----*- tablegen -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
 // This file is distributed under the University of Illinois Open Source
 // License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
 // This file describes the sign and zero extension operations.
 //
 //===----------------------------------------------------------------------===//
 
 let hasSideEffects = 0 in {
-  let Defs = [AX], Uses = [AL] in
+  let Defs = [AX], Uses = [AL] in // AX = signext(AL)
   def CBW : I<0x98, RawFrm, (outs), (ins),
-              "{cbtw|cbw}", [], IIC_CBW>, OpSize16;  // AX = signext(AL)
-  let Defs = [EAX], Uses = [AX] in
+              "{cbtw|cbw}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+  let Defs = [EAX], Uses = [AX] in // EAX = signext(AX)
   def CWDE : I<0x98, RawFrm, (outs), (ins),
-              "{cwtl|cwde}", [], IIC_CBW>, OpSize32; // EAX = signext(AX)
+              "{cwtl|cwde}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
 
-  let Defs = [AX,DX], Uses = [AX] in
+  let Defs = [AX,DX], Uses = [AX] in // DX:AX = signext(AX)
   def CWD : I<0x99, RawFrm, (outs), (ins),
-              "{cwtd|cwd}", [], IIC_CBW>, OpSize16; // DX:AX = signext(AX)
-  let Defs = [EAX,EDX], Uses = [EAX] in
+              "{cwtd|cwd}", [], IIC_CBW>, OpSize16, Sched<[WriteALU]>;
+  let Defs = [EAX,EDX], Uses = [EAX] in // EDX:EAX = signext(EAX)
   def CDQ : I<0x99, RawFrm, (outs), (ins),
-              "{cltd|cdq}", [], IIC_CBW>, OpSize32; // EDX:EAX = signext(EAX)
+              "{cltd|cdq}", [], IIC_CBW>, OpSize32, Sched<[WriteALU]>;
 
 
-  let Defs = [RAX], Uses = [EAX] in
+  let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
   def CDQE : RI<0x98, RawFrm, (outs), (ins),
-               "{cltq|cdqe}", [], IIC_CBW>;     // RAX = signext(EAX)
+               "{cltq|cdqe}", [], IIC_CBW>, Sched<[WriteALU]>;
 
-  let Defs = [RAX,RDX], Uses = [RAX] in
+  let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
   def CQO  : RI<0x99, RawFrm, (outs), (ins),
-                "{cqto|cqo}", [], IIC_CBW>; // RDX:RAX = signext(RAX)
+                "{cqto|cqo}", [], IIC_CBW>, Sched<[WriteALU]>;
 }
 
-
-
 // Sign/Zero extenders
 let hasSideEffects = 0 in {
 def MOVSX16rr8 : I<0xBE, MRMSrcReg, (outs GR16:$dst), (ins GR8:$src),
                    "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_R8>,
                    TB, OpSize16, Sched<[WriteALU]>;
 let mayLoad = 1 in
 def MOVSX16rm8 : I<0xBE, MRMSrcMem, (outs GR16:$dst), (ins i8mem:$src),
                    "movs{bw|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVSX_R16_M8>,

lib/Target/X86/X86SchedSandyBridge.td

 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLQrr")>;
 def: InstRW<[SBWriteResGroup14], (instregex "VPSRLWrr")>;
 
 def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
+def: InstRW<[SBWriteResGroup15], (instregex "CWD")>;
 def: InstRW<[SBWriteResGroup15], (instregex "FNSTSW16r")>;
 
 def SBWriteResGroup16 : SchedWriteRes<[SBPort1,SBPort05]> {
   let Latency = 2;
   let NumMicroOps = 2;
   let ResourceCycles = [1,1];
 }
 def: InstRW<[SBWriteResGroup16], (instregex "BSWAP(16|32|64)r")>;

test/CodeGen/X86/schedule-x86_64.ll

 define void @test_cbw_cdq_cdqe_cqo_cwd_cwde() optsize {
 ; GENERIC-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
 ; GENERIC:       # BB#0:
 ; GENERIC-NEXT:    #APP
 ; GENERIC-NEXT:    cbtw # sched: [1:0.33]
 ; GENERIC-NEXT:    cltd # sched: [1:0.50]
 ; GENERIC-NEXT:    cltq # sched: [1:0.50]
 ; GENERIC-NEXT:    cqto # sched: [1:0.50]
-; GENERIC-NEXT:    cwtd
+; GENERIC-NEXT:    cwtd # sched: [2:1.00]
 ; GENERIC-NEXT:    cwtl # sched: [1:0.33]
 ; GENERIC-NEXT:    #NO_APP
 ; GENERIC-NEXT:    retq # sched: [1:1.00]
 ;
 ; ATOM-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
 ; ATOM:       # BB#0:
 ; ATOM-NEXT:    #APP
 ; ATOM-NEXT:    cbtw # sched: [4:2.00]
 ; ATOM-NEXT:    cltd # sched: [4:2.00]
 ; ATOM-NEXT:    cltq # sched: [4:2.00]
 ; ATOM-NEXT:    cqto # sched: [4:2.00]
 ; ATOM-NEXT:    cwtd # sched: [4:2.00]
 ; ATOM-NEXT:    cwtl # sched: [4:2.00]
 ; ATOM-NEXT:    #NO_APP
 ; ATOM-NEXT:    retq # sched: [79:39.50]
 ;
 ; SLM-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
 ; SLM:       # BB#0:
 ; SLM-NEXT:    #APP
-; SLM-NEXT:    cbtw
-; SLM-NEXT:    cltd
-; SLM-NEXT:    cltq
-; SLM-NEXT:    cqto
-; SLM-NEXT:    cwtd
-; SLM-NEXT:    cwtl
+; SLM-NEXT:    cbtw # sched: [1:0.50]
+; SLM-NEXT:    cltd # sched: [1:0.50]
+; SLM-NEXT:    cltq # sched: [1:0.50]
+; SLM-NEXT:    cqto # sched: [1:0.50]
+; SLM-NEXT:    cwtd # sched: [1:0.50]
+; SLM-NEXT:    cwtl # sched: [1:0.50]
 ; SLM-NEXT:    #NO_APP
 ; SLM-NEXT:    retq # sched: [4:1.00]
 ;
 ; SANDY-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
 ; SANDY:       # BB#0:
 ; SANDY-NEXT:    #APP
 ; SANDY-NEXT:    cbtw # sched: [1:0.33]
 ; SANDY-NEXT:    cltd # sched: [1:0.50]
 ; SANDY-NEXT:    cltq # sched: [1:0.50]
 ; SANDY-NEXT:    cqto # sched: [1:0.50]
-; SANDY-NEXT:    cwtd
+; SANDY-NEXT:    cwtd # sched: [2:1.00]
 ; SANDY-NEXT:    cwtl # sched: [1:0.33]
 ; SANDY-NEXT:    #NO_APP
 ; SANDY-NEXT:    retq # sched: [1:1.00]
 ;
 ; HASWELL-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
 ; HASWELL:       # BB#0:
 ; HASWELL-NEXT:    #APP
 ; HASWELL-NEXT:    cbtw # sched: [1:0.25]

 ; SKX-NEXT:    cwtd # sched: [2:0.50]
 ; SKX-NEXT:    cwtl # sched: [1:0.25]
 ; SKX-NEXT:    #NO_APP
 ; SKX-NEXT:    retq # sched: [7:1.00]
 ;
 ; BTVER2-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
 ; BTVER2:       # BB#0:
 ; BTVER2-NEXT:    #APP
-; BTVER2-NEXT:    cbtw
-; BTVER2-NEXT:    cltd
-; BTVER2-NEXT:    cltq
-; BTVER2-NEXT:    cqto
-; BTVER2-NEXT:    cwtd
-; BTVER2-NEXT:    cwtl
+; BTVER2-NEXT:    cbtw # sched: [1:0.50]
+; BTVER2-NEXT:    cltd # sched: [1:0.50]
+; BTVER2-NEXT:    cltq # sched: [1:0.50]
+; BTVER2-NEXT:    cqto # sched: [1:0.50]
+; BTVER2-NEXT:    cwtd # sched: [1:0.50]
+; BTVER2-NEXT:    cwtl # sched: [1:0.50]
 ; BTVER2-NEXT:    #NO_APP
 ; BTVER2-NEXT:    retq # sched: [4:1.00]
 ;
 ; ZNVER1-LABEL: test_cbw_cdq_cdqe_cqo_cwd_cwde:
 ; ZNVER1:       # BB#0:
 ; ZNVER1-NEXT:    #APP
-; ZNVER1-NEXT:    cbtw
-; ZNVER1-NEXT:    cltd
-; ZNVER1-NEXT:    cltq
-; ZNVER1-NEXT:    cqto
-; ZNVER1-NEXT:    cwtd
-; ZNVER1-NEXT:    cwtl
+; ZNVER1-NEXT:    cbtw # sched: [1:0.25]
+; ZNVER1-NEXT:    cltd # sched: [1:0.25]
+; ZNVER1-NEXT:    cltq # sched: [1:0.25]
+; ZNVER1-NEXT:    cqto # sched: [1:0.25]
+; ZNVER1-NEXT:    cwtd # sched: [1:0.25]
+; ZNVER1-NEXT:    cwtl # sched: [1:0.25]
 ; ZNVER1-NEXT:    #NO_APP
 ; ZNVER1-NEXT:    retq # sched: [1:0.50]
   tail call void asm "cbw \0A\09 cdq \0A\09 cdqe \0A\09 cqo \0A\09 cwd \0A\09 cwde", ""() nounwind
   ret void
 }
 
 define void @test_clc_cld_cmc() optsize {
 ; GENERIC-LABEL: test_clc_cld_cmc: