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[X86] Add CBW/CDQ/CDQE/CQO/CWD/CWDE to WriteALU schedule class
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Authored by RKSimon on Nov 10 2017, 5:36 AM.

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Summary

Some CPUs are already overriding these sign extension instructions but we should be able to use the WriteALU schedule class by default.

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rL LLVM

Event Timeline

RKSimon created this revision.Nov 10 2017, 5:36 AM
gadi.haber edited edge metadata.Nov 13 2017, 12:24 AM

Note that WriteALU means 1 cycle latency using Port 0156

This is true for CBW, CDQE and CWDE.
However, CQO and CDQ do not use port0156 and CWD takes 2 cycles and 2 ports.
See below:

iform: , latency: ports:
XED_IFORM_CBW 1 0156
XED_IFORM_CDQE 1 0156
XED_IFORM_CWDE 1 0156

XED_IFORM_CQO 1 06
XED_IFORM_CDQ 1 06

XED_IFORM_CWD 2 06, 0156

So do you want me add a fix for the SB model? What about the SLM are you happy with it using the defaults?

yes. SLM is good enough

RKSimon updated this revision to Diff 122670.Nov 13 2017, 8:51 AM

Added SandyBridge tweak

@gadi.haber Does that match what you were after? IIRC you auto-generate X86SchedSandyBridge.td - will my edit cause a problem?

Ah you're right. For SNB this is fine.
My comment was for HSW. Sorry.

gadi.haber accepted this revision.Nov 15 2017, 6:02 AM
This revision is now accepted and ready to land.Nov 15 2017, 6:02 AM
This revision was automatically updated to reflect the committed changes.